JP2004061368A - Semiconductor integrated circuit testing system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit testing system which effectively tests a semiconductor integrated circuit by applying different test patterns to objects under test arranged in parallel without inviting large increase in cost of the system and a method. <P>SOLUTION: A pattern generator 10 generates a test pattern to be applied to the semiconductor integrated circuits 30a-30n, and a distributor 13 distributes patterns S1 generated by the generator 10 and outputs them as patterns S4a-S4n. A memory 19 stores test patterns corresponding to test results obtained by applying the same patterns S4a-S4n to the circuits 30a-30n. Selection circuits 15a-15n select and output either the patterns S4a-S4n outputted by the distributor 13 or the patterns S5a-S5n stored in the memory 19. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit test apparatus and method configured to be able to test a plurality of test objects in parallel.
[0002]
[Prior art]
As is well known, a semiconductor integrated circuit test apparatus (so-called IC tester) matches a signal obtained by applying a test pattern to a semiconductor integrated circuit to be tested and a predetermined expected value (path). ) Or not (fail), the semiconductor integrated circuit is tested for non-defective products or defective products. In testing a semiconductor integrated circuit, a plurality of semiconductor integrated circuits are tested in parallel in order to improve test efficiency.
[0003]
In order to test a plurality of semiconductor integrated circuits in parallel, the same test pattern is distributed and applied simultaneously to each of the plurality of semiconductor integrated circuits, and a signal obtained from each semiconductor integrated circuit and a predetermined expectation The values are compared for each semiconductor integrated circuit, and a pass / fail is determined according to the comparison result, and a non-defective product or a defective product of each semiconductor integrated circuit is tested. Thus, the test efficiency can be improved as the parallel number of the semiconductor integrated circuits to be tested is increased.
[0004]
[Problems to be solved by the invention]
By the way, in the test of the semiconductor integrated circuit, when it is known in advance that the test pattern applied to all the semiconductor integrated circuits is the same, the same test is performed on the semiconductor integrated circuits provided in parallel as described above. Patterns can be distributed and applied simultaneously.
[0005]
However, a test of a semiconductor integrated circuit includes a test that feeds back a test result in consideration of a test result of a test once performed on the semiconductor integrated circuit. For example, a semiconductor integrated circuit such as a flash memory recognizes defects up to a certain amount for improving the yield, and writes information related to the defective area to the normal area in the same semiconductor integrated circuit as defect information data. The defect information data is read out so that the defect area is not used.
[0006]
However, since the defect information data is different for each semiconductor integrated circuit, and the normal area where the defect information data is written is also different, it is necessary to feed back and test the test results for each semiconductor integrated circuit. The above-described test in which the same pattern is simultaneously applied to all integrated circuits cannot be performed.
[0007]
For this purpose, conventionally, only one semiconductor integrated circuit to which a test pattern is applied is selected at a time, and a pass / fail is determined by applying a test pattern corresponding to a test result previously performed on the selected semiconductor integrated circuit. It is necessary to perform the operation for the semiconductor integrated circuits provided in parallel. In other words, in the test method for selecting and testing a semiconductor integrated circuit, it is necessary to test each semiconductor integrated circuit in order, which requires a long time for the test and is extremely inefficient. .
[0008]
In order to solve the above problem, if a circuit for generating a test pattern is provided corresponding to a semiconductor integrated circuit provided in parallel, different test patterns can be simultaneously applied to a plurality of semiconductor integrated circuits. However, there is a problem that the scale of the apparatus increases and the cost increases.
[0009]
The present invention has been made in view of the above circumstances, and can efficiently apply different test patterns to test objects provided in parallel without incurring a significant increase in the cost of the apparatus. An object of the present invention is to provide a semiconductor integrated circuit test apparatus and method capable of testing an integrated circuit.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit test apparatus according to the present invention is a semiconductor integrated circuit test apparatus that performs a test by applying a test pattern to test objects (30a to 30n) provided in parallel. A storage unit (19) for storing a second test pattern corresponding to a test result obtained by simultaneously applying the same first test pattern to the test target, for each test target, and the storage unit On the other hand, a read signal output unit (20) for outputting a read signal for simultaneously outputting the stored second test pattern for each object to be tested and either the first test pattern or the second test pattern are selected. And a selection unit (15a to 15n) to be applied to the object to be tested.
According to this invention, the memory | storage part which memorize | stores for every to-be-tested object the 2nd test pattern according to the test result obtained by applying the same 1st test pattern simultaneously to the to-be-tested object provided in parallel The second test pattern is read from the storage unit and applied to the object under test at the same time, so that it differs from the object under test provided in parallel without significantly increasing the cost of the apparatus. A test pattern can be applied, and a semiconductor integrated circuit can be efficiently tested.
The semiconductor integrated circuit test apparatus according to the present invention further includes a pattern generator (10) that generates a pattern that is a source of the first test pattern, and a timing signal that generates a timing signal that defines a timing of the first pattern. A waveform shaper (12) for shaping a pattern output from the pattern generator based on a timing signal output from the timing signal generator, and a pattern shaped by the waveform shaper. And a distributor (13) that distributes the portion to be tested to the first test pattern.
The semiconductor integrated circuit test apparatus of the present invention receives the second test pattern output from the storage unit and the output of the distributor, and inputs the second test pattern based on the signal output from the distributor. And a shaper (14a to 14n) that outputs the result to the selection unit.
Furthermore, the semiconductor integrated circuit test apparatus of the present invention is characterized in that when the pattern generator applies the second test pattern to the test object, a pattern having a constant value is generated.
In order to solve the above-described problems, a semiconductor integrated circuit test method of the present invention is a semiconductor integrated circuit test method for performing a test by applying a test pattern to a test object provided in parallel. A first test step for performing a test by simultaneously applying the same first test pattern to the test, and a memory for storing a second test pattern corresponding to the test result obtained in the first test step for each object to be tested And a second test step of performing a test by applying a second test pattern for each test object individually and simultaneously for each test object.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor integrated circuit test apparatus and method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor integrated circuit test apparatus according to an embodiment of the present invention is configured such that each constituent circuit is connected to a low-speed bus B and parallel data can be transferred. Note that a control device (not shown) for controlling the operation of the semiconductor integrated circuit testing device is connected to the bus B, and the operation of each unit is performed based on a control signal output from the control device via the bus B. Set and controlled.
[0012]
In FIG. 1, a pattern generator 10 generates a common pattern (first test pattern) S1 to be applied to semiconductor integrated circuits 30a to 30n as an object to be tested. In the present specification and drawings, the variable n is the number of semiconductor integrated circuits 30a to 30n. The timing signal generator 11 generates a timing signal S2 that defines the timing of the pattern output from the pattern generator 10. Since the pattern output from the pattern generator 10 is a pattern composed of a plurality of bits, the timing signal S2 is required to define the timing between each bit. The type of timing signal output from the timing signal generator 11 is set according to a control signal output from a control device (not shown).
[0013]
The waveform shaper 12 shapes the pattern S1 output from the pattern generator 10 based on the timing signal S2 output from the timing signal generator 11, and outputs a pattern S3. The waveform shaper 12 is configured using, for example, a flip-flop. Whether the waveform shaper 12 performs waveform shaping so as to output an NRZ (non-return-zero) signal each time a timing signal is input in response to a control signal output from a control device (not shown). Alternatively, waveform shaping is performed so that an RZ (return zero) signal is output each time a timing signal is input.
[0014]
The distributor 13 outputs patterns S4a to S4n obtained by distributing the pattern shaped by the waveform shaper 12 by n. Further, the waveform shapers 14a to 14n shape the waveforms (second test patterns) S5a to S5n output from the memory 19 described later based on the signals output from the distributor 13, and the patterns S6a to S6n. Output. The waveform shapers 14a to 14n correspond to the shapers referred to in the present invention. The waveform shapers 14a to 14n are configured using, for example, flip-flops.
[0015]
The selection circuits 15a to 15n select any one of the patterns (first test patterns) S4a to S4n distributed by the distributor 13 or the patterns (second test patterns) S6a to S6n output from the waveform shapers 14a to 14n. This is selected and output, and corresponds to the selection section referred to in the present invention. The driver circuits 16a to 16n apply the patterns respectively output from the selection circuits 15a to 15n to the semiconductor integrated circuits 30a to 30n as test objects.
The determination circuits 17a to 17n compare a signal obtained when a test pattern is applied to the semiconductor integrated circuits 30a to 30n with a predetermined expected value, and perform a pass / fail determination for each of the semiconductor integrated circuits 30a to 30n. Do. The device data detector 18 collects defect information of the semiconductor integrated circuits 30a to 30n based on the determination results of the determination circuits 17a to 17n. Also, based on this defect information, a test pattern (second test pattern) used when individually testing the semiconductor integrated circuits 30a to 30n is generated.
[0017]
The memory 19 stores the test pattern generated by the device data detector 18 for each semiconductor integrated circuit. That is, the memory 19 stores a test pattern according to a test result obtained by simultaneously applying the same test pattern (first test pattern) to the semiconductor integrated circuits 30a to 30n. The memory 19 has a capacity for storing at least n-bit test patterns. The counter 20 outputs an address (read signal) for reading the test pattern stored in the memory 19 and an address for writing the test pattern to the memory 19. The memory 19 corresponds to a storage unit according to the present invention, and the counter 20 corresponds to a read signal output unit according to the present invention. The semiconductor integrated circuit test apparatus having the above configuration operates in synchronization with a system clock (not shown).
[0018]
Next, the operation of the semiconductor integrated circuit according to the embodiment of the present invention will be described. First, the operation in the case where the same test pattern is simultaneously applied to the semiconductor integrated circuits 30a to 30n for testing will be described. FIG. 2 is a timing chart showing an example of a waveform pattern in the semiconductor integrated circuit test apparatus when the same test pattern is simultaneously applied to the semiconductor integrated circuits 30a to 30n for testing. Note that T in FIG. 2 indicates one cycle of the system clock.
[0019]
When performing this test, a control device (not shown) sets the timing signal generator 11 so as to generate a timing signal only once in one cycle of the system clock, and performs timing for the waveform shaper 12. The NRZ (non-return-zero) signal is set to be output every time the signal S2 is input. The selection circuits 15a to 15n are set to select and output the patterns S4a to S4n.
[0020]
When the pattern generator 10 outputs the pattern S1 shown in FIG. 2 and the timing signal generator 11 outputs the timing signal S2 shown in FIG. 2, the waveform shaper 12 outputs a pattern S3 obtained by shaping the pattern S1. . A control device (not shown) outputs an expected value determined in advance according to the pattern output from the pattern generator 10 to the determination circuits 17a to 17n. Referring to FIG. 2, it can be seen that the pattern S3 is a waveform in which the level of the pattern S1 at the time when the timing signal S2 is input is maintained for one cycle of the system clock.
[0021]
The pattern S3 output from the waveform shaper 12 is output to the distributor 13 and distributed n times. The distributed patterns are output from the distributor 13 as patterns S4a to S4n, and are simultaneously applied to the semiconductor integrated circuits 30a to 30n via the selection circuits 15a to 15n and the driver circuits 16a to 16n, respectively. When a test pattern is applied to the semiconductor integrated circuits 30a to 30n, signals corresponding to the applied test pattern are output from the semiconductor integrated circuits 30a to 30n, respectively.
[0022]
Signals output from the semiconductor integrated circuits 30a to 30n are input to the determination circuits 17a to 17n, respectively. The determination circuits 17a to 17n compare a signal output from the semiconductor integrated circuits 30a to 30n with an expected value output in advance from a control device (not shown) to determine pass / fail. This determination result is output to the device data detector 18. The step of performing the test by simultaneously applying the same test pattern described above to the semiconductor integrated circuits 30a to 30n corresponds to the first test step according to the present invention.
[0023]
When the above operation is completed, the device data detector 18 collects defect information of the semiconductor integrated circuits 30a to 30n based on the obtained test results, and based on the defect information, the device data detector 18 applies to the semiconductor integrated circuits 30a to 30n. Thus, a test pattern (second test pattern) used when individually testing is generated. The test pattern is transferred to the memory 19 via the bus B and stored. Since the data transfer from the device data detector 18 to the memory 19 via the bus B is performed at a low speed, the counter 20 writes the write address at a timing corresponding to the transfer speed of the bus B (a timing slower than the system clock). Is output. The operation of storing the test pattern in the memory 19 corresponds to a storage step according to the present invention.
[0024]
Next, an operation in the case of performing a test by feeding back the above test results will be described. FIG. 3 is a timing chart showing an example of a waveform pattern in the semiconductor integrated circuit test apparatus when different test patterns are simultaneously applied to the semiconductor integrated circuits 30a to 30n for testing. Note that T in FIG. 3 indicates one cycle of the system clock.
[0025]
When performing this test, a control device (not shown) is set to output a pattern S1 having a constant value to the pattern generator 10, and is set to one cycle of the system clock with respect to the timing signal generator 11. The timing signal is set to be generated twice, and the RZ (return zero) signal is set to be output every time the timing signal S2 is input to the waveform shaper 12. The selection circuits 15a to 15n are set so as to select and output the patterns S6a to S6n.
[0026]
When the pattern generator 10 outputs the pattern S1 having a constant value shown in FIG. 3 and the timing signal generator 11 outputs the timing signal S2 shown in FIG. 3, the waveform shaper 12 is a pattern obtained by waveform shaping the pattern S1. S3 is output. Even when a test is performed in which a test pattern is simultaneously applied to each of the semiconductor integrated circuits 30a to 30n, the control device (not shown) has an expected value that is determined in advance according to the pattern output from the pattern generator 10. Is output to the determination circuits 17a to 17n.
[0027]
Referring to FIG. 3, it can be seen that the pattern S3 output from the waveform shaper 12 changes in value every time the timing signal S2 is input. The pattern S3 is output to the distributor 13 and distributed n. The distributed patterns are output to the waveform shapers 14a to 14n as patterns S4a to S4n. In parallel with the operations of the pattern generator 10 and the timing signal generator 11, the counter 20 outputs an address for reading the test pattern stored in the memory 19 in synchronization with the system clock.
[0028]
When the address is output from the counter 20, the patterns S5a to S5n stored at the address output from the counter 20 are simultaneously output from the memory 19. In FIG. 3, the pattern S5a and the pattern S5n are shown as representatives, and these are different patterns. The waveform shapers 14a to 14n shape the patterns S5a to S5n output from the memory 19 based on the patterns S4a to S4n output from the distributor 13, and output the patterns S6a to S6n to the selection circuits 15a to 15n, respectively. .
[0029]
The patterns S6a to S6n output from the waveform shapers 14a to 14n are simultaneously applied to the semiconductor integrated circuits 30a to 30n via the selection circuits 15a to 15n and the driver circuits 16a to 16n, respectively. When a test pattern is applied to the semiconductor integrated circuits 30a to 30n, signals corresponding to the applied test pattern are output from the semiconductor integrated circuits 30a to 30n, respectively.
[0030]
Signals output from the semiconductor integrated circuits 30a to 30n are input to the determination circuits 17a to 17n, respectively. The determination circuits 17a to 17n compare a signal output from the semiconductor integrated circuits 30a to 30n with an expected value output in advance from a control device (not shown) to determine pass / fail. This determination result is output to the device data detector 18. The step of performing the test by simultaneously applying the different test patterns described above to the semiconductor integrated circuits 30a to 30n corresponds to the second test step in the present invention.
[0031]
As described above, even when the test patterns applied to the semiconductor integrated circuits 30a to 30n are the same or different from each other, the test patterns are almost simultaneously applied to the semiconductor integrated circuits 30a to 30n. Since the test is performed by being applied, the test can be efficiently performed on the test target provided in parallel. Further, as shown in FIG. 1, in the present embodiment, the same test pattern and different test patterns are simultaneously applied to the semiconductor integrated circuits 30a to 30n without complicating the apparatus configuration and increasing the cost. be able to.
[0032]
The semiconductor integrated circuit test apparatus and method according to the embodiment of the present invention have been described above. However, the present invention is not limited to the above embodiment, and can be freely modified within the scope of the present invention. For example, in the above embodiment, the memory 19 is provided to store the test pattern (second test pattern). However, the present invention is not limited to the memory, and may be configured to include a storage device such as a register or a hard disk.
[0033]
【The invention's effect】
As described above, according to the present invention, the second test pattern corresponding to the test result obtained by simultaneously applying the same first test pattern to the test target provided in parallel is obtained. Since the second test pattern is read out from the storage unit and applied to the test target at the same time, the test target provided in parallel can be provided without causing a significant increase in the cost of the apparatus. Different test patterns can be applied to the test object, and the semiconductor integrated circuit can be efficiently tested.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an example of a waveform pattern in the semiconductor integrated circuit test apparatus when the same test pattern is simultaneously applied to the semiconductor integrated circuits 30a to 30n for testing.
FIG. 3 is a timing chart showing an example of a waveform pattern in a semiconductor integrated circuit test apparatus when different test patterns are simultaneously applied to each of the semiconductor integrated circuits 30a to 30n for testing.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Pattern generator 11 Timing signal generator 12 Waveform shaper 13 Dividers 15a-15n Selection circuit (selection part)
19 Memory (storage unit)
20 counter (read signal output unit)
30a-30n semiconductor integrated circuit (object under test)

Claims (5)

A semiconductor integrated circuit test apparatus for performing a test by applying a test pattern to an object to be tested provided in parallel,
A storage unit for storing a second test pattern according to a test result obtained by simultaneously applying the same first test pattern to the test target;
A readout signal output unit for outputting a readout signal for simultaneously outputting the stored second test pattern for each object to be tested to the storage unit;
A semiconductor integrated circuit test apparatus comprising: a selection unit that selects either the first test pattern or the second test pattern and applies the selected test pattern to the test target. A pattern generator for generating a pattern that is the basis of the first test pattern;
A timing signal generator for generating a timing signal defining the timing of the first pattern;
A waveform shaper that shapes a pattern output from the pattern generator based on a timing signal output from the timing signal generator;
2. The semiconductor integrated circuit test apparatus according to claim 1, further comprising a distributor that distributes the pattern shaped by the waveform shaper by an amount corresponding to the object to be tested to form the first test pattern. A shaper that receives the second test pattern output from the storage unit and the output of the distributor, shapes the second test pattern based on a signal output from the distributor, and outputs the second test pattern to the selection unit The semiconductor integrated circuit test apparatus according to claim 2, further comprising: 4. The semiconductor integrated circuit test apparatus according to claim 3, wherein the pattern generator generates a pattern having a constant value when the second test pattern is applied to the test object. A semiconductor integrated circuit test method for performing a test by applying a test pattern to an object to be tested provided in parallel,
A first test step in which a test is performed by simultaneously applying the same first test pattern to the test object;
Storing a second test pattern corresponding to the test result obtained in the first test step for each of the test objects;
And a second test step of performing a test by applying a second test pattern for each test target individually and simultaneously for each test target.

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