JP5003953B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus for measuring a plurality of devices under test in parallel, and in particular, in a waveform generation circuit of an IC tester, a PSR memory for storing waveform data is arranged for each system pin, and a test pattern waveform for each DUT. The present invention relates to a semiconductor test apparatus capable of applying a signal (hereinafter referred to as a waveform).

  In a semiconductor test apparatus, a signal obtained by applying a test pattern waveform to a device under test such as an IC group to be tested (hereinafter referred to as DUT) matches a predetermined expected value. By determining whether (Pass) or not (Fail), a non-defective product or a defective product of the DUT to be tested is tested. In order to improve test efficiency, a semiconductor test apparatus performs tests on a plurality of DUTs in parallel.

In a DUT test, when it is known in advance that the test pattern waveforms applied to all the DUTs are the same, the same test pattern waveforms may be distributed and applied simultaneously to the DUTs provided in parallel. .

However, a test of a semiconductor integrated circuit includes a test that feeds back a test result in consideration of a test result of a test once performed on the semiconductor integrated circuit. For example, a semiconductor integrated circuit such as a flash memory recognizes defects up to a certain amount for improving the yield, and writes information related to the defective area to the normal area in the same semiconductor integrated circuit as defect information data. The defect information data is read out so that the defect area is not used.

However, since the defect information data is different for each semiconductor integrated circuit, and the normal area where the defect information data is written is also different, it is necessary to feed back and test the test results for each semiconductor integrated circuit. A test in which the same pattern waveform is simultaneously applied to all integrated circuits cannot be performed.

Thus, when it is desired to apply individual test pattern waveforms corresponding to each DUT, a circuit for generating an individual test pattern waveform for each DUT is required.
FIG. 3 is a configuration block diagram showing a test waveform application circuit for applying a test pattern waveform to the DUT as an example of such a conventional semiconductor test apparatus.

A test waveform applying circuit including a pattern generator 1, a distributor 2, integrated circuits IC01 and IC02, an integrated circuit IC11, and an integrated circuit IC12 is used for each system pin of each DUT.

The same circuit is mounted inside the integrated circuits IC01 and IC02. Further, A01, A02,... Are mounted inside the integrated circuit IC11, and A11, A12,... Are mounted inside the integrated circuit IC12. Although the case where there are two integrated circuits IC11 and IC12 is shown here, any number is possible.

The pattern data output from the pattern generator 1 is distributed into two by the distributor 2 and sent to the integrated circuits IC01 and C02.

The pattern data input to the integrated circuits IC01 and C02 is shaped into a test pattern waveform by the waveform shaper 4 based on the timing signal output from the timing signal generator 3, and is output from the integrated circuits IC01 and IC02.

The test pattern waveform output from the integrated circuit IC01 is input to the integrated circuit IC11, and the test pattern waveform output from the integrated circuit IC02 is input to the integrated circuit IC12.

  The test pattern waveforms input to the integrated circuits IC11 and IC12 are each adjusted in timing by the timing correction circuit 5 and input to the selection circuits 10 respectively.

Here, the role of the timing correction circuit 5 will be described. The application timings of the test pattern waveforms output from the integrated circuits IC11 and IC12 and applied to each DUT 12 need to match. However, if the line lengths from the output ends of the integrated circuits IC11 and IC12 to the respective DUTs 12 are different, even if the generation timings of the respective test pattern waveforms are the same at the output ends of the integrated circuits IC11 and IC12, they are applied to the respective DUTs 12. The application timing of the test pattern waveform is different.

Therefore, each timing correction circuit 5 has a variation value of the time required for each test pattern waveform output from the output terminals of the integrated circuits IC11 and IC12 to reach each DUT 12 in advance, and each variation time is added. Thus, the timing adjustment is performed so that the application timings of the test pattern waveforms applied to the respective DUTs 12 coincide.

Different test pattern data for each DUT 12 is recorded in the memory 6 (PSR memory).

Further, an exclusive OR (hereinafter referred to as XOR) 7 performs an exclusive OR operation on the test pattern data output from the distributor 2 and the test pattern data output from the memory 6, and a new test is performed. Output pattern data. Here, the reason why the XOR 7 is used is that the test pattern data obtained by inverting the pattern data output from the memory 6 (PSR memory) can be easily obtained using the pattern generated by the pattern generator 1. .

Each selection circuit 8 selects one of the test pattern data output from the distributor 2, the test pattern data generated in the memory 6, and the test pattern data output from the XOR 7.

The waveform shaper 9 generates a test pattern waveform in which the test pattern data output from the selection circuit 8 is shaped according to the timing of the test pattern waveform output from the timing correction circuit 5.

  The selection circuit 10 selects either the test pattern waveform output from the timing correction circuit 5 or the test pattern waveform output from the waveform shaper 9. In other words, which of the test pattern waveform common to each DUT 12 and the individual test pattern waveform is applied is selected here.

  The test pattern waveform output from the selection circuit 10 passes through the drive circuit 11 and is applied to each DUT 12.

  Note that the pattern generator 1 having the above-described configuration has various pattern data, has various calculation functions such as addition / subtraction, multiplication / division, and a scramble function, and has a very large circuit scale. Since the circuit scale becomes enormous if these functions are provided for each pin, the pattern data generator 1 is provided separately from the individual memory 6 (PSR memory).

  Prior art documents related to the semiconductor test apparatus as described above include the following.

JP 2004-61368 A

  However, the conventional apparatus has a redundant circuit configuration in that the waveform shaper 4 and the waveform shaper 9 are doubled, and the circuit scale increases.

Further, between the test pattern waveform S1 output from the timing correction circuit 5 and the test pattern waveform S2 shaped by the waveform shaper 9 at the waveform timing of the test pattern waveform S1 output from the timing correction circuit 5. In this case, timing deviation occurs at the rise / fall of the waveform. That is, an application timing “shift” occurs between each DUT 12 when “a common test pattern waveform S1 is applied” and when a different (ie, individual) test pattern waveform S2 is applied.

  The present invention is intended to solve such a problem, and the test waveform application circuit differs in application timing between when a common test pattern waveform is applied to each DUT and when individual test pattern waveforms are applied. An object of the present invention is to provide a semiconductor test apparatus with a reduced circuit scale.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor test apparatus that performs a parallel test by applying a test pattern waveform to multiple devices under test,
A pattern generator for generating first test pattern data common to each device under measurement;
A storage unit for generating individual second test pattern data for each device under measurement;
A logic circuit that performs a logical operation on the first pattern data generated by the pattern generator and the second pattern data generated by the storage unit;
A first selection circuit for selecting output data of the logic circuit, the first test pattern data, and the second test pattern data, and outputting test pattern data for generating the test pattern waveform;
A waveform shaper for shaping the test pattern data selected by the first selection circuit and outputting the test pattern waveform;
And a timing signal generator for supplying a timing signal to the waveform shaper .

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
The storage unit, the first selection circuit, the logic circuit, and the waveform shaper are mounted and integrated for each DUT pin .

The invention described in claim 3
The semiconductor test apparatus according to claim 1 or 2,
The storage unit includes a memory, and the logic circuit includes an exclusive OR circuit .

The invention according to claim 4
The semiconductor test apparatus according to claim 1 or 2 ,
The storage unit
A plurality of memories for storing different test pattern data;
A second selection circuit for selecting second test pattern data for each device under test from the plurality of memories;
It is provided with.

  As is apparent from the above description, according to the present invention, in a semiconductor test apparatus that performs a parallel test by applying test pattern waveforms to a plurality of devices under measurement, the first test pattern common to each device under measurement A pattern generator for generating data, a storage unit for generating individual second test pattern data for each device under measurement, and selecting either the first test pattern data or the second test pattern data, By providing a first selection circuit that outputs test pattern data for generating a test pattern waveform, “applying a common test pattern waveform” and “applying an individual test pattern waveform” to each DUT In this case, it is possible to provide a semiconductor test apparatus in which the application timing “deviation” is corrected and the redundancy of the circuit configuration is eliminated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a test waveform application circuit for applying a test pattern to a DUT as an example of a semiconductor test apparatus according to an embodiment of the present invention. The same parts as those in FIG. 3 are given the same symbols.

In FIG. 1, a test waveform applying circuit is configured by the pattern generator 101 and the integrated circuits IC101 and IC102 for each system pin of each DUT 12.

The pattern generator 1 generates first test pattern data common to each DUT and outputs the first test pattern data to the integrated circuits IC101 and IC102.

  In the integrated circuit IC101, the distributor 102 distributes the test pattern data input from the pattern generator 1 to a plurality of circuits A101, A102,.

The circuits A101, A102,... Are composed of the same circuit, and select and shape a test pattern waveform for each DUT 12 respectively.

  The memory 103 (PSR memory) constitutes a storage unit, in which individual second test pattern data corresponding to each DUT is recorded.

The XOR 104 forms a logic circuit, performs exclusive OR with the first test pattern data output from the distributor 102 and the second test pattern data generated in the memory 103 as two inputs, and outputs the result as new test pattern data. To do.

The selection circuit 105 selects one of the first test pattern data input from the distributor 102, the second test pattern data input from the memory 103, and the test pattern data input from the XOR 104, and outputs one of them.

The timing signal generator 106 generates a timing signal.

The timing correction circuit 107 corrects the timing signal input from the timing signal generator 106 with a timing value corresponding to the line length from the drive circuit 11 to the DUT 12.

The waveform shaper 108 is configured by, for example, a flip-flop, and performs waveform shaping on the test pattern data input from the selection circuit 105 using the timing signal subjected to timing correction by the timing correction circuit 107, and outputs a waveform.

The drive circuit 11 applies the test pattern waveform shaped by the waveform shaper 108 to the DUT 12 as a drive signal.

In the above description, the pattern generator 1 constitutes a pattern generator that generates first test pattern data common to each device under measurement, and the memory 103 stores individual second test pattern data for each device under measurement. The memory | storage part which generate | occur | produces is comprised.

The operation of the apparatus of FIG. 1 will now be described.

The first test pattern data common to each DUT output from the pattern generator 1 is output to the integrated circuits IC101 and IC102. The test pattern data input to the integrated circuit IC101 is distributed by the distributor 102 to the circuits A101, A102,.

  In the circuit A101, the individual second test pattern data output to the DUT 12 output from the memory 103 (PSR memory) is exclusively ORed with the first test pattern data output from the distributor 102 in the XOR 104. And output as new test pattern data.

The selection circuit 105 selects and outputs one of the first test pattern data input from the distributor 102, the second test pattern data input from the memory 103, and the test pattern data input from the XOR 104.

The timing signal output from the timing signal generator 106 is corrected by the timing correction circuit 107 with a timing value corresponding to the line length from the drive circuit 11 to the DUT 12.

The test pattern data output from the selection circuit 105 is waveform-shaped in the waveform shaper 108 according to the timing signal output from the timing correction circuit 107.

The test pattern waveform shaped by the waveform shaper 108 becomes a drive signal in the drive circuit 11 and is applied to the DUT 12.

That is, when the selection circuit 105 selects the first test pattern data input from the distributor 102, a test pattern waveform is commonly applied to each DUT 12, and is input from the memory 103 in the selection circuit 105. When the second test pattern data or the test pattern data input from the XOR 104 is selected, the test pattern waveform is individually applied to the DUT 12.

Although the operation of the circuit A101 of the integrated circuit IC101 has been described above, the circuit A102 and the subsequent circuits are the same as the A101, and the integrated circuit IC102 is the same as the integrated circuit IC101.

According to the arbitrary waveform generator having the above-described configuration, the test pattern waveform is generated based on the test pattern data output from the same selection circuit. Therefore, “a common test pattern waveform is applied to each DUT. "And" applying individual test pattern waveforms ", there is no" shift "in the application timing.

In addition, since the number of waveform shapers per DUT is one per system pin and redundant circuits of the waveform shapers are reduced, the circuit scale can be reduced. For this reason, the number of conventional integrated circuits consisting of four can be reduced to two, and the integration of the test waveform applying circuit can be promoted. Therefore, it is possible to reduce the size of the device and reduce the wiring cost.

In the above-described embodiment, the case where there are two integrated circuits, IC101 and IC102, can be any number according to the number of DUTs to be tested in parallel.

In the above embodiment, since the pattern generator 1 having a large fan-out is used, a distributor such as 2 in FIG. 3 is not used, but the output of the pattern generator 1 as shown in FIG. You may distribute with a distributor.

FIG. 2 shows a second example of the semiconductor test apparatus according to the embodiment of the present invention, and does not output test pattern data from a fixed memory for each DUT as in FIG. It is a block diagram showing a configuration in which a built-in memory output can be output to various DUTs. The same parts as those in FIG.

In FIG. 2, a test waveform applying circuit is configured by the pattern generator 201, the distributor 202, the integrated circuits IC 201, and IC 202 for each system pin of each DUT 12.

The pattern generator 201 generates first test pattern data common to each DUT 12.

The distributor 202 distributes the test pattern data input from the pattern generator 201 to the integrated circuits IC201 and IC202.

  In the integrated circuit IC201, the test pattern data input from the distributor 202 is input to a plurality of circuits A201, A202,.

The circuits A201, A202,... Are composed of the same circuit, and select and shape the test pattern waveform for each DUT 12 respectively.

  In the storage unit 203, individual test pattern data corresponding to each DUT is selected and output. A plurality of memories 2031a, 2031b,... 2031n constitute a PSR memory, and test pattern data for applying a test pattern waveform to each DUT individually is stored.

  The selection circuit 2032 selects from different test pattern data input from the plurality of memories 2031a, 2031b,... 2031n, and associates them with the plurality of circuits A201, A202,. Here, the selection circuit 2032 constitutes a second selection circuit that selects from the plurality of memories 2031a, 2031b,... 2031n and outputs the second test pattern data for each device under measurement 12.

The logic circuit 204 includes various logic circuits such as AND, OR, and XOR, for example, and has two inputs, the first test pattern data output from the distributor 202 and the second test pattern data selected by the storage unit 203. The exclusive OR is calculated and output as individual new test pattern data corresponding to each DUT 12.

The selection circuit 105 selects one from the first test pattern data input from the distributor 202, the second test pattern data input from the storage unit 203, and the test pattern data input from the logic circuit 204, and outputs one of them. .

Other configurations are the same as those of the apparatus shown in FIG.

The operation of the apparatus of FIG.

The first test pattern data common to each DUT output from the pattern generator 201 is distributed by the distributor 202 to the integrated circuits IC201 and IC202. The first test pattern data input from the distributor 202 to the integrated circuit IC 201 is input to a plurality of circuits A201, A202,.

  In the storage unit 203 of the IC 201, different test pattern data output from the plurality of memories 2031a, 2031b,... 2031n are selected by the selection circuit 2032 and the second test pattern data is transmitted to the plurality of circuits A201, A202,. Is output as

In the circuit A 201, the logic operation is performed on the test pattern data output from the distributor 202 and the test pattern data selected by the storage unit 203 by the logic circuit 204.

One of the first test pattern data output from the distributor 202, the second test pattern data output from the storage unit 203, and the test pattern data output from the logic circuit 204 is selected by the selection circuit 105.

That is, when the selection circuit 105 selects the first test pattern data input from the distributor 202, a test pattern waveform is applied to each DUT 12 in common, and is output from the storage unit 203 in the selection circuit 205. When the second test pattern data or the test pattern data output from the logic circuit 204 is selected, the test pattern waveform is individually applied to the DUT 12.

Although the operation of the circuit A201 of the integrated circuit IC201 has been described above, the same applies to the circuit A202 and the subsequent circuits, and the integrated circuit IC202 is similar to the integrated circuit IC201.

According to the semiconductor test apparatus configured as described above, in addition to the features of the semiconductor test apparatus shown in FIG. 1, the second test pattern data is selected by the selection circuit using the outputs of the plurality of memories as an input. Since the built-in memory output can be used in various DUTs, the memory can be used efficiently.

  Further, by using the logic circuit (204), the output of the logic circuit having the test pattern data output from the pattern generator 1 and the test pattern data output from the plurality of memories 2031a, 2031b,. Various test pattern data can be obtained from

In the above-described embodiment, the number of integrated circuits is two, that is, IC 201 and IC 202. However, any number may be used according to the number of DUTs to be tested in parallel.

1 is a configuration block diagram showing an example of a semiconductor test apparatus according to an embodiment of the present invention. It is a block diagram which shows the 2nd Example of the semiconductor test apparatus which concerns on embodiment of this invention. It is a block diagram showing a conventional example of a semiconductor test apparatus.

Explanation of symbols

12 device under test 101, 201 pattern generator 103, 203 storage unit 104, 204 logic circuit 105 first selection circuit 106 timing signal generator 108 waveform shapers 2031a, 2031b,... 2031n multiple memories 2032 second Selection circuit

Claims (4)

In a semiconductor test apparatus that performs a parallel test by applying a test pattern waveform to multiple devices under test,
A pattern generator for generating first test pattern data common to each device under measurement;
A storage unit for generating individual second test pattern data for each device under measurement;
A logic circuit that performs a logical operation on the first pattern data generated by the pattern generator and the second pattern data generated by the storage unit;
A first selection circuit for selecting output data of the logic circuit, the first test pattern data, and the second test pattern data, and outputting test pattern data for generating the test pattern waveform;
A waveform shaper for shaping the test pattern data selected by the first selection circuit and outputting the test pattern waveform;
A semiconductor test apparatus comprising: a timing signal generator for supplying a timing signal to the waveform shaper . The storage unit, the first selection circuit, the logic circuit and the waveform shaper mounted to each DUT pin, the semiconductor test apparatus according to claim 1, wherein the integrated. 3. The semiconductor test apparatus according to claim 1, wherein the storage unit is a memory, and the logic circuit is an exclusive OR circuit. The storage unit
A plurality of memories for storing different test pattern data;
The semiconductor test apparatus according to claim 1 or 2, characterized in that a second selection circuit for selecting a second test pattern data for each device under test from the plurality of memory.

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