JPH0514002A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0514002A
JPH0514002A JP3192619A JP19261991A JPH0514002A JP H0514002 A JPH0514002 A JP H0514002A JP 3192619 A JP3192619 A JP 3192619A JP 19261991 A JP19261991 A JP 19261991A JP H0514002 A JPH0514002 A JP H0514002A
Authority
JP
Japan
Prior art keywords
voltage
package
resistance pattern
semiconductor device
mmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3192619A
Other languages
Japanese (ja)
Inventor
Yoshinobu Kadowaki
好伸 門脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3192619A priority Critical patent/JPH0514002A/en
Publication of JPH0514002A publication Critical patent/JPH0514002A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Details Of Resistors (AREA)
  • Waveguide Connection Structure (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To realize the semiconductor device not requiring the adjustment of a voltage externally and for ease of use. CONSTITUTION:A resistance pattern 6 is provided in a package 7. A DC bias voltage of each FET of an MMIC chip 5 is adjusted to a required value by the resistance pattern 6. An external voltage applied to a common gate bias terminal 30 of the package 7 is a prescribed voltage and the voltage divided by the resistance pattern 6 is distributed to each FET.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体装置に関し、特
にマイクロ波帯半導体装置のパッケージ構造の改良に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of a microwave band semiconductor device package structure.

【0002】[0002]

【従来の技術】マイクロ波半導体装置として、モノリシ
ックマイクロ波集積回路増幅器(以下、MMICアンプ
と称す)があるが、図2は例えば従来のMMICアンプ
のパッケージの蓋を取り去った状態を示す内部目視図で
あり、電界効果トランジスタ(以下、FETと称す)3
個を有している。図において、5はMMICアンプのチ
ップ、7は半導体素子であるMMICチップ5を収納す
るパッケージ、1は該パッケージ7に設けられた入力信
号端子、2は上記パッケージ7に設けられた出力信号端
子である。31,32,33はMMICに含まれるFE
Tのゲートバイアス端子で、上記パッケージ7に設けら
れている。41,42,43は同様にFETのドレイン
バイアス端子で、上記パッケージ7に設けられている。
8はMMICチップ5とパッケージ7の上記各端子とを
接続するボンディングワイヤである。
2. Description of the Related Art As a microwave semiconductor device, there is a monolithic microwave integrated circuit amplifier (hereinafter referred to as MMIC amplifier). FIG. 2 is an internal visual view showing a state in which a conventional MMIC amplifier package has a lid removed. And a field effect transistor (hereinafter referred to as FET) 3
Have pieces. In the figure, 5 is an MMIC amplifier chip, 7 is a package for housing the MMIC chip 5 which is a semiconductor element, 1 is an input signal terminal provided on the package 7, and 2 is an output signal terminal provided on the package 7. is there. 31, 32, and 33 are FEs included in MMIC
It is a gate bias terminal of T and is provided in the package 7. Similarly, reference numerals 41, 42 and 43 denote FET drain bias terminals, which are provided in the package 7.
Reference numeral 8 is a bonding wire that connects the MMIC chip 5 and each terminal of the package 7.

【0003】次に動作について説明する。MMICアン
プはFETの直流バイアス条件を所定値に設定するた
め、ゲート電圧を外部調整している。例えば図2に示す
FETを3個含むMMICアンプにおいて、各々のFE
Tについてゲートバイアス端子31,32,33を設
け、各々外部から入力するゲート電圧を調整する。
Next, the operation will be described. In the MMIC amplifier, the gate voltage is externally adjusted in order to set the DC bias condition of the FET to a predetermined value. For example, in the MMIC amplifier including three FETs shown in FIG.
Gate bias terminals 31, 32, and 33 are provided for T, and the gate voltage input from the outside is adjusted.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、実使用時に複数のゲー
ト電圧を調整する必要があり、煩雑でかつ調整に時間を
費やすなどの問題点があった。
Since the conventional semiconductor device is configured as described above, it is necessary to adjust a plurality of gate voltages during actual use, which is troublesome and time consuming for adjustment. was there.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、ゲート電圧の外部調整を不要と
した半導体装置を得ることを目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device which does not require external adjustment of the gate voltage.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体装
置は、半導体素子を収納するパッケージに、上記半導体
素子への印加電圧調整のための抵抗パターンを形成した
ものである。
A semiconductor device according to the present invention is a package in which a semiconductor element is housed and a resistance pattern for adjusting a voltage applied to the semiconductor element is formed.

【0007】[0007]

【作用】この発明においては、半導体素子を収納するパ
ッケージに、上記半導体素子への印加電圧調整のための
抵抗パターンを設けたので、該抵抗パターンにより電圧
が調整され、電圧の外部調整を行わないで、所要の電圧
を上記半導体素子に印加することができる。
According to the present invention, the package for accommodating the semiconductor element is provided with the resistance pattern for adjusting the voltage applied to the semiconductor element. Therefore, the voltage is adjusted by the resistance pattern and the voltage is not externally adjusted. Then, a required voltage can be applied to the semiconductor element.

【0008】[0008]

【実施例】図1はこの発明の一実施例による半導体装置
であるMMICアンプのパッケージの蓋を取り去った状
態を示す内部目視図であり、FET3個を有している。
図において、図2と同一符号は同一又は相当部分を示
し、6は半導体素子(MMICチップ)の直流電圧印加
用の抵抗パターンで、パッケージ7に設けられている。
30はMMICに含まれるFETの共通ゲートバイアス
端子で、パッケージ7に設けられている。40はMMI
Cに含まれるFETの共通ドレインバイアス端子で、パ
ッケージ7に設けられている。尚、従来においてもドレ
インバイアス端子は電圧を共通とできるので、共通ドレ
インバイアス端子40を用いることができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an internal visual view showing a state in which a package lid of an MMIC amplifier, which is a semiconductor device according to an embodiment of the present invention, is removed, and has three FETs.
In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions, and 6 is a resistance pattern for applying a DC voltage to a semiconductor element (MMIC chip), which is provided in the package 7.
Reference numeral 30 denotes a common gate bias terminal of the FET included in the MMIC, which is provided in the package 7. 40 is MMI
The common drain bias terminal of the FET included in C is provided in the package 7. In addition, since the drain bias terminal can share the same voltage in the related art, the common drain bias terminal 40 can be used.

【0009】次に作用について説明する。抵抗パターン
6は、ゲートバイアス端子30に印加された電圧をMM
ICチップ5の各々のFETに必要なゲート電圧を与え
るために、ゲートバイアス端子30に印加された電圧を
抵抗分圧して変換する。つまり、外部のゲート端子は所
定の電圧であるが、内部のMMICチップ5の各FET
のゲート電圧は抵抗パターン6により異なったものとな
っている。
Next, the operation will be described. The resistance pattern 6 sets the voltage applied to the gate bias terminal 30 to MM.
In order to apply a required gate voltage to each FET of the IC chip 5, the voltage applied to the gate bias terminal 30 is resistance-divided and converted. That is, although the external gate terminal has a predetermined voltage, each FET of the internal MMIC chip 5 is
The gate voltage varies depending on the resistance pattern 6.

【0010】このように本実施例では、パッケージ7の
MMICチップ5を収納する部分にゲート電圧調整用の
抵抗パターン6を設けたので、ゲートバイアス端子30
を共通のものとし、MMICチップ5の各々のFETの
直流バイアス電圧を所要の値に調整することができ、従
ってゲート電圧の外部調整を不要とした使用が容易なM
MICアンプを得ることができる。
As described above, in this embodiment, since the resistance pattern 6 for adjusting the gate voltage is provided in the portion of the package 7 in which the MMIC chip 5 is housed, the gate bias terminal 30 is provided.
Is common to each of the MMIC chips 5, and the DC bias voltage of each FET of the MMIC chip 5 can be adjusted to a required value.
A MIC amplifier can be obtained.

【0011】[0011]

【発明の効果】以上のようにこの発明に係る半導体装置
によれば、半導体素子を収納するパッケージに上記半導
体素子への印加電圧調整のための抵抗パターンを形成し
たので、該抵抗パターンにより電圧調整され、外部電圧
の調整を不要とした使用が容易な半導体装置を得ること
ができる効果がある。
As described above, according to the semiconductor device of the present invention, since the resistance pattern for adjusting the applied voltage to the semiconductor element is formed in the package that accommodates the semiconductor element, the voltage adjustment is performed by the resistance pattern. Therefore, it is possible to obtain a semiconductor device which does not require adjustment of the external voltage and is easy to use.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例によるMMICアンプを示
す内部目視図。
FIG. 1 is an internal visual view showing an MMIC amplifier according to an embodiment of the present invention.

【図2】従来のMMICアンプを示す内部目視図。FIG. 2 is an internal visual view showing a conventional MMIC amplifier.

【符号の説明】[Explanation of symbols]

1 入力信号端子 2 出力信号端子 5 MMICチップ 6 抵抗パターン 7 パッケージ 8 ボンディングワイヤ 30 共通ゲートバイアス端子 40 共通ドレインバイアス端子 1 Input signal terminal 2 Output signal terminal 5 MMIC chip 6 Resistance pattern 7 Package 8 Bonding wire 30 Common gate bias terminal 40 Common drain bias terminal

Claims (1)

【特許請求の範囲】 【請求項1】 半導体素子をパッケージに収納してなる
半導体装置において、 上記パッケージには、上記半導体素子への印加電圧調整
のための抵抗パターンが形成されていることを特徴とす
る半導体装置。
Claim: What is claimed is: 1. A semiconductor device comprising a semiconductor element housed in a package, wherein the package is formed with a resistance pattern for adjusting a voltage applied to the semiconductor element. Semiconductor device.
JP3192619A 1991-07-05 1991-07-05 Semiconductor device Pending JPH0514002A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3192619A JPH0514002A (en) 1991-07-05 1991-07-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3192619A JPH0514002A (en) 1991-07-05 1991-07-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0514002A true JPH0514002A (en) 1993-01-22

Family

ID=16294275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3192619A Pending JPH0514002A (en) 1991-07-05 1991-07-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0514002A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005227031A (en) * 2004-02-10 2005-08-25 Mitsubishi Electric Corp Millimeter wave transmission/reception module and bias adjustment method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5626910B2 (en) * 1975-06-24 1981-06-22
JPS6482551A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5626910B2 (en) * 1975-06-24 1981-06-22
JPS6482551A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005227031A (en) * 2004-02-10 2005-08-25 Mitsubishi Electric Corp Millimeter wave transmission/reception module and bias adjustment method

Similar Documents

Publication Publication Date Title
JPH045289B2 (en)
JPH0514002A (en) Semiconductor device
JPH02110943A (en) Field-effect transistor
JP3371151B2 (en) Monolithic microwave semiconductor integrated circuit
JPH06120424A (en) Semiconductor integrated circuit device
JPH0212972A (en) Dual-gate gallium-arsenite metal-semiconductor power field effect transistor
JP3792012B2 (en) Positive voltage operation type high frequency power amplifier
JPH021177A (en) Semiconductor device
US6452370B1 (en) Low noise biasing technique
JPH09283710A (en) Gate bias circuit for fet
JPH11154835A (en) Differential amplifier
JPH01216608A (en) Package for semiconductor device
JPH04914A (en) Semiconductor integrated circuit device
JPS61172376A (en) Semiconductor device
JPS63133701A (en) Microwave semiconductor device
JPS6251231A (en) Semiconductor integrated circuit device
JP2982256B2 (en) Waveform correction circuit
JPH01189210A (en) Negative-feedback type wide band amplifier circuit
JPS63303410A (en) Semiconductor ic device
JP3153970B2 (en) Single balance mixer circuit
JPH01272202A (en) Package for semiconductor device
JPH11136047A (en) High frequency power amplifier
JPH0794649A (en) Gaasfet package
JPS63111659A (en) Semiconductor device
JP2004303949A (en) Mos transistor device