JP2982256B2 - Waveform correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier using an IC such as a radar device and a navigation device using a high-frequency pulse signal, and in particular,
The present invention relates to a waveform correction circuit for flattening the top of a high-frequency pulse output signal.

2. Description of the Related Art Conventionally, this type of high-frequency pulse amplifier employs a method in which a field effect transistor is operated in class A, a predetermined DC voltage is applied to a gate bias and a drain bias, and a method in which a gate bias or a drain bias is switched. .

Problems to be Solved by the Invention In the high-frequency amplifier using the conventional field-effect transistor described above, when a DC voltage is applied to a gate bias and a drain bias, a drain current flows even during a time when there is no high-frequency pulse input signal. There is a disadvantage that power consumption is large.

In the method of switching the gate bias or the drain bias, generally, when the drain current is constant, the gain of the field effect transistor decreases as the internal temperature of the field effect transistor increases as shown in FIG. A bias is applied before the signal is input to the effect transistor, and the internal temperature is increased in advance before the high-frequency pulse input signal is applied. However, since the drain current is small at the bias voltage that is optimal for amplifying the high-frequency pulse signal, the temperature rise is gradual, and the fluctuation of the gain is inevitable.

The present invention has been made in view of the above-described conventional circumstances, and accordingly, it is an object of the present invention to provide a novel waveform correction circuit capable of solving the above-described problems inherent in the conventional technology. is there.

Means for Solving the Problems In order to achieve the above object, a waveform correction circuit according to the present invention comprises at least one first field effect transistor and a bias having one end connected to the gate of the first field effect transistor. Waveform correction for correcting an output waveform of a power amplifier for power-amplifying a high-frequency input signal, comprising a supply resistor, an input terminal for inputting a high-frequency pulse signal, and an output terminal for outputting a signal obtained by power-amplifying the high-frequency pulse signal. A bias circuit, comprising: a second field-effect transistor; a load resistor connected between a drain of the second field-effect transistor and a power supply; a drain voltage of the second field-effect transistor; And a pulse signal voltage generated in response to the signal change timing of the high-frequency pulse signal at an optimum level. To the other end of the bias supply resistor connected to the gate of the first field effect transistor.

Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

 FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Referring to FIG. 1, resistors R ₁ of the power amplifier 1 is a high resistance value to the gate of the field effect transistor Q ₁ to Q thereof has a three-stage structure of ₃ field-effect transistor Q ₁ to Q ₃ ~ R ₃
Are connected to each other.

The bias circuit 2 is composed of a field effect transistor Q ₁ to Q ₃ and the load resistor R ₄ which connected between the drain and source terminals of the field formed by the same conditions effect transistor Q ₄ and the field effect transistor Q ₄ I have.

The adder 3, the field effect of the drain terminal of the transistor Q ₄ signal and pulse input terminal 4 signal and the sum is set to the optimum level, the output terminal to the gate of the field effect transistor Q ₁ to Q ₃ It is connected to the other end of the connected resistors R _{1 to} R ₃ .

Now, when the pulse signal to the pulse input terminal 4 is input, the drain current of the field effect transistor Q ₄ are, the internal temperature is at a low state the current rapidly flows, the drain current is reduced to a temperature rise with time I do. The drain voltage of the field effect transistor Q ₄ and the input pulse signal is added by the adder 3, the field effect transistor of this voltage
With the gate voltage of Q ₁ to Q _3, the drain current is small immediately after the pulse signal input of the field effect transistor Q ₁ to Q _3, increases with time, in a steady state.

Generally field effect transistor as gain less small drain current, in order to increase the gain as much as the drain current is large, the field effect transistor Q ₁ to Q ₃ immediately after the pulse input is reduced gain, the gain with time is steady state Approach. Therefore, the gain decrease due to the temperature rise and the gain increase due to the increase in the drain current are offset, and the gain becomes constant.

FIG. 2 shows the pulse input terminal 4 and the field effect transistor Q ₄
And the operating state of the adder 3 are shown.

Effect of the Invention As described above, according to the present invention, the decrease in gain due to a temperature rise of a field effect transistor and the increase in gain due to an increase in drain current are made the same ratio.
The effect of flattening the top of the high-frequency pulse signal is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a pulse waveform diagram of each part in the embodiment, and FIG. 3 is an internal temperature rise characteristic and gain with respect to time of the field effect transistor in the embodiment. It is a fluctuation characteristic figure. 1 ... power amplifying unit, 2 ... bias circuit, 3 ... adder, 4 ... pulse input terminal

Claims (2)

(57) [Claims] An at least one first field effect transistor; a bias supply resistor having one end connected to the gate of the first field effect transistor; and a gate of the first stage first field effect transistor. An input terminal for inputting a high-frequency pulse signal, which is an input signal, and an output terminal for outputting a signal obtained by power-amplifying the high-frequency pulse signal. A bias circuit composed of a second field-effect transistor whose source is grounded, a load resistor connected between the drain of the second field-effect transistor and a power supply, A drain voltage of the second field-effect transistor, and a pulse signal voltage generated in response to a signal change timing of the high-frequency pulse signal. An adder for adding each of the signals at an optimum level and adding the added output to the other end of the bias supply resistor connected to the gate of the first field-effect transistor. A waveform correction circuit for canceling a decrease in gain due to an increase by changing a gate bias value determined by an output of the adder. 2. The power amplifier, the bias circuit,
2. The waveform correction circuit according to claim 1, wherein said adder and said adder are provided in the same semiconductor chip.