JPH0794961A - High frequency amplification module - Google Patents

Abstract

PURPOSE:To provide a high frequency amplification module capable of optimizing an idle current in each stage and improving efficiency and yield by independently setting up gate bias voltage for an FET in each stage. CONSTITUTION:Plural gate bias circuits for supplying gate bias voltages set up by the divided voltages of bias resistors b1 to bn, c1 to cn serially connected to a bias power supply from respective serial nodes of the bias resistors b1 to bn, c1 to cn to the gate terminals of FETs Tr1 to Trn in amplifier circuits through respective extracting resistors a1 to an are independently prepared while sharing the bias power supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifying module using an FET as an active element, and more particularly to a high frequency amplifying module used in a wireless communication device such as a car phone or a mobile phone.

[0002]

2. Description of the Related Art As a conventional high frequency amplification module using an FET (field effect transistor) as an active element, there is, for example, a structure shown in FIG.

The module shown in FIG. 5 is composed of a plurality of stages of circuits. The high frequency matching circuit of the input circuit 101, the interstage circuit 102, and the output circuit 103, and the F of the interstage circuit 102.
ETTr. 1 and the FET Tr. Of the output circuit 103. It has a gate bias circuit for supplying a gate bias voltage to the second gate terminal. The gate bias circuit extracts a gate bias voltage obtained by dividing the resistance of the resistors 106 and 107 connected in series between the gate bias power supply terminal V _APC and the ground potential to a take-out resistor connected to the series connection point of the resistors 106 and 107. Corresponding FE via 108 or 109
TTr. 1, Tr. 2 is supplied with the gate bias voltage.

Further, in such a module,
From the viewpoint of miniaturization and integration, it is desirable to have a simple configuration. Therefore, for the gate bias circuit, the gate bias power supply terminal V _APC , the interstage circuit 102, and the output circuit 10 are provided.
The drain power supply terminals V _DD for 3 are made common terminals.

In such a high frequency amplifier module, as shown in FIG. 5, the FET Tr. 1, Tr.
A current hardly flows through the takeout resistors 108 and 109 connected to the No. 2 and the resistors 106 and 10 connected in series are connected.
Each of the FET Tr. 1, Tr. 2 is applied to the gate terminal of each FET Tr.
1, Tr. The same gate bias voltage was applied to 2.

On the other hand, in the FETs forming the module, it is necessary to increase the transistor size according to the output to be obtained, that is, the gate width. For this reason, the gate width of the FET generally becomes larger toward the output side.

However, in the module shown in FIG. 5, since the same gate bias voltage is supplied to the FETs in each stage, the idle current (drain current) flowing in the FETs in each stage is The FETs flow according to the gate width of each FET, and a larger amount of idle current flows in the FET on the output side. The fact that the idle current is large causes a decrease in efficiency, as is clear from FIG. 3 showing the relationship between the idle current of the FET and the output and efficiency.

Further, variations in idle current lead to variations in element impedance, causing deterioration of characteristics such as circuit mismatching and output reduction, leading to a reduction in yield.

[0009]

As described above,
In the conventional high frequency amplification module having a common gate bias voltage as shown in FIG.
Since the gate bias voltage is not set according to the size of the FET, the idle current in each FET was not optimized. As a result, the efficiency is deteriorated and the yield is decreased.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide each F
It is an object of the present invention to provide a high-frequency amplifier module that can optimize the idle current by independently setting the gate bias voltage for each ET, and can improve the efficiency and the yield.

[0011]

In order to achieve the above object, the invention according to claim 1 has a plurality of stages of circuits having a plurality of FETs (field effect transistors) for taking out a drain terminal as a common terminal, and a bias power supply. A gate bias circuit that supplies a gate bias voltage set by the voltage division of the bias resistor to the gate terminal of the FET of the circuit via one extraction resistor from the series connection point of the bias resistors connected in series between A plurality of gate bias circuits are independently provided with a common bias power supply.

According to a second aspect of the present invention, each of the gate bias circuits adjusts one resistance value of the bias resistor with a voltage equal to or lower than a threshold voltage of the FET as an initial value of the gate bias voltage. It is configured to set the gate bias voltage.

[0013]

According to the present invention, the gate bias voltages are independently supplied to the gate terminals of the corresponding FETs by the independent gate bias circuits directly connected to the common bias power source.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a gate bias circuit in a high frequency amplification module according to an embodiment of the present invention.

In FIG. 1, the gate bias circuit is n
Each FET Tr. Of the stage amplification module. 1-T
r. This is a circuit for supplying a gate bias voltage to n, and n sets are provided in parallel with the gate bias power supply terminal V _APC . Each of the gate bias circuits divides the gate bias power supply voltage by resistors b _{1 to} b _n and resistors C _{1 to} C _n connected in series between the gate bias power supply terminal V _APC and the ground potential to divide the gate bias power supply voltage. The voltage is set, and the set gate bias voltage is taken out from the series connection point via the resistors a _{1 to} a _n , and the corresponding FET T
r. 1-Tr. n gate terminal.

Next, such a gate bias circuit is
An embodiment applied to a high-frequency amplification module for stage amplification will be described with reference to FIG.

In FIG. 2, the high frequency amplification module is
Input circuit 1, interstage circuit 2, output circuit 3, and FETT
r. 1 and FET Tr. 2 has a gate bias circuit composed of resistors a ₁ , a ₂ , b ₁ , b ₂ , c ₁ , c ₂ for supplying a bias voltage to the gate terminal, and has an input terminal IN, an output terminal OUT, and a drain common to each stage. It is a module with the simplest structure of four terminals including a power supply terminal V _DD and a gate bias power supply terminal V _APC .

In such a high frequency amplifier module, the resistors a ₁ , a ₂ ,
b ₁ , b ₂ , c ₁ and c ₂ are composed of thick film (printing) resistors, and resistors b ₁ and b ₂ and a resistor c connected in series between the gate bias power supply terminal V _APC and the ground potential. Of the ₁ and c ₂ , the resistors c ₁ and c ₂ are set to fixed values, for example, 5 and 6 KΩ, and the resistance values of the resistors b ₁ and b ₂ are adjusted so that the F
ETTr. 1, Tr. The gate bias voltage of 2 is set, the set gate bias voltage is taken out, and the resistance a ₁ ,
a ₂ through the corresponding FET Tr. 1, T
r. It is supplied to the gate terminal of 2.

The FET Tr. 1, Tr. Since a direct current hardly flows to the gate terminal of _{No. 2,} there is no voltage drop at the take-out resistors a ₁ and a ₂ , and the gates set by the resistors b ₁ , b ₂ , c ₁ and c ₂ connected in series. The FET Tr. 1, Tr. Two
Will be supplied to the gate terminal of. Further, when the high-frequency circuit on the input side is DC and the potential is not fixed, the take-out resistors a ₁ and a ₂ may be set to a value (about 100Ω) which is about 50 to 100 times the input impedance of the element. desirable.

Next, a method of adjusting the gate bias voltage in such a gate bias circuit will be described.

First, each FET Tr. 1-Tr.
The initial value of the gate bias voltage applied to the gate terminal of 2 is set below the threshold voltage of the FET,
ETTr. 1, Tr. Make sure that almost no drain current flows through 2. In the configuration shown in FIG. 2, each FET Tr. 1-Tr. The threshold voltage of 2 was 1.5V, the power supply voltage applied to the gate bias power supply terminal V _APC was 3.0V, and the gate bias voltage was 1.5V. That is, since the resistance values of the resistors c ₁ and c ₂ are set to 5.6 KΩ, the resistance values of the resistors b ₁ and b ₂ are set to 5, 6
Set to KΩ.

Next, while detecting the overall circuit drain current (total drain current), and the resistance value of the resistor b ₁ is increased by a laser trimming method, the potential of the series connection point of the resistors b ₁ and the resistor c _1, That is, the gate bias voltage is increased. As the gate bias voltage increases, the total drain current, that is, the FET Tr. 1 drain current (idle current) increases, and the resistance value of the resistor b ₁ is adjusted so that the idle current has a desired value. Set the gate bias voltage of 1.

Next, in the same manner as described above, the resistance value of the resistor b ₂ is increased by the laser trimming method, and the FET Tr.
2. Increase the gate bias voltage of 2. At this time, since the gate bias circuits in each stage are independent, they do not interfere with each other. FET Tr. 2 as the gate bias voltage of the FET Tr. The drain current of 2 increases and the total drain current also increases.

Here, the total drain current is FETT
r. Although the idle current of No. 1 is included, the value of the idle current has already been set at the stage of the above-mentioned setting. By subtracting the idle current of FETTr. The drain current of 2 (idle current) is easily obtained. In this way, the total drain current, that is, the FET Tr. The resistance value of the resistor b ₁ is adjusted so that the idle current of _{No. 2} becomes a desired value, and the FET Tr. Set the gate bias voltage of 2.

In this way, the idle current is set by setting the gate bias voltage of each stage. However, since the idle current of the FET has the characteristics shown in FIG. 3, the output is relatively high. It is desirable to set a relatively large idle current in order to obtain a gain in the FET of a very small front stage, and to set a relatively small idle current in order to obtain an efficiency in the FET of a subsequent stage.

Therefore, in this embodiment, for example, the idle current in the front stage is set to about 150 mA, and the idle current in the rear stage is set to about 150 mA, and the front and rear stages have the same value. This is the FET Tr. 1 is the FETT in the latter stage
r. Since the gate width, that is, the transistor size is smaller than that of 2, even if the idle current of the preceding stage is made equal to the idle current of the following stage, the idle current per unit gate becomes larger in the preceding stage than in the latter stage.

Further, the gate width of the FET in the subsequent stage is F
Since the gain is large compared to the gate width of ET, if the idle current is increased, self-excited oscillation due to the DC bias is likely to occur, and it is effective to reduce the idle current to prevent this. Further, when the high frequency gain has a margin, it is desirable that the idle current of the FET that obtains a large output be 50 mA or less.

The present invention is not limited to the above embodiment, and a capacitor 4 for cutting off a high frequency signal may be provided as shown in FIG. 4, for example.

As described above, in the above embodiment, since the gate bias voltage of the FET of each stage can be set independently, the idle current of the FET of each stage is set to the optimum value according to the transistor size of each FET. It becomes possible to set. This improves the overall efficiency of the entire circuit, stabilizes the element impedance, improves circuit matching, and improves output. As a result, the yield is also improved.

Further, since each gate bias circuit for supplying the gate bias voltage to the FET of each stage is directly connected to the gate bias power supply terminal V _APC , the gate bias voltage is FE through the minimum resistance and capacitor.
It is supplied to the gate terminal of T to improve the transient characteristic. Further, by reducing the capacitor for blocking high frequency signals, the switching speed is improved and it becomes possible to realize a digital module.

Further, in FIG. 4, the resistances of the takeout resistors a ₁ and a ₂ connected to the gate terminals of the FETs of the respective stages are grounded at a high frequency by a high frequency cutoff capacitor, so that the resistance values thereof are high. By setting it to 50 to 100Ω, the stability factor K of the element can be set to 1 or more.

[0033]

As described above, according to the present invention, in each gate bias circuit which is directly connected to a common bias power source and is independent of each other, each gate bias voltage obtained by resistance division of the gate bias power source voltage is Since the gate terminals of the corresponding FETs are independently supplied, the optimum idle current can be set for each amplification stage with a simple configuration. As a result, the efficiency of the module is improved, the circuit matching is improved, and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a gate bias circuit of a high frequency amplification module according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a high frequency amplification module according to an embodiment of the present invention using the gate bias circuit shown in FIG.

FIG. 3 is a diagram showing the relationship between idle current, efficiency, and output in a FET.

FIG. 4 is a diagram showing a configuration of a high frequency amplification module according to another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a high-frequency amplifier module using a conventional gate bias circuit.

[Explanation of symbols]

1,101 input circuit 2,102 interstage circuit 3,103 output circuit 4 capacitors _{a 1, a n, b 1} , b n, c 1, c n, 106~109
Resistor Tr1, Tr2 FET

Claims (2)

[Claims] 1. A high-frequency circuit of a plurality of stages having a plurality of FETs (field-effect transistors) that take a drain terminal as a common terminal, and a series connection point of bias resistors connected in series between bias power sources through a single take-out resistor. FE of high frequency circuit
The gate terminal of T has a gate bias circuit for supplying a gate bias voltage set by voltage division of a bias resistor, and a plurality of gate bias circuits are independently provided with a common bias power supply. High frequency amplification module. 2. Each of the gate bias circuits comprises:
2. The high frequency amplification module according to claim 1, wherein the gate bias voltage is set by adjusting one resistance value of the bias resistor with a voltage equal to or lower than the threshold voltage of the FET as an initial value of the gate bias voltage. .