JPH02151109A - Semiconductor amplifier circuit - Google Patents

Abstract

PURPOSE:To constitute an amplifier circuit without less distortion with no adjustment without any load of an external circuit by dividing a threshold level for a FET for a gate bias formed on one and same chip and supplying the divided voltage to the gate of the FET. CONSTITUTION:An amplifier FET 6 and a gate bias FET 12 are formed on one and same chip at the same time. Thus, a pinch-off voltage Vp or a threshold voltage of both the FETs 6, 12 is made nearly equal to each other. A resistor 9a limiting an input current up to an offset IDS is connected to a bias power supply terminal 5 to make the voltage across the FET 12 equal to a voltage Vp. Moreover, the voltage Vp is divided by gate bias resistors 10a, 10b. In the case of class A operation, when the resistance of both the resistors 10a, 10b is selected equal, a voltage 1/2Vp is fed to a gate of the FET 6 via a gate series resistor 8 as a bias voltage. Thus, the selection of the bias point of the amplifier circuit in response to the division ratio of the resistors 10a, 10b is attained with no adjustment.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor amplifier circuit, and mainly uses GaAsF.
This invention relates to a power amplifier circuit using ET.

[Conventional technology]

FIG. 2 shows a power amplifier circuit using a commonly used FET. The high frequency signal enters the FET 6 from the input terminal 1 via the DC cut capacitor 7 and is amplified, and the output appears at the connection point between the load resistor 11 and the drain of I'ET 6, and the capacitor 7
A high-frequency output signal is obtained at terminal 2 through . A bias voltage applied to the gate of the FET 6 when amplifying a high frequency signal is supplied from the terminal 5, and the bias voltage suitable for the FET is adjusted by the adjustment resistor 9b.

In order to perform class A operation, the gate bias voltage of the FET 6 is supplied from the bias power supply terminal 5, and the drain current due to the gate bias voltage is the maximum drain current IDS of the FET.
Set the gate voltage to the point where it becomes 1/2 of the gate bias voltage 8
Adjust with b and apply. In this case, the gate voltage is at terminal 5
is divided by the resistors 9b and 10, and the divided voltage is F
If the FET's drain current is adjusted to approximately 1/2 of the threshold voltage of the ET or the pinch-off voltage, which is approximately the same value, the drain current of the FET will also be approximately 1/2 of the maximum drain current IDS, and the A
satisfies the conditions for class operation.

Due to variations in FET characteristics, the gate voltage must be adjusted for each amplifier circuit by the gate bias resistor 9b.
A circuit with low distortion cannot be obtained. Figure 3 shows an example of FET characteristics. By adjusting the gate bias voltage to approximately 1/2Vp (pinch-off voltage), the drain current can be reduced by 1/2.
This shows that the signal is amplified centering on the IDS. Therefore, if the gate bias voltage is biased, the drain output waveform will be distorted, which is not desirable as an amplifier circuit.

[Problem to be solved by the invention]

In conventional class A semiconductor amplifier circuits using FETs, in order to obtain the optimum gate bias voltage, each amplification stage is adjusted using a variable adjustment resistor 9b shown in FIG. When using a large number of circuits, FETs with large variations, or integrated circuits (integrated circuits) using FETs and resistors, there are problems such as the need to externally attach an adjustment resistor for miniaturization, and the need for adjustment. There was a point.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor amplifier circuit that can be made in a small size and has a high yield, with almost no adjustment required.

[Means to solve the problem]

In the semiconductor amplifier circuit according to the present invention, the characteristics of another FET formed on the same chip as the FET are almost the same so that the gate bias voltage is automatically set to a point with little distortion even if there are variations in the FET characteristics. Taking advantage of this fact, the threshold voltage (approximately equal to the pinch-off voltage) is divided and supplied to the gate of the FET, thereby eliminating an external adjustment circuit or adjustment resistor.

[Effect]

In this invention, even if the input signal is excessive and the gate bias voltage value of the FET deviates, the gate bias voltage setting value is automatically created at the time of circuit creation by using the FET characteristics that have approximate characteristics within the same chip. be done.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 12 is a gate bias FET 59a.
is a gate bias resistance, and 10a and 10b are gate bias resistances.

Next, the operation will be explained.

The input signal is supplied from terminal 1 through capacitor 7 to the gate of FET θ. In the example of class A operation, the gate bias voltage is set at approximately 1/2 I DS as shown in FIG. However, if there are variations in FET characteristics,
A constant voltage will cause distortion in the output waveform. Therefore, FE
It is necessary to superimpose a gate bias voltage such that the drain current becomes 1/21 DS even with variations in T with the high frequency input signal and supply it to the gate of the FET 8. In the present invention, the amplification FET 6 and the gate bias FET 12 are simultaneously formed on the same chip. Therefore, the vp or threshold voltages shown in FIG. 3 of both FETs 6 and 12 are approximately equal.

The bias power supply terminal 5 is connected to a third voltage (Vp).Furthermore, the Vp is divided by gate bias resistors 10a and 10b.In the case of class A operation, by making the resistance values of both resistors 10a and 10b equal, 1/2Vp is applied to the gate. It is supplied as a bias voltage to the gate of FET 6 via series resistor 8.

FIG. 3 shows an example of the characteristics of FETs 6 and 12 shown in FIG. 2, and both FETs have similar characteristics and have almost the same value of Vp. In addition, when performing class A operation with the gate bias voltage set to 1/2 IDS, the gate voltage vs. drain current characteristic can be considered to be almost a straight line in practical terms, and the Vp of FET12
If the voltage is divided into two and supplied as a bias voltage to the gate of the FET 6, the conditions for a class-A operation amplifier circuit will be satisfied. Therefore, the gate bias resistor 9a is selected so that the offset current (IDS in FIG. 3) is at least 10 times the current flowing out from the gate of the FET 8 due to the gate bias voltage.

In a normal FET, the gate current is 1 for every 1 mm of gate width.
Offset IDS shown in Figure 3 for FET12 as low as μA
Since the ratio of 10 times or more can be obtained, even if the Vp of FET 12 is divided by the resistors LOa and 10b, the variation in Vp will be negligible, and the bias point of the amplifier circuit can be set according to the division ratio of the resistors 10a and 10b. The choice becomes possible without adjustment.

Although the above embodiment shows a resistive load type amplifier circuit,
The present invention can also be applied to a circuit whose load is an inductance load 1 published constant circuit, and has similar effects. Further, in the above embodiment, an example of class A operation is shown, but depending on the division ratio of Vp, the present invention can be automatically applied to operation modes other than class A operation, such as class B and class 0.

〔Effect of the invention〕

As described above, according to the present invention, the threshold voltage of gate bias FETs formed on the same chip is divided,
Since this is supplied to the gate of the FET, any gate bias voltage can be applied regardless of the FET variation, and an amplifier circuit with low distortion can be built at low cost without any adjustment or external circuit load. There are configurable effects.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a class A amplifier circuit using an FET according to an embodiment of the present invention, Fig. 2 is a diagram showing a conventional circuit example, and Fig. 3 shows characteristics of gate bias voltage and drain current of the FET. It is a diagram. 1 is a high frequency input terminal, 2 is a high frequency output terminal, 3 is a power supply terminal, 4 is a ground terminal, 5 is a bias power supply terminal, 6 is a FET
, 7 is an input/output coupling capacitor, 8 is a gate series resistance, 9
．． 10 is a gate bias resistance, 11 is a FET load resistance,
12 is FET for gate bias. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1) In a semiconductor amplifier circuit using FETs, the above-mentioned FE
A gate bias FET is formed in the same chip as T and detects the threshold voltage of the FET, and the detection voltage is arbitrarily divided so that the gate bias voltage is applied according to the characteristic variation of the FET. . A semiconductor amplifier circuit comprising: a detection voltage dividing means for determining a gate bias voltage of the FET.