JPH0846446A - Gate bias circuit - Google Patents

Abstract

PURPOSE:To cope with the variation of the pinch-off voltage of an FET. CONSTITUTION:This circuit is provided with an FETQ 1 which is formed on the same chip as an FETQ 5 for depression mode high frequency amplification where a gate is connected with a RF input terminal T5, a drain is connected with a RF output terminal T6 and a source is connected with a ground terminal T7 and whose drain is connected with a Vdd terminal T1 and source is connected with the gate, an FETQ 2 where the gate is formed on the same chip as the Q5 so as to be wider than the gate of the Q1, the drain is connected with the source of the Q1 and the source is connected with a ground terminal T2, a resistor R1 to be connected between the gates of the Q1 and Q2 on the chip, a resistor R2 to be connected between the gate of the Q2 and a Vss terminal T3 on the chip, a resistor R3 to be connected between the gate of the Q2 and the gate of the Q5 on the chip and an exterior capacitor C1 whose one end is grounded and the other end is connected with the gate of the Q2 via the exterior terminal T4 of the chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate bias circuit of a depletion mode type field effect transistor used in, for example, a high frequency band amplifier circuit.

[0002]

2. Description of the Related Art As is well known, a depletion mode type GaAs field effect transistor (hereinafter referred to as FET) is used in a high frequency power amplifier of a car phone, a mobile phone, etc. A negative bias (usually about -2 to -3V) for setting the operating point is applied. This voltage is the Idss when there is no high frequency signal when the FET is operated in class B (no input).
It is often selected to be about 1/10 of (drain current when gate voltage = 0V).

However, in the conventional gate bias circuit as described above, since the voltage is simply applied to the gate, the gate voltage must be changed when the pinch-off voltage of the FET changes. The FET pinch-off voltage usually varies widely, and often varies among manufacturing lots, wafers, and in some cases, chips in the wafer.

Therefore, in the conventional gate bias circuit, the resistance value for the gate bias is changed for each lot, each wafer, or each chip in one wafer, an expensive variable resistor is inserted, or pinch-off is performed at the time of shipping the FET. It was necessary to finely divide the voltage rank.

[0005]

As described above, in the conventional gate bias circuit, there are variations in the pinch-off voltage of the FET, so that lot-to-lot, wafer-to-wafer, or wafer-to-wafer or 1-to-wafer.
It was necessary to change the resistance value for gate bias for each chip in the wafer, insert an expensive variable resistor, or finely classify the pinch-off voltage at the time of shipping the FET.

Therefore, the present invention has been made to solve the above problems, and a gate bias circuit capable of coping with variations in the pinch-off voltage of FETs without requiring complicated work and using expensive parts. The purpose is to provide.

[0007]

In order to solve the above-mentioned problems, a first invention is that a control electrode is connected to a high-frequency signal input terminal, one controlled electrode is connected to a high-frequency signal output terminal, and the other control electrode is It is formed on the same chip as the depletion mode type high frequency amplification FET connected to the reference potential connection terminal in the same process, one controlled electrode is connected to the positive power supply connection terminal, and the other controlled electrode is the control electrode. The first FET connected to the first FET and the high-frequency amplification FET on the same chip on the same step, and the control electrode is the first FET.
Second FET formed so as to be wider than the control electrode, the one controlled electrode being connected to the other controlled electrode of the first FET, and the other controlled electrode being connected to the reference potential connection terminal. And the first and second F on the chip.
A first resistor connected between the control electrodes of the ET; a second resistor connected between the control electrode of the second FET and the negative power supply connection terminal on the chip; and a second resistor connected on the chip. A third resistor connected between the control electrode of the second FET and the control electrode of the high frequency amplification FET, one end of which is connected to a reference potential point and the other end of which is connected through an external terminal of the chip. An external capacitor connected to the control electrode of the second FET, and connecting a positive power supply and a negative power supply to the chip so that a bias voltage is applied to the control electrode of the high frequency amplification FET. It is characterized by having done.

A second aspect of the present invention is a depletion mode type high frequency in which a control electrode is connected to a high frequency signal input terminal, one controlled electrode is connected to a high frequency signal output terminal, and the other control electrode is connected to a reference potential connection terminal. A first FET formed on the same chip as the amplifying FET in the same step, one controlled electrode being connected to the positive power supply connection terminal, and the other control electrode being connected to the control electrode; F
The control electrode is formed on the same chip as the ET in the same process as the first electrode.
Second control electrode is formed to be wider than the control electrode of the first FET, one controlled electrode is connected to the other controlled electrode of the first FET, and the other controlled electrode is connected to the reference potential connection terminal. FET, a first resistor connected between control electrodes of the first and second FETs on the chip, and a control electrode of the second FET on the chip and a negative power supply connection terminal. A second resistor connected to the second resistor, an external additional circuit connected between the control electrode of the second FET and the control electrode of the high frequency amplification FET via an external terminal of the chip, and one end thereof. Is connected to a reference potential point, and the other end is connected to the control electrode of the second FET through an external terminal of the chip, and a positive power supply and a negative power supply are connected to the chip. To control the high-frequency amplifier FET by Characterized by being adapted to apply a bias voltage to the.

According to a third aspect of the present invention, in the structure of the first aspect, the high-frequency amplification FET is formed on the same chip in the same step, and the control electrode is connected to the control electrode of the second FET. , One controlled electrode is the second F
A third FET connected to the other controlled electrode of ET,
It is formed on the same chip as the high frequency amplification FET in the same step, one controlled electrode is connected to the other controlled electrode of the third FET, and the control electrode together with the other controlled electrode is the negative electrode. Fourth FE connected to power supply connection terminal
T and the other controlled electrode of the third FET and one controlled electrode of the fourth FET are connected to the external capacitor via the external terminal, and
It is characterized in that it is connected to the control electrode of the high-frequency amplification FET via the resistor.

According to a fourth invention, in the first or second invention, a plurality of the first FETs are formed on the same chip as the high frequency amplification FETs in the same step, and each control electrode and The other control electrode is commonly connected, each one control electrode is connected to an independent positive power supply connection terminal, and any positive power supply connection terminal is selectively connected to the positive power supply. To do.

[0011]

In the gate bias circuit of the first aspect of the present invention, when the pinch-off voltage of the first FET changes, the gate potential of the second FET also changes.
Since the proportional relationship is maintained, by applying this voltage to the high-frequency amplification FET in the same chip, that is, having the same pinch-off voltage via the third resistor, the current flowing in this FET is also Idss regardless of the pinch-off voltage. The proportional relationship is maintained. Therefore, automatic bias setting can be realized, and it is not necessary to reset the gate bias even if the pinch-off voltage of the FET fluctuates.

In the gate bias circuit of the second invention, the gate of the second FET and the gate of the high frequency amplification FET are not connected inside the chip but are connected outside the chip through an additional circuit, so that, for example, high frequency amplification is performed. The gate impedance of the power FET to the optimum value, and Ids
A bias point different from the proportional convention of s can be set.

In the gate bias circuit of the third invention, a source follower circuit composed of the third and fourth FETs is inserted between the gate of the second FET and the gate of the high frequency amplification FET, and the second follower circuit is provided. FET for high frequency amplification by converting high impedance at the gate point of FET to low impedance
To increase the first and second resistances while maintaining the resistance ratio and reduce the gate widths of the first and second FETs to reduce the power consumption and stabilize the circuit operation. Plan.

In the gate bias circuit according to the fourth aspect of the present invention, a plurality of the first FETs are formed and selectively connected to a positive power source, so that the ratio of the drain current at the time of no input of the high frequency amplification FET and the Idss is increased. It can be set to several types only by the external connection method.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a gate bias circuit according to the present invention. In FIG. 1, the inside of the broken line is formed on the same chip. Here, Q5 in the figure is a depletion mode type GaAs FET that actually amplifies a high frequency band. Further, Q1 and Q2 are both FETs having the same or very close characteristics per unit gate width as Q5, and the gate width of Q1 is set narrower than the gate width of Q2.

The gate and source of Q1 are connected to the drain of Q2, the drain of Q1 is connected to the fixed positive power supply Vdd via terminal T1, and the source of Q2 is grounded to zero potential via terminal T2. A resistor R1 is connected between the source of Q1 and the gate of Q2, and a resistor R1 is connected between the gate of Q2 and a terminal T3 connected to the fixed negative power supply Vss.
2 are connected.

The gate of Q5 and the gate of Q2 are connected via a resistor R3. The gate of Q2 is grounded through the terminal T4 and the external capacitor C1. The gate of Q5 is connected to the terminal T5 to which the high frequency signal RF is supplied, the drain is connected to the terminal T6 which outputs the amplified high frequency signal RF, and the source is grounded via the terminal T7.

The operation of the above arrangement will be described below.

First, for example, all the FETs Q1, Q2, Q
5, it is assumed that 1/10 of Idss (saturated drain current when the gate voltage is 0V) has a gate voltage (as Vgsq) flowing as a drain current of -2.3V. In addition, by applying + 5V to Vdd and -5V to Vss, Idss of Q1 is 2.9 mA, Idss of Q2.
Is 29 mA (that is, the gate width of Q2 is 10 times the gate width of Q1), R1 is 45 kΩ, and R2 is 25 kΩ. Further, it is assumed that the saturation characteristics of all the FETs are sufficiently good and the drain current does not change when the drain-source voltage is 1.5V to 10V.

When the voltage at each point is calculated in this state, Q1
Source is about + 2.5V, Q2 gate is about -2.3V
Becomes The circuit works as follows.

First, since the gate and the source of Q1 are short-circuited, if a voltage of 1.5 V or more is applied between the drain and the source, 2.9 mA is applied as the drain voltage. Since the resistance values of R1 and R2 are high, the current becomes the drain current of Q2 almost as it is, and the drain current of Q2 becomes about 1/10 of Idss. Q2 that realizes this
Has a gate potential of -2.3 V and the voltage across R2 is 2.7 V, the current flowing through R2 is equal to the current flowing through R1 and is 0.108 mA. Therefore, Q
The source potential of 1 is + 2.5V.

This state is a stable state and a little Vd
Even if there are fluctuations in d and Vss, the source voltage of Q1 is +
As long as it is within the range of 1.5V to 3.5V, Q1 and Q2
Shows a saturation characteristic, the gate potential of Q2 is always Ids
It is kept at a value that realizes approximately 1/10 of s.

If the pinch-off voltage of the FET changes, the gate potential of Q2 also changes, but Ids
It is a value that realizes 1/10 of s. This voltage is applied to the resistor R3
The current flowing in Q5 is 1/10 of Idss regardless of the pinch-off voltage by applying the same to Q5 having the same pinch-off voltage in the same chip via.

As described above, in the gate bias circuit of the embodiment of FIG. 1, when the pinch-off voltage of the FET Q1 changes, the gate potential of the FET Q2 also changes, but since the proportional relationship of Idss is maintained, this voltage is resistance. By adding to the high frequency amplifying FET Q5 having the same pinch-off voltage in the same chip through R3, this FETQ
The current flowing in 5 also maintains the proportional relationship of Idss regardless of the pinch-off voltage. Therefore, automatic bias setting can be realized, and it is not necessary to reset the gate bias even if the pinch-off voltage of the FET fluctuates.

As a trial, the characteristics of a FET having a pinch-off voltage of about -3.2 V under a fixed gate bias voltage were examined.
The permissible range of the pinch-off voltage required for controlling to ± 20% in the vicinity of 1/10 becomes ± 0.09V. On the other hand, when this circuit is adopted, it can be expanded to ± 0.30V.

This is the result when trying to control the drain current without input as constant as possible, but when trying to set the drain current without input to 1/10 of Idss of the FET, , The allowable range of pinch-off voltage is further expanded. These effects are very effective in achieving a large yield improvement and no adjustment.

FIG. 2 shows the configuration of the second embodiment.
It is a modification of the first embodiment shown in FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, the gate of Q2 and the gate of Q5 of FIG. 1 are not connected inside the chip but are connected via the outside of the chip.

In the above structure, the bias voltage generated at the gate of Q2 can be applied to the gate of Q5 after being processed by an external additional circuit. As the external additional circuit, in addition to resistors only, resistors R4 and R
A combination circuit of 5 and the inductance L1 or a circuit to which a bias power source is added can be considered.

As described above, in the gate bias circuit of the embodiment of FIG. 2, the gate of the FET Q2 and the high frequency amplifying FET Q are
By connecting the gate of 5 through the additional circuit outside the chip without connecting the inside of the chip, for example, FE for high frequency amplification
The gate impedance of TQ5 can be changed to an optimum value, or a bias point different from the Idss proportional convention can be set. Therefore,
The gate impedance of the FET Q5 can be changed to an optimum value, and it is possible to set a bias point different from 1/10 of Idss.

FIG. 3 shows the configuration of the third embodiment.
This is also a modification of the first embodiment shown in FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, a source follower circuit composed of FETs Q3 and Q4 is inserted between the gate Q2 and the gate Q5 in FIG.

That is, the gate of Q3 is connected to the gate of Q2, the drain of Q3 is grounded via the terminal T2, the source of Q3 and the drain of Q4 are connected together and connected to the gate of Q5 via the resistor R3. The gate and source of Q4 are connected together and connected to Vss via terminal T3.

In the above structure, since Q3 and Q4 are source follower circuits, the source potential of Q3 changes following the source potential of Q4.

As described above, in the gate bias circuit of the embodiment shown in FIG. 3, the gate of the FET Q2 and the high frequency amplification FET Q are connected.
A source follower circuit composed of FETs Q3 and Q5 is inserted between the gate of the FET 5 and the gate of the FET Q5 to convert the high impedance at the gate point of the FET Q2 into a low impedance and supply it to the gate of the high frequency amplification FET Q5. R
2 is increased while maintaining the resistance ratio, and the gate widths of the FETs Q1 and Q2 are reduced to reduce power consumption and stabilize the circuit operation. In this way, by adding the source follower circuit, the high impedance at the gate point of Q2 can be converted to low impedance and supplied to the gate of Q5. Therefore, the resistance values of R1 and R2 are increased while maintaining the ratio, and Q1
Since the gate width of Q2 and Q2 can be reduced, low power consumption can be realized. Furthermore, the bias circuit impedance seen from the gate of Q5 is low, so the circuit operation becomes stable.

FIG. 4 shows the configuration of the fourth embodiment.
This is also a modification of the first embodiment shown in FIG. 4, the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, the source and gate of FIG. 1 are connected together and have one or more FETs Q1 'connected to the source and gate of Q1. The drain of Q1 'is drawn out through the terminal T8.

In the above structure, when a power supply voltage (for example, +5 V) is applied to either or both of Vdd and Vdd ', the operation is similar to that of the first embodiment. At this time, by appropriately selecting the gate widths of Q1 and Q1 ',
The ratio of the drain current of Q5 when there is no input and Idss can be set to several types only by the external connection method. Q
When 1'is one, it can be deformed in a maximum of three ways, and when Q1 'is two, it can be deformed in a maximum of seven ways. in this way,
In the gate bias circuit shown in FIG. 4, a plurality of FETs Q1 are formed and selectively connected to a positive power source, so that the ratio of the drain current at no input of the high frequency amplification FET to Idss can be determined only by the external connection method. It can be set to several types with.

In the above-mentioned embodiments, the example of the depletion mode type FET of GaAs has been described, but the present invention is not limited to GaAs but Si, AlGaAs, InP.
It is also applicable to FETs made of other materials such as.

In the above embodiment, all FEs are
Although T is a single mode type, it can be similarly applied to a dual mode type.

The number of the FET Q5 receiving the supply of the bias is one in the embodiment, but it may be two or more.
A circuit using one or more FETs may be formed on the chip.

In the above embodiment, the operating point current is approximately I
Although the case of about 1/10 of dss has been described, the present invention is not limited to this, and any ratio of less than 1 is applicable, including about 1/2 of class A operation.

The present invention is particularly effective when used in a high frequency power amplification section of a car phone, a mobile phone or the like, but it goes without saying that it can also be applied to a high frequency amplification section of other electronic equipment.

In addition, the present invention is not limited to the above-mentioned embodiments, but can be similarly implemented even if various modifications are made without departing from the gist of the present invention.

[0043]

As described above, according to the present invention, no complicated work is required, expensive components are not used, and F
It is possible to provide a gate bias circuit that can cope with variations in ET pinch-off voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a gate bias circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of a gate bias circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third embodiment of a gate bias circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment of a gate bias circuit according to the present invention.

[Explanation of symbols]

 Q1 to Q4, Q1 '... FET Q5 ... Depletion mode type FET R1 to R5 ... Resistor C1 ... Capacitor L1 ... Inductance T1 to T8 ... Terminal Vdd ... Fixed positive power supply Vss ... Fixed negative power supply

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/337 29/808 H03F 3/195 8839-5J

Claims (4)

[Claims] 1. A depletion mode high frequency amplifying FET in which a control electrode is connected to a high frequency signal input terminal, one controlled electrode is connected to a high frequency signal output terminal, and the other control electrode is connected to a reference potential connection terminal. A first FET formed on the same chip in the same step and having one controlled electrode connected to the positive power supply connection terminal and the other controlled electrode connected to the control electrode, and the same high-frequency amplification FET In the same step, a control electrode is formed on the chip so as to be wider than the control electrode of the first FET, one controlled electrode is connected to the other controlled electrode of the first FET, and the other controlled electrode is connected. A second FET having a control electrode connected to a reference potential connection terminal; a first resistor connected between the control electrodes of the first and second FETs on the chip; and a second resistor on the chip. FE A second resistor connected between the control electrode of T and the negative power supply connection terminal, and connected between the control electrode of the second FET and the control electrode of the high frequency amplification FET on the chip. A third resistor; and an external capacitor having one end connected to a reference potential point and the other end connected to a control electrode of the second FET via an external terminal of the chip, the chip A bias voltage is applied to the control electrode of the high frequency amplification FET by connecting a positive power source and a negative power source to the gate bias circuit. 2. A depletion mode high frequency amplifying FET in which a control electrode is connected to a high frequency signal input terminal, one controlled electrode is connected to a high frequency signal output terminal, and the other control electrode is connected to a reference potential connection terminal. A first FET, which is formed on the same chip in the same step, one controlled electrode is connected to a positive power supply connection terminal, and the other control electrode is connected to the control electrode, and the same chip as the high frequency amplification FET In the same step, the control electrode is formed to be wider than the control electrode of the first FET, one controlled electrode is connected to the other controlled electrode of the first FET, and the other controlled electrode is formed. A second FET whose electrode is connected to a reference potential connection terminal; a first resistor connected between the control electrodes of the first and second FETs on the chip; and a second resistor on the chip. FET A second resistor connected between the control electrode and the negative power supply connection terminal, and between the control electrode of the second FET and the control electrode of the high frequency amplification FET via an external terminal of the chip. And an external capacitor having one end connected to the reference potential point and the other end connected to the control electrode of the second FET through the external terminal of the chip. A gate bias circuit, wherein a bias voltage is applied to the control electrode of the high frequency amplification FET by connecting a positive power supply and a negative power supply to the chip. 3. A depletion mode type high frequency amplification FET in which a control electrode is connected to a high frequency signal input terminal, one controlled electrode is connected to a high frequency signal output terminal, and the other control electrode is connected to a reference potential connection terminal. A first FET formed on the same chip in the same step and having one controlled electrode connected to the positive power supply connection terminal and the other controlled electrode connected to the control electrode, and the same high-frequency amplification FET In the same step, a control electrode is formed on the chip so as to be wider than the control electrode of the first FET, one controlled electrode is connected to the other controlled electrode of the first FET, and the other controlled electrode is connected. A second FET whose control electrode is connected to the reference potential connection terminal and a high-frequency amplification FET are formed on the same chip in the same step, and the control electrode is connected to the control electrode of the second FET. A third FET whose one controlled electrode is connected to the other controlled electrode of the second FET and a high-frequency amplification FET formed on the same chip in the same step, and one controlled electrode A fourth FE in which an electrode is connected to the other controlled electrode of the third FET, and the control electrode is connected to the negative power supply connection terminal together with the other controlled electrode.
T and the other controlled electrode of the third FET and the fourth FE.
One of the controlled electrodes of T is connected to the external capacitor via the external terminal, and is connected to the control electrode of the high frequency amplification FET via a third resistor. Gate bias circuit to do. 4. A plurality of the first FETs are formed on the same chip as the high frequency amplification FET in the same step, and each control electrode and the other control electrode are connected in common, and one of the first and second control electrodes is connected. 2. The control electrode of is connected to an independent positive power source connection terminal, and any positive power source connection terminal is selectively connected to the positive power source.
2. The gate bias circuit according to any one of 2.