JPH0513608A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0513608A
JPH0513608A JP16571191A JP16571191A JPH0513608A JP H0513608 A JPH0513608 A JP H0513608A JP 16571191 A JP16571191 A JP 16571191A JP 16571191 A JP16571191 A JP 16571191A JP H0513608 A JPH0513608 A JP H0513608A
Authority
JP
Japan
Prior art keywords
substrate
frame body
semiconductor chip
frame
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP16571191A
Other languages
Japanese (ja)
Inventor
Takao Nishimura
隆雄 西村
Satoru Murakami
悟 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16571191A priority Critical patent/JPH0513608A/en
Publication of JPH0513608A publication Critical patent/JPH0513608A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To miniaturize a frame body constituting a package and to prevent corrosion of the bonding material of a substrate or a frame body by diminishing dispersion in warp or height of a sealing junction with regard to a semiconductor device having a ceramic package. CONSTITUTION:A device comprises: a ceramic-made substrate 1 which mounts a semiconductor chip 2; a frame body 6 formed into a ring out of a material of a coated metal film 8 or a metal material without drawing work and having an opening 7 which surrounds a wiring 4 on the top of the substrate 1; a lid body 9 mounted on the frame body 6; a sealant 12 interposed between the substrate 1 and the frame body 6 and between the frame body 6 and the lid body 9; and an adhesive 11 which makes the semiconductor chip 2 and the lid body 9 adhered.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、よ
り詳しくは、セラミックパッケージを有する半導体装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a ceramic package.

【0002】[0002]

【従来の技術】セラミックICパッケージは、図3に示
すように、半導体チップ31を載せるセラミック基板3
2と、このセラミック基板32の上で半導体チップ31
を囲む金属製枠体33と、この枠体33を覆う板状のセ
ラミック蓋体34とから構成されており、これらにより
半導体チップ31を封止する。
2. Description of the Related Art As shown in FIG. 3, a ceramic IC package has a ceramic substrate 3 on which a semiconductor chip 31 is mounted.
2 and the semiconductor chip 31 on the ceramic substrate 32.
The semiconductor chip 31 is sealed by a metal frame 33 that surrounds the frame 33 and a plate-shaped ceramic lid 34 that covers the frame 33.

【0003】また、セラミック基板32の上面周縁やセ
ラミック蓋体34の下面には金膜35、36が形成され
る一方、枠体33の表面は金膜37により被覆されてい
る。さらに、枠体33の内周部は、セラミック基板32
上面の配線38と接触しないように絞り加工により持ち
上げられている。
Gold films 35 and 36 are formed on the upper peripheral edge of the ceramic substrate 32 and the lower surface of the ceramic lid 34, while the surface of the frame 33 is covered with a gold film 37. Further, the inner peripheral portion of the frame body 33 has the ceramic substrate 32.
It is lifted by drawing so as not to come into contact with the wiring 38 on the upper surface.

【0004】半導体チップ31を封止する場合には、基
板32上面の配線38に半導体チップ31を接続した状
態で、セラミック蓋体34の中央に薄膜状の半田39を
付けるとともに、セラミック基板32の上面周縁に金錫
合金材40を付ける。そして、セラミック基板32の上
に枠体33とセラミック蓋体34を順に載せ、これらを
加熱炉に入れ、半田39や金錫合金材40をリフローし
て気密封止を行っている。
When the semiconductor chip 31 is sealed, thin-film solder 39 is attached to the center of the ceramic lid 34 while the semiconductor chip 31 is connected to the wiring 38 on the upper surface of the substrate 32, and the ceramic substrate 32 is sealed. The gold-tin alloy material 40 is attached to the peripheral edge of the upper surface. Then, the frame 33 and the ceramic lid 34 are placed in this order on the ceramic substrate 32, placed in a heating furnace, and the solder 39 and the gold-tin alloy material 40 are reflowed to hermetically seal.

【0005】[0005]

【発明が解決しようとする課題】しかし、このような構
造によれば、枠体33を絞り加工する関係上その幅を1
mm程度確保する必要があるため、パッケージの外形の縮
小化に支障をきたす。しかも、絞り形状の枠体33では
封止接合部の反りや封止部の高さ等の安定化に対応しき
れないといった不都合がある。
However, according to such a structure, the width of the frame body 33 is 1 in view of drawing.
Since it is necessary to secure about mm, it hinders the reduction of the outer shape of the package. In addition, there is a disadvantage that the diaphragm-shaped frame body 33 cannot cope with the warp of the sealing joint portion and the stabilization of the height of the sealing portion.

【0006】また、セラミック基板32、枠体33及び
セラミック蓋体34の接合を行う場合に、半田39や金
錫合金材40を溶融するが、これらの接合材料がセラミ
ック蓋体34等の表面の金膜35〜37を伝って移動す
るために、これらの封止材が枠体33の外側で混合して
腐食し易くなり、外観不良が生じたり、クラック発生の
原因になるといった問題がある。
Further, when the ceramic substrate 32, the frame 33 and the ceramic lid 34 are joined, the solder 39 and the gold-tin alloy material 40 are melted, but these joining materials form the surface of the ceramic lid 34 and the like. Since they move along the gold films 35 to 37, these sealing materials are easily mixed and corroded on the outer side of the frame body 33, which causes a problem of appearance failure and crack generation.

【0007】本発明はこのような問題に鑑みてなされた
ものであって、封止接合部の反りや高さのばらつきを少
なくし、パッケージを構成する枠体の小型化を図るとと
もに、基板や枠体等の接合材の腐食を防止することがで
きる半導体装置を提供することを目的とする。
The present invention has been made in view of the above problems, and is intended to reduce the warp and height variation of the sealing joint portion, to reduce the size of the frame constituting the package, and to reduce the board and substrate. An object of the present invention is to provide a semiconductor device capable of preventing corrosion of a bonding material such as a frame body.

【0008】[0008]

【課題を解決するための手段】上記した課題は、図1に
例示するように、半導体チップ2を載置するセラミック
製の基板1と、金属膜8に被覆された材料または金属材
により絞り加工を施さずに環状に形成され、かつ前記基
板1上面の配線4を囲む開口部7を有する枠体6と、前
記枠体6の上に載置される蓋体9と、前記基板1と前記
枠体9、前記枠体9と前記蓋体6の間にそれぞれ介在さ
れる封止材12と、前記半導体チップ2と前記蓋体9を接
着する接着剤11とを有することを特徴とする半導体装置
によって達成する。
The above-mentioned problems are, as illustrated in FIG. 1, drawn by a ceramic substrate 1 on which a semiconductor chip 2 is mounted and a material coated with a metal film 8 or a metal material. A frame body 6 which is formed in an annular shape without being formed and has an opening 7 surrounding the wiring 4 on the upper surface of the substrate 1, a lid body 9 mounted on the frame body 6, the substrate 1 and the A semiconductor comprising a frame body 9, a sealing material 12 respectively interposed between the frame body 9 and the lid body 6, and an adhesive 11 for bonding the semiconductor chip 2 and the lid body 9 together. Achieved by the device.

【0009】[0009]

【作 用】本発明によれば、枠体を絞り加工せずに環状
に形成するとともに、その開口部7の大きさを基板1表
面の配線6を囲む程度の広さにしている。
[Operation] According to the present invention, the frame body is formed into an annular shape without being drawn, and the size of the opening 7 is set so as to surround the wiring 6 on the surface of the substrate 1.

【0010】従って、絞り加工する必要がないため、枠
体6の幅を狭くすることが可能になり、その分だけ基板
1上で占める面積が狭くなり、半導体装置の小型化を一
層図ることが可能になる。しかも絞り加工を行っていな
いので、封止接合部の反りや封止部の高さのばらつきが
少なくなる。
Therefore, since it is not necessary to perform the drawing process, the width of the frame body 6 can be reduced, and the area occupied on the substrate 1 is reduced accordingly, and the semiconductor device can be further miniaturized. It will be possible. Moreover, since the drawing process is not performed, the warp of the sealing joint portion and the variation of the height of the sealing portion are reduced.

【0011】また、基板1、蓋体9と枠体6との間に金
錫合金等の封止材12を介在させる一方、枠体6の幅を
狭くして半導体チップ2からの距離を大きくしているた
め、半導体チップ2上の接着材11が外部に移動して封
止材12と混合し難くなり、接合部分の亀裂は無くな
り、しかも外観が良くなる。
Further, a sealing material 12 such as a gold-tin alloy is interposed between the substrate 1, the lid body 9 and the frame body 6, while the width of the frame body 6 is narrowed to increase the distance from the semiconductor chip 2. As a result, the adhesive 11 on the semiconductor chip 2 moves to the outside and is difficult to mix with the encapsulant 12, cracks at the joint are eliminated, and the appearance is improved.

【0012】[0012]

【実施例】そこで、以下に本発明の実施例を図面に基づ
いて説明する。図1は、本発明の一実施例を示す装置の
断面図及び部分拡大断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view and a partially enlarged sectional view of an apparatus showing an embodiment of the present invention.

【0013】図において符号1は、内部に配線層(不図
示)を有する上下面矩形状のセラミック製基板で、その
上面には、TAB法やフリップチップ法により半導体チ
ップ2のバンプ3に接続される配線4が配置され、ま
た、その上面縁部に沿った領域には金膜5が形成されて
いる。
In the figure, reference numeral 1 is a ceramic substrate having a rectangular upper and lower surfaces having a wiring layer (not shown) inside, and the upper surface thereof is connected to the bumps 3 of the semiconductor chip 2 by the TAB method or the flip chip method. The wiring 4 is arranged, and the gold film 5 is formed in the region along the upper surface edge portion.

【0014】6は、基板1の上に取付けられるコバール
製の枠体で、絞り加工されずにエッチングにより環状に
成形されており、その中央の開口部7は基板1上面の配
線4に接触しない大きさとなっている。また、枠体6
は、半導体チップ2とほぼ同じ高さを有するとともに、
その高さ方向の断面が図1(b) に示すような矩形状とな
るように形成され、さらに、その表面は金膜8によって
一様に覆われている。
Reference numeral 6 denotes a Kovar frame body mounted on the substrate 1, which is formed into an annular shape by etching without being drawn, and the central opening 7 does not come into contact with the wiring 4 on the upper surface of the substrate 1. It has become large. Also, the frame body 6
Has almost the same height as the semiconductor chip 2, and
The cross section in the height direction is formed to have a rectangular shape as shown in FIG. 1 (b), and the surface thereof is uniformly covered with the gold film 8.

【0015】9は、枠体7の上面に載置される板状のセ
ラミック製蓋体で、その下面には一様に金膜10が形成
され、また、半導体チップ2と当接する領域にはさらに
半田(Pb・Sn合金)11が付けられており、この半田1
1により半導体チップ2を蓋体9に接着するように構成
されている。
Reference numeral 9 denotes a plate-shaped ceramic lid which is placed on the upper surface of the frame body 7. The gold film 10 is uniformly formed on the lower surface of the lid, and the area where it abuts the semiconductor chip 2 is provided. Furthermore, solder (Pb / Sn alloy) 11 is attached.
The semiconductor chip 2 is configured to be bonded to the lid body 9 by 1.

【0016】12は、基板1及び蓋体9の間に枠体7を
接着するための金錫合金材で、基板1と蓋体9の縁部に
沿った環状領域に付けられており、これを溶融、冷却す
ることにより基板1と蓋体9に挟まれた枠体7を密着固
定するように構成されている。
Reference numeral 12 is a gold-tin alloy material for adhering the frame 7 between the substrate 1 and the lid 9, which is attached to an annular region along the edges of the substrate 1 and the lid 9. The frame 1 sandwiched between the substrate 1 and the lid 9 is closely fixed by melting and cooling.

【0017】なお、図中符号13は、セラミック製基板
1の下面に取付けられたピンを示している。上記した実
施例において、枠体6は絞り加工されていないために、
その幅を0.5mm程度に狭くすることが可能になり、その
分だけ基板1に占める面積が狭くなり、半導体装置の小
型化を一層図ることが可能になる。しかも絞り加工を行
っていないので、封止接合部の反りや封止部の高さのば
らつきが少なくなる。
Reference numeral 13 in the drawing denotes a pin attached to the lower surface of the ceramic substrate 1. In the above-mentioned embodiment, since the frame body 6 is not drawn,
The width can be reduced to about 0.5 mm, and the area occupied by the substrate 1 is reduced accordingly, and the size of the semiconductor device can be further reduced. Moreover, since the drawing process is not performed, the warp of the sealing joint portion and the variation of the height of the sealing portion are reduced.

【0018】また、半導体チップ2を取付けた基板1と
枠体6と蓋体9を順に重ね合わせ、これらを加熱炉(不
図示)に入れて330℃程度に加熱すると、それらの間
に介在させた半田11や金錫合金材12が溶融する。
The substrate 1 on which the semiconductor chip 2 is mounted, the frame body 6 and the lid body 9 are stacked in this order, and they are placed in a heating furnace (not shown) and heated to about 330.degree. The solder 11 and the gold-tin alloy material 12 are melted.

【0019】この結果、基板1、蓋体9が金錫合金材1
2によって枠体6と接合する一方、枠体6が従来装置に
比べて半導体チップ2から離れているため、半導体チッ
プ2上の半田11が枠体6を超えて外部に漏れなくな
り、半導体装置の外部において半田11と金錫合金材1
2が混合することはない。このため、封止接合部から腐
食が発生して亀裂が生じることはなく、外観も良好にな
る。
As a result, the substrate 1 and the lid 9 are made of the gold-tin alloy material 1.
While it is joined to the frame body 6 by means of 2, the frame body 6 is farther from the semiconductor chip 2 than the conventional device, so that the solder 11 on the semiconductor chip 2 does not leak beyond the frame body 6 to the outside of the semiconductor device. Solder 11 and gold-tin alloy material 1 outside
The two never mix. For this reason, corrosion does not occur from the sealed joint and cracks do not occur, and the appearance is also good.

【0020】なお、上記した枠体6はコバールにより形
成したが、セラミック等を金によりメタライズしたも
の、或いは42合金のような金属材を用いてもよい。
Although the frame 6 is made of Kovar, it is also possible to use a metallized ceramic or the like, or a metal material such as 42 alloy.

【0021】[0021]

【発明の効果】以上述べたように本発明によれば、枠体
を絞り加工せずに環状に形成するとともに、その開口部
の大きさを基板表面の配線を囲む程度の広さにしている
ので、枠体の幅を狭くすることが可能になり、その分だ
け基板上で占める面積が狭くして半導体装置の小型化を
一層図ることができる。
As described above, according to the present invention, the frame is formed into an annular shape without being drawn, and the size of the opening is wide enough to surround the wiring on the substrate surface. Therefore, the width of the frame body can be reduced, and the area occupied on the substrate can be reduced accordingly, and the size of the semiconductor device can be further reduced.

【0022】しかも、絞り加工を行っていないので、封
止接合部の反りや封止部の高さのばらつきを少なくする
ことができる。また、基板、蓋体と枠体との間に金錫合
金等の封止材を介在させる一方、枠体の幅を狭くして半
導体チップからの距離を大きくしているので、半導体チ
ップを固定するための接着材が外部に移動して封止材と
混合しにくくなり、封止接合部における亀裂の発生を防
止し、しかも外観を良くすることが可能になる。
Moreover, since the drawing process is not performed, it is possible to reduce the warp of the sealing joint portion and the variation of the height of the sealing portion. In addition, while the sealing material such as gold-tin alloy is interposed between the substrate, the lid and the frame, the width of the frame is narrowed to increase the distance from the semiconductor chip, so that the semiconductor chip is fixed. It becomes difficult for the adhesive material to move to the outside and mix with the sealing material, which prevents the occurrence of cracks in the sealing joint and improves the appearance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例装置を示す断面図である。FIG. 1 is a sectional view showing an apparatus according to an embodiment of the present invention.

【図2】本発明の一実施例装置を示す斜視図である。FIG. 2 is a perspective view showing an apparatus according to an embodiment of the present invention.

【図3】従来装置の一例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of a conventional device.

【符号の説明】[Explanation of symbols]

1 基板 2 半導体チップ 3 バンプ 4 配線 5、8、10 金膜 6 枠体 7 開口部 9 蓋体 11 半田(接着材) 12 金錫合金材(封止材) 1 Substrate 2 Semiconductor Chip 3 Bump 4 Wiring 5, 8, 10 Gold Film 6 Frame 7 Opening 9 Lid 11 Solder (Adhesive) 12 Gold Tin Alloy (Encapsulation)

Claims (1)

【特許請求の範囲】 【請求項1】半導体チップ(2)を載置するセラミック
製の基板(1)と、 金属膜(8)に被覆された材料または金属材により絞り
加工を施さずに環状に形成され、かつ、前記基板(1)
上面の配線(4)を囲む開口部(7)を有する枠体
(6)と、 前記枠体(6)の上に載置される蓋体(9)と、 前記基板(1)と前記枠体(9)、前記枠体(9)と前
記蓋体(6)の間にそれぞれ介在される封止材(12)
と、 前記半導体チップ(2)と前記蓋体(9)を接着する接
着剤(11)とを有することを特徴とする半導体装置。
Claim: What is claimed is: 1. A ceramic substrate (1) on which a semiconductor chip (2) is mounted, and an annular material without being drawn by a material coated with a metal film (8) or a metal material. Formed on the substrate and the substrate (1)
A frame (6) having an opening (7) surrounding the upper wiring (4), a lid (9) placed on the frame (6), the substrate (1) and the frame Sealing material (12) interposed between the body (9), the frame body (9) and the lid body (6), respectively.
And a bonding agent (11) for bonding the semiconductor chip (2) and the lid body (9).
JP16571191A 1991-07-05 1991-07-05 Semiconductor device Withdrawn JPH0513608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16571191A JPH0513608A (en) 1991-07-05 1991-07-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16571191A JPH0513608A (en) 1991-07-05 1991-07-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0513608A true JPH0513608A (en) 1993-01-22

Family

ID=15817609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16571191A Withdrawn JPH0513608A (en) 1991-07-05 1991-07-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0513608A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633150B2 (en) * 2005-07-13 2009-12-15 Shinko Electric Industries Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
WO2024000941A1 (en) * 2022-06-27 2024-01-04 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633150B2 (en) * 2005-07-13 2009-12-15 Shinko Electric Industries Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
WO2024000941A1 (en) * 2022-06-27 2024-01-04 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981008