JPH05183076A - Semiconductor package - Google Patents

Abstract

PURPOSE:To beforehand prevent mixing between a solder material of a cap sealing part and a solder material of a die bonding part of a semiconductor chip in a semiconductor package for which a heat-radiating member is mounted onto the back surface of the semiconductor chip and the semiconductor chip is sealed between an insulating substrate and a cap, and the heat-radiating member. CONSTITUTION:A cap 3 is so fitted as to encircle a semiconductor chip 5 mounted onto a board 1 having a terminal and the outer periphery is sealed to the board 1. A heat-radiating member 7 is inserted from an opening 6 of the cap 3 opened in the upper part of the semiconductor chip 5 to be die-bonded to the back surface of the semiconductor chip 5 with a solder material 8 and the periphery of the opening 6 of the cap 3 and the heat-radiating member 7 are sealed with a solder material 9 to form a package for semiconductor device. In the heat-radiating member 7, a groove 10 is formed between a die- bonding part and a sealing part between a cap and a heat-radiating member so that the die-bonding part comprising the heat-radiating member 7 and the semiconductor chip 5 can be encircled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for mounting a heat dissipation member on the back surface of a semiconductor chip and sealing the semiconductor chip between an insulating substrate, a cap and a heat dissipation member.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing the whole of a conventional semiconductor package. Reference numeral 1 is an insulating substrate made of ceramic or the like, and a large number of terminals 2 are implanted therein. The insulating substrate 1 is covered with a cap 3 for hermetic sealing, and the outer periphery of the cap is covered.
A space between 3o and the insulating substrate 1 is sealed by a brazing material 4 or welding. Then, in the cap 3, the semiconductor chip 5 is mounted on the insulating substrate 1, and each terminal of the semiconductor chip 5 and the terminal 2 of the insulating substrate 1 are electrically connected.

An opening 6 is formed in the upper portion of the semiconductor chip 5 in the cap 3, and a heat radiating member 7 is inserted through the opening 6 and die-bonded to the back surface of the semiconductor chip 5 so as to conduct heat. Is becoming Also, the cap 3
A space between the peripheral edge 3i of the opening 6 and the heat dissipation member 7 is hermetically sealed with a brazing material.

FIG. 5 is a sectional view showing a state in which the heat radiation member 7, the semiconductor chip 5 and the cap 3 are bonded. The back surface of the semiconductor chip 5 and the heat radiating member 7 are die-bonded with the die portion brazing material 8, and the rim 3i of the opening 6 of the cap 3 and the heat radiating member 7 are
It is hermetically sealed with the brazing material 9 in the sealing portion. Note that bumps and leads are used between the semiconductor chip 5 and the conductor pattern of the insulating substrate 1, or face-down bonding is performed in advance by a flip chip method or the like.

As the die part brazing material 8 for bonding the back surface of the semiconductor chip 5 and the heat radiating member 7 to each other, a PbSn type brazing material which is soft and easily absorbs stress though it is liable to have cavities and poor in airtightness. Is suitable.

On the other hand, as the brazing material 9 for hermetically sealing the gap between the cap 3 and the heat radiating member 7, an AuSn-based brazing material which is excellent in airtightness and is less likely to have cavities is suitable. However, since the AuSn-based brazing material is hard, it is difficult to absorb mechanical and thermal stress, and when used for bonding with the semiconductor chip 5, the semiconductor chip is directly subjected to stress and the semiconductor chip is cracked. There is a risk of As the heat dissipation member 7, a CuW-based or AlN-based material is usually used.

[0007]

As described above, the brazing material is used differently in the sealing portion of the opening 6 of the cap 3 and the die bonding portion of the semiconductor chip and the heat radiating member 7. However, both brazing materials were mixed and melted in the bonding process,
In particular, there is a problem that the thermal shock resistance of the sealing portion is deteriorated.

At the time of brazing, a rectangular ring-shaped brazing material sheet is sandwiched between the cap 3 and the heat radiating member 7, or is once passed through a furnace to be temporarily fixed, and the heat radiating member 7 and the semiconductor chip 5 are connected together. A weight is placed on the semiconductor chip 5 with a rectangular brazing material sheet sandwiched therebetween. Then, it is put in a furnace and heated at a temperature of about 310 to 350 ° C. for about 10 minutes to melt the brazing material, so that both are brazed at once.

However, when the amount of the brazing material is too large, the weight load is too large, or when the brazing material is impacted in a molten state, the AuSn-based brazing material 9 for sealing the cap 3 is die-bonded. When the PbSn-based brazing material 8 for contact is brought into contact with each other, as shown in FIG.

In particular, since the PbSn-based brazing material easily flows, it flows into the AuSn-based brazing material 9 side for sealing, and AuSn and Pb
Since the ternary alloy is formed and becomes brittle, there is a concern that the thermal shock resistance of the brazing material on the sealing side is deteriorated, cracks occur, and the airtightness is lowered.

The technical problem of the present invention is to pay attention to such a problem and to prevent mixing of the brazing material of the cap sealing portion and the brazing material of the die bonding portion of the semiconductor chip. is there.

[0012]

FIG. 1 is a sectional view for explaining the basic principle of a semiconductor package according to the present invention. A cap 3 is attached so as to surround the semiconductor chip 5 mounted on the substrate 1 having terminals, and the outer periphery of the cap 3 is sealed by the substrate 1.

The cap 3 has an opening 6 formed in the upper portion of the semiconductor chip 5, and a heat dissipation member 7 is inserted through the opening 6 and die-bonded to the back surface of the semiconductor chip 5 with a brazing material 8. Further, a space between the periphery of the opening 6 of the cap 3 and the heat dissipation member 7 is sealed with a brazing material 9 of a different type.

According to a first aspect of the present invention, in such a semiconductor package, between the die bonding portion and the cap / heat radiation member, the heat radiation member 7 is surrounded by the die bonding portion between the heat radiation member 7 and the semiconductor chip 5. The configuration is such that the groove 10 is formed between the groove and the sealing portion.

According to a second aspect of the present invention, the heat radiation member 7 includes a die bonding portion and a cap / heat radiation member sealing portion so as to surround the die bonding portion between the heat radiation member 7 and the semiconductor chip 5. This is a configuration in which a convex wall 11 is formed therebetween.

[0016]

As described in claim 1, since the groove 10 is formed between the die bonding portion and the cap-radiating member sealing portion, the brazing material 8 of the die bonding portion and the cap-radiating member sealing are formed. Even if the brazing material 9 of the part melts, it cannot come into contact with each other beyond the groove 10 and thus does not mix with each other.

Further, since the convex wall 11 is formed between the die bonding portion and the cap / heat radiating member sealing portion as in claim 2, the brazing material 8 of the die bonding portion and the cap / heat radiating member are formed. Even if the brazing material 9 of the intersealing portion melts, it cannot pass over the convex wall 11 and come into contact with each other, so that they do not mix and melt with each other.

[0018]

Next, practical examples of how the semiconductor package according to the present invention is embodied will be described. FIG. 2 is a sectional view showing an embodiment of the invention of claim 1. A groove 10 is formed on the surface of the heat dissipation member 7 on the die bonding portion side, between the die bonding portion and the sealing portion with the cap on the outer periphery thereof. The groove 10 may be a rectangular groove as shown in FIG. 1 or a V groove as shown in FIG.

The groove 10 has an effect of preventing the brazing material 8 of the die bonding part and the brazing material 9 of the sealing part of the cap from bridging in the shortest distance, and has a function of melting both the brazing materials 8 and 9. By extending the creepage distance when spreading, the action of preventing the brazing material flowing along the surface of the heat dissipation member 7 from joining is obtained.

FIG. 3 is a sectional view showing an embodiment of the invention according to claim 2. In this embodiment, the convex wall 11 is formed so as to surround the die bonding portion. Also in this case, since the convex wall 11 blocks between both the brazing materials 8 and 9, a bridge at the shortest distance can be prevented and the creeping distance becomes long. Further, since the extra brazing material in the die bonding portion fills the gap between the outer periphery of the semiconductor chip 5 and the convex wall 11, the thermal bonding between the semiconductor chip 5 and the heat dissipation member 7 is further improved.

In the example of FIG. 2, the bumps 12 and the leads 13 are used for face-down bonding for electrical connection between the semiconductor chip 5 and the terminals of the substrate 1.
As in the above example, the bonding may be performed by a flip chip method using the solder bumps 14 or the like.

Further, a plurality of openings 6 are opened in the cap 3,
It is also possible to mount a plurality of semiconductor chips 5 on one substrate by inserting the heat dissipation member 7 from each opening and performing die bonding.

[0023]

As described above, according to the invention of claim 1,
By providing the groove 10 between the die bonding portion of the heat dissipation member 7 and the semiconductor chip 5 and the sealing portion of the cap 3, and by providing the convex wall 11 according to the invention of claim 2, It is possible to surely prevent both the brazing materials 8 and 9 from directly joining at the position of the shortest distance or by flowing along the surface and joining.

Therefore, even if the brazing materials of the die bonding portion and the sealing portion of the cap 3 are different, it is possible to prevent both of the brazing materials from being mixed and melted and to fully exhibit the characteristics of each brazing material. it can. As a result, it is possible to surely perform the sealing and to prevent the semiconductor chip 5 from being stressed.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a basic principle of a semiconductor package according to the present invention.

FIG. 2 is a sectional view showing an embodiment of the invention of claim 1.

FIG. 3 is a sectional view showing an embodiment of the invention of claim 2;

FIG. 4 is a cross-sectional view showing the whole of a semiconductor package.

FIG. 5 is a cross-sectional view showing a sealing portion of a cap and a die bonding portion of a semiconductor chip in a semiconductor package.

FIG. 6 is a cross-sectional view showing mixing and melting of brazing materials in a conventional semiconductor package.

[Explanation of symbols]

 1 Insulating board 2 Terminal 3 Cap 3i Inner circumference of cap (opening edge) 3o Outer circumference of cap 4 Sealing part between cap and substrate 5 Semiconductor chip 6 Cap opening 7 Heat dissipation member 8 Brazing material in die bonding part 9 Brazing material in the sealing part of the cap 10 Groove 11 Convex wall 12 Bump 13 Lead

Claims (2)

[Claims] 1. A cap (3) is attached so as to surround a semiconductor chip (5) mounted on a substrate (1) having a terminal, and the outer periphery of the cap (3) is sealed in the substrate (1) to form a semiconductor chip (5). ) Through the opening (6) of the cap (3) on the upper part of the
And die-bond it to the back surface of the semiconductor chip (5) with the brazing material (8), and then the brazing material (9) between the opening (6) edge (3i) of the cap (3) and the heat dissipation member (7). In a package for a semiconductor device sealed with, the heat dissipation member (7) and the semiconductor chip are attached to the heat dissipation member (7).
A groove (10) between the die bonding part and the cap / heat dissipation member sealing part so as to surround the die bonding part with (5).
A semiconductor package comprising: 2. A cap (3) is attached to surround a semiconductor chip (5) mounted on a substrate (1) having terminals, and the outer periphery of the cap (3) is sealed to the substrate (1) to form a semiconductor chip (5). ) Through the opening (6) of the cap (3) on the upper part of the
And die-bond it to the back surface of the semiconductor chip (5) with the brazing material (8), and then the brazing material (9) between the opening (6) edge (3i) of the cap (3) and the heat dissipation member (7). In a package for a semiconductor device sealed with, the heat dissipation member (7) and the semiconductor chip are attached to the heat dissipation member (7).
(5) Enclose the die-bonding part with the convex wall (1
1) A semiconductor package characterized by being formed.