JPH05135439A - Signal generating means - Google Patents

Abstract

PURPOSE:To control the period and the phase of a control signal and to stably generate the control signal by generating the control signal without being affected by the change of an external reference signal at the time of special reproducing. CONSTITUTION:When a mode signal is asynchronism, a period set value of being the same period as the period of external period information indicated by a control signal is outputted by a period set value supplying means 27. by a control signal generating means 25, since a period control signal according to the inputted period set value is outputted regardless of the external reference signal, the control signal is not affected by the disturbance of the external reference signal. When the mode signal indicates synchronism, the period set value so as to be the same period as the external reference signal is outputted by the supplying means 27. Further, when the mode signal moves from asynchronism to synchronism, by the supplying means 27, the period set value is changed and the control signal is set to the same period as the external reference signal and a phase difference is made a prescribed value. Thus, the generation control signal period and the phase are synchronized with the external reference signal without disturbing a servo control response.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating means capable of phase synchronization with an input signal, and more particularly to a signal generating means suitable for use in a video information reproducing apparatus.

[0002]

2. Description of the Related Art A video signal reproducing apparatus such as a video. Tape. As a function of the recorder (hereinafter abbreviated as VTR), there is special reproduction in addition to normal reproduction. Special reproduction is a reproduction of a magnetic tape running at a speed different from normal speed, and various special reproductions differ in tape running speed and presence or absence of noise in the reproduced image depending on the purpose. There is a way. FIG. 2 shows a conventional structure of servo means for realizing such a special reproduction function. 80 is a control signal input terminal,
81 is a drum servo circuit, 82 is a capstan servo circuit, 83 and 85 are motors, 84 is a frequency generator of the motor 83 (hereinafter referred to as DFG), and 86 is a frequency generator of the motor 85. (Hereinafter referred to as CFG), 88 is a rotary drum,
87 is a tack signal generator (hereinafter referred to as DPG) for detecting the rotational phase of the rotary drum 88, 89 is a video head,
Reference numeral 90 is a control signal head (hereinafter referred to as CTL head), and 91 is a magnetic tape.

In FIG. 2, a video head 89 is attached to a rotary drum 88 and is rotated together with the rotary drum 88 by a motor 83 to read out image information on a magnetic tape. The CTL head 90 detects a control signal (hereinafter referred to as a CTL signal) recorded in the longitudinal direction of the magnetic tape 91. The drum servo 81 outputs a signal representing the rotation phase of the rotary drum 88 from the DPG 87, a signal representing the rotation speed of the rotary drum 88 from the DFG 84, and a signal serving as a reference of the servo means from the control signal input terminal 80 ( (Hereinafter referred to as a control signal), the speed of the motor 83 is controlled so that the rotation speed of the rotating drum 88 matches the speed of the control signal, and the rotation phase of the rotating drum 88 matches the predetermined phase of the control signal. By controlling the phase of the motor 83, the speed and phase of the rotary drum 88 are controlled by the control signal. Further, the capstan servo 82 receives the CTL signal from the CTL head 90 and the motor 8 from the CFG 86.
5 and the control signal from the control signal input terminal 80 are input to control the speed of the motor 85 so that the rotation speed of the motor 85 matches the speed of the control signal, and then the CTL signal. By controlling the phase of the motor 85 so as to match with the predetermined phase of the control signal, the traveling speed of the magnetic tape is controlled by the control signal.

By performing speed control and phase control of each servo at the time of normal reproduction, the drum servo circuit 81 and the capstan servo circuit 82 send a synchronizing signal of image information obtained from the video head 89 to the control signal. The motors 83 and 85 are controlled so that the video head 89 accurately tracks the track of the video information recorded on the magnetic tape while synchronizing with the control signal from the input terminal 80.
At the time of special reproduction, for the frequency and phase of the control signal different from the normal reproduction input to the control signal input terminal 80,
Depending on whether or not the speed control and the phase control of each servo are performed or not, it is possible to realize various special reproductions different from the normal reproduction such as tape running speed and presence / absence of noise in the reproduced image. Is becoming The speed and phase of each servo are controlled. In the case of a control signal different from normal reproduction, the running speed of the magnetic tape changes according to the cycle of the control signal, and the control from the video head 89 is performed. The same continuous video information as when recorded on the magnetic tape synchronized with the signal is read out accurately.

Here, as the function of the image information reproducing apparatus,
In some cases, it is necessary to reproduce the video information in synchronization with the video signal or the synchronization signal input to the reproduction device. Especially, it is said to be an essential function for business use and broadcasting use. When reproducing at normal speed in synchronization with the input video signal, the signal extracted from the input video signal may be used as the control signal, or a signal synchronized with the input video signal may be created and used as the control signal. .. On the other hand, when performing special playback, a signal that is asynchronous with the input video signal or a signal that is an arbitrary multiple of the frequency is generated from the input video signal.
It may be used as a control signal. In this way, during normal reproduction, a control signal with a frequency synchronized with the input video is output to the servo means, and during special reproduction, a control signal with a frequency different from that during normal reproduction is output to the servo means. The configuration of is shown in FIG.

In FIG. 3, 1 is a video signal input terminal, 2
Is an external reference signal generating means, 3 is a control signal generating means, 4 is a control means, and 5 is a control signal output terminal. The external reference signal generating means 2 extracts a sync signal from the video signal input from the video signal input terminal 1 to generate a color frame signal and outputs it as an external reference signal. The control means 4 outputs the external cycle information indicating the cycle of the control signal corresponding to the traveling speed of the magnetic tape, and the mode signal indicating whether the control signal is synchronized with the external reference signal or not. To do. In the control signal generating means 3, the external reference signal from the external reference signal generating means 2 and the control means 4 are used.
The external cycle information and the mode signal are input, and a control signal having a phase corresponding to the mode signal is output at a cycle corresponding to the external cycle information. When the VTR performs normal reproduction, the control means 4 outputs a mode signal indicating synchronization with the external cycle information having the same cycle as the external reference signal, and the control signal generating means 3 outputs the external reference signal. It outputs a phase-synchronized control signal. If the VTR performs special playback,
The means 4 outputs a mode signal representing asynchronousness with the external cycle information corresponding to the traveling speed of the magnetic tape, and the control signal generating means 3 outputs a control signal asynchronous with the external reference signal.

FIG. 4 is a block diagram showing an example of a conventional device in the control signal generating means 3. 9 is an external reference signal input terminal, 10 and 14 are frequency dividers, 11 is a phase comparator,
Reference numeral 12 is a low-pass filter, 13 is a VCO which is a voltage controlled oscillator, 15 is a frequency division ratio varying means, 16 is a mode signal input terminal, 17 is an external period information input terminal, and 18 is a control signal output terminal. Phase comparator 11, low-pass filter 1
2, VCO 13, and frequency division ratio varying means 15 form a phase synchronization loop circuit (PLL).

In FIG. 4, the frequency division ratio varying means 15 inputs the external cycle information from the external cycle information input terminal 17 and the mode signal from the mode signal input terminal 16 and divides them according to these values. It is a frequency divider with a variable frequency ratio. When the frequency division ratio is changed, the cycle of the control signal output from the control signal output terminal 18 via the phase comparator 11, the low pass filter 12, the VCO 13, and the frequency divider 14 changes. Therefore, the frequency division ratio of the frequency division ratio varying means 15 is controlled in accordance with the external cycle information from the external cycle information input terminal 18 to control the control signal synchronous or asynchronous with the external reference signal from the external reference signal input terminal 9. It is configured so that it can be generated at the signal output terminal 18.

Another conventional method of generating a control signal is shown in US Pat. No. 4,635,138. There, a control signal is generated by the configuration shown in FIG. In FIG. 5, 20 is an external reference signal signal input terminal, 21 is a program counter, 22 is a count value setting means, and 23 is a control signal output terminal. FIG. 6 is a diagram showing the waveform of each part of FIG. FIG. 6A shows an external reference signal from the external reference signal input terminal 20, (B1),
(B2) is a control signal output from the program counter 21.

In FIG. 5, the program counter 21 is
The external reference signal from the external reference signal input terminal 20 is used as a trigger to count up to the preset count value from the count value setting means 22 and output a control signal.
When the count value from the count value setting means 22 is constant, the output of the program counter 21 outputs a control signal which is delayed and synchronized with the external reference signal of FIG. 6A as shown in FIG. 6B1. To do. Also, the count value setting means 2
When the count value from 2 is changed at a predetermined rate,
As shown in FIG. 6 (B2), the output of the program counter 21 is a control signal asynchronous with the external reference signal of FIG. 6 (A). As described above, the conventional control signal generating means can generate an output signal which is synchronous or asynchronous with the input signal.

[0011]

In the conventional example shown in FIG. 4, when the special reproduction is switched to the normal reproduction, that is, the phase and the cycle of the output signal with respect to the input signal of the control signal generating means are not in the asynchronous state. When the output signal is immediately synchronized with the input signal at the time of shifting to the synchronous state, the phase and frequency of the control signal suddenly change, and the mechanical means of the servo means based on the frequency and phase of the control signal. There is a problem that the reproduced image is disturbed because the response of the operation cannot follow.

Further, in the conventional example shown in FIG. 5, when the special reproduction is shifted to the normal reproduction, the count value setting means 22 outputs the control signal so that the cycle of the control signal gradually coincides with the external reference signal. By changing the count value at a predetermined rate, it is possible to prevent the control signal from changing suddenly. Therefore, even if this control signal is supplied to the servo means, the response of the mechanical operation of the servo means follows and the reproduced image is not disturbed. However, since the external reference signal that triggers the program counter 21 is required, if the external reference signal is disturbed or lost, the control signal that is the output is disturbed, and as a result, the reproduced image is disturbed.

An object of the present invention is to generate a control signal that is not affected by changes in the external reference signal during special reproduction, and
It is an object of the present invention to provide a control signal generating means capable of controlling the phase and cycle of a control signal so that a reproduced image is not disturbed when transitioning from special reproduction to normal reproduction.

[0014]

The above-mentioned object is to detect the difference in the phase of the control signal with respect to the phase of the external reference signal and the control signal generating means for outputting the control signal of the cycle corresponding to the cycle set value. A phase comparing means for outputting a signal indicating the difference, and a mode for indicating whether the period and the phase of the signal indicating the phase difference from the phase comparing means and the control signal are synchronized with or asynchronous with the external reference signal. When the signal and period information are input and the mode signal indicates synchronization, the period signal is output so that the phase difference has a predetermined phase and a period equal to that of the external reference signal. When representing asynchronous, it can be realized by configuring with a cycle set value supply means that outputs a cycle set value according to the value of the cycle information.

[0015]

When the period and phase of the control signal shift from the asynchronous state to the synchronized state with respect to the external reference signal, the period set value supplying means gradually sets the period so that the response of the servo means is not disturbed. Change the value. At this time, according to the signal indicating the phase difference from the phase comparison means, when the cycle of the control signal becomes equal to the external reference signal, the phase difference is converged to a constant value so that the cycle set value supply means Determines the cycle setting value to be changed. Therefore, in the signal generator capable of phase synchronization according to the present invention, it is possible to gradually bring the cycle and phase of the control signal with respect to the external reference signal from the asynchronous state to the synchronized state, and from the special reproduction such as VTR to the normal reproduction. When the process shifts to, the reproduced image is not disturbed by the transient response of the servo means. Further, when the control signal is asynchronous with respect to the external reference signal, the external reference signal is not used for generating the control signal, so that the control signal is not affected even if the external reference signal is disturbed or lost.
Furthermore, when the control signal is synchronized with the external reference signal, even if the phase of the external reference signal changes suddenly, the phase of the control signal is gradually synchronized with the external reference signal using the information from the phase comparison means. be able to.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The same parts are designated by the same reference numerals. FIG. 1 is a block diagram showing a basic configuration of a control signal generating means embodying the present invention. 9 is an external reference signal input terminal, 25 is a control signal generating means, 26 is a phase comparing means, 27 is a period set value supply. Reference numeral 16 is a mode signal input terminal, 17 is an external cycle information input terminal, and 18 is a control signal output terminal. In FIG. 1, the control signal generating means 25 generates and outputs a control signal having a cycle corresponding to the input cycle setting value. The control signal is output from the control signal output terminal 18 and is also supplied to the phase comparison means 26. In the phase comparison means 26, the external reference signal input from the external reference signal input terminal 9 and the control signal are input, the phase difference of the control signal with respect to the external reference signal is detected, and the signal representing the phase difference (hereinafter, A phase difference signal) is supplied to the period setting value supply means 27. The cycle set value supply means 27 inputs the phase difference signal from the phase comparison means 26, the mode signal from the mode signal input terminal 16 and the external cycle information from the external cycle information input terminal 17, and outputs the mode. The cycle setting value is output according to the read signal and the external cycle information.

When the mode signal indicates non-synchronization, the cycle setting value supplying means 27 outputs a cycle setting value such that the control signal has a cycle equal to the cycle indicated by the external cycle information. The control signal generation means 25 generates and outputs a control signal having a cycle corresponding to the input cycle setting value, regardless of the external reference signal, so that the control signal is not affected even if the external reference signal is disturbed. ..

When the mode signal indicates synchronization, the cycle set value supply means 27 causes the control signal to have a cycle set value equal to the cycle indicated by the external cycle information, that is, equal to the external reference signal. Is output. Here, when the difference in the cycle or phase of the control signal with respect to the external reference signal is different from a predetermined value, for example, when the mode signal shifts from asynchronous to synchronous, the cycle set value supply means 27 causes the cycle set value supply means 27 to set the cycle set value. In accordance with a predetermined control procedure so that the control signal has the same period as the external reference signal and the phase difference has a predetermined value. If the cycles of the external reference signal and the control signal are significantly different, the change in the phase difference between them becomes large, and especially if the cycles of the both differ by more than two times, the phase difference cannot be clearly defined and is detected. The phase difference cannot be used for control. Therefore, when the control signals having different cycles are synchronized with the external reference signal, the procedure for the cycle setting value supply means 27 to change the cycle setting value is such that the control signal has a cycle sufficiently equal to that of the external reference signal at first. Change the cycle setting value to. Next, the cycle setting value is changed so that the phase difference signal from the phase comparison means 26 has a target value, and when the target phase difference is obtained, a cycle setting value with which the cycle is equal to that of the external reference signal is set. Output. When the control signal according to the present embodiment is used as the reference signal for the servo control of the VTR, the ratio of the cycle set value changed per unit time is limited to a certain fixed value or less so that the servo control response is not disturbed. Good. With the above configuration, the cycle and phase of the control signal generated can be synchronized with the external reference signal without disturbing the response of the servo control.

The cycle set value supply means 27 can be realized by the following operations. It is detected whether the cycle set value output from the cycle set value supply means 27 matches the value of the external cycle information, and if they do not match, the ratio of the cycle set value changed per unit time is set to a certain fixed value. The cycle set value is increased or decreased in the matching direction while limiting to the following. As a result, a control signal having a desired cycle can be obtained regardless of whether the control signal is synchronized with the external reference signal. When the cycle set value matches the value of the external cycle information and the mode signal indicates synchronization, it is detected whether the phase difference signal from the phase comparison means 26 matches the target value, and the values match. If not, the cycle set value is increased or decreased by a minute amount. When the phase difference signal matches the target value, the cycle setting value corresponding to the value of the external cycle information is output again. A flow chart showing the above operation procedure is shown in FIG. Further, FIG. 8 shows an embodiment of the cycle set value supply means 27 for performing the processing according to the flow chart shown in FIG.

In FIG. 8, 120 and 125 are comparison circuits, 121 is an AND circuit, 122 is a counter circuit for outputting a cycle setting value, 123 and 126 are switch circuits, and 124 is a cycle setting value from the counter circuit 122. It is a cycle data conversion means for converting into the same data format as the external cycle information. The comparison circuit 120 compares the external cycle information from the terminal 17 and the cycle set value with the cycle data conversion unit 1.
The value is compared with the value converted by 24 and the result is output. The counter circuit 122 operates to decrease the count value if the comparison result from the comparison circuit 120 is larger than the external period information, increase the count value if the comparison result is smaller, and stop the count if they are equal. Therefore, the output of the counter circuit 122 is controlled so as to have the cycle set value corresponding to the external cycle information. Further, since the count operation is performed by the clock input to the counter circuit 122,
The magnitude of the count value that changes per unit time, that is, the rate of change of the cycle set value can be limited by the frequency of the clock. The comparison circuit 125 compares the phase difference signal from the terminal 31 with the set value, and controls the switch circuit 126. The switch 126 selects the cycle set value N corresponding to the external cycle information at the time of synchronization when the phase difference is equal to the set value, and the phase difference is large when the phase difference is smaller than the set value. If the phase difference is larger than the set value, the cycle set value N + a is selected so that the phase difference becomes smaller. Therefore, when the switch circuit 123 selects the output of the switch circuit 126, the phase of the control signal output from the control signal generating means is controlled to be constant.

Here, the AND circuit 121 takes the logical product of the mode signal from the terminal 16 indicating the synchronization and the output of the comparison circuit 120 being equal, and controls the switch circuit 123. That is, the switch circuit 123 selects the output of the switch circuit 126 only when the mode signal indicates synchronization and the cycle setting value is equal to the value corresponding to the external cycle information. In other cases, the output of the counter circuit 122 is selected. Select. Therefore, when the processing cycle set value does not match the value of the external cycle information, the cycle set value is changed in the direction of matching while limiting the ratio of the cycle set value changed per unit time to a certain value or less. Increase or decrease, and if the cycle setting value matches the value of the external cycle information and the mode signal indicates synchronization, increase the cycle setting value by a small amount so that the phase difference signal matches the target value. Alternatively, the cycle setting value corresponding to the value of the external cycle information is output again when the phase difference signal coincides with the target value by decreasing the phase difference signal. Therefore, the operation according to the flowchart shown in FIG. 7 can be realized.

In the embodiment shown in FIG. 8, the period set value is increased or decreased by a minute amount to match the phase difference signal with the target value. At this time, the phase difference between the external reference signal and the control signal is changed. If is large, it will take time for the phase difference signal to match the target value depending on the increase / decrease amount of the cycle setting value. If the amount of increase / decrease in the cycle set value is made as large as possible, the amount of change in the phase also becomes large and the time to match can be shortened. The cycle of the control signal changes abruptly, which may disturb the servo control response. To solve this problem, find the maximum value of the increase / decrease amount of the cycle set value (hereinafter referred to as target cycle information) from the value of the phase difference detected when the cycles of the reference signal and the control signal match, While limiting the ratio of the cycle set value to be changed per time to a certain value or less, the cycle set value is increased or decreased to the target cycle information, and when the target cycle information is reached, the cycle set value is decreased or increased, and then again. Equal to the value of the external cycle information. The target cycle information has a value such that the phase difference signal matches the target value when the cycle set value becomes equal to the value of the external cycle information. By operating the cycle set value supply means 27 as described above, the cycle and phase of the control signal can be synchronized with the external reference signal in a short time without disturbing the response of the servo control. A flow chart showing the above operation procedure is shown in FIG.

In the flow chart shown in FIG. 9, if the accuracy of the phase difference detecting means is poor, the phase difference detection cycle is long, or the phase difference signal information is old in time, the external cycle information When the value and the value of the period information match, the phase difference signal does not reach the target phase difference. Therefore, if feedback control is performed to change the period setting value while monitoring the phase difference at a certain period,
Accurate and faster phase synchronization is possible than the control procedure shown in FIG. FIG. 10 is a flow chart showing the operation procedure when feedback control is performed.

FIG. 11 is a block diagram showing an embodiment of the cycle set value supply means 27 for performing the process according to the flowchart shown in FIG. 9 or 10. In FIG. 11, 31 is a phase difference signal input terminal, 66 is a phase difference data conversion means, 33 is cycle information determination means, and 114 is cycle data.
16 is a mode signal input terminal, 17 is an external cycle information input terminal, and 35 is a cycle set value output terminal. The phase difference signal input from the phase difference signal input terminal 31 is converted by the phase difference data converting means 66 into target cycle information corresponding to the value of the phase difference signal, and the cycle information determining means 33.
Is supplied to. Further, the mode signal from the control means 4 and the external cycle information are inputted to the cycle information determining means 33 from the mode signal input terminal 16 and the external cycle information input terminal 17. The cycle information determining means 33 outputs the external cycle information from the external cycle information input terminal 17 when the mode signal is asynchronous. When the mode signal is synchronous, the period information which finally becomes the period of the external reference signal is output according to the control procedure shown in FIG. 9 or 10, and the phase difference data converting means 66 outputs the period information. The cycle information is controlled and output so that the target cycle information has a predetermined value. The cycle data conversion means 114 converts the cycle information into a cycle set value required for the control signal generation means 25 to generate a control signal corresponding to the cycle information from the cycle information determination means 33, and outputs the cycle set value. The cycle setting value is output from the terminal 35. FIG. 12 is a block diagram showing a specific example of the period information determining means 33 that performs the process according to the flowchart shown in FIG. In FIG. 12, 17 is an external cycle information input terminal, 4
0 is a target period information input terminal, 16 is a mode signal input terminal, 41 is an OR circuit, 42 is an RS flip-flop, 4
3 is an AND circuit, 45 and 49 are comparison circuits, 46 is a data latch, 47 is a clock input terminal, 48 is a selection circuit, 5
Reference numeral 0 is an addition value setting circuit, 51 is an adder, and 53 is a cycle information output terminal.

The comparison circuit 49 has an external cycle information input terminal 1
External cycle information input from 7 and cycle information output terminal 5
3 is compared with the value of the period information output to the output terminal 3, and the result is output to one input of the selection circuit 48 and the AND circuit 43, and when the comparison result indicates a match, the RS flip-flop 42 is set. The comparison circuit 45 compares the values of the target cycle information input from the target cycle information input terminal 40 and the cycle information output to the cycle information output terminal 53, and outputs the result to the other input of the selection circuit 48. It is output to the AND circuit 43. The AND circuit 43 takes the logical product of the fact that the comparison circuit 45 indicates equality and the fact that the comparison circuit 48 indicates equality, and outputs a signal to the OR circuit 41. In the OR circuit 41, the mode signal input terminal 1
The RS flip-flop 42 is reset by taking the logical sum of the output of the AND circuit 43 and that the mode signal supplied to the OR circuit 41 via 6 is asynchronous. R
The S flip-flop 42 sets the output and holds the state when the set signal is input, and resets the output and holds the state when the reset signal is input. However, when the set signal and the reset signal are simultaneously input, the output retains the previous state. The selection circuit 48 selects the output signal of the comparison circuit 49 when the output of the RS flip-flop 42 is set, and selects the output signal of the comparison circuit 45 when the output of the RS flip-flop 42 is reset. The output of the selection circuit 48 is supplied to the addition value setting circuit 50. The addition value setting circuit 50 outputs 0 when the comparison result of the comparison circuit 45 or the comparison circuit 49, which is the output of the selection circuit 48, indicates that they are equal to each other, and outputs the cycle information output to the cycle information output terminal 53. Is selected, a positive constant value is selected, and when the cycle information is larger, a negative constant value is selected and output to the adder circuit 51. The adder circuit 51 adds the output of the added value setting circuit 50 and the value of the cycle information output to the cycle information output terminal 53, and supplies the result to the data latch 46. Data latch 4
6 is an adder circuit 5 at the timing of the clock from the terminal 47.
The output data of 1 is held and output as cycle information to the cycle information output terminal 53, the adder circuit 51, the comparison circuit 45, and the comparison circuit 49. The amount of change per unit time of the cycle information output to the cycle information output terminal 53 is limited by the value set in the addition value setting circuit 50 and the cycle of the clock from the terminal 47.

Here, consider a case where the mode signal indicates asynchronous and the cycle information does not match the external cycle information. Since the mode signal indicates asynchronous, the OR circuit 41
The flip-flop 42 is reset so that the selection circuit 48 selects the output of the comparison circuit 49. The addition value setting circuit 50 is provided for the comparison circuit 4 input via the selection circuit 48.
A positive or negative constant value is selected according to the comparison result of 9 and is output to the adder circuit 51. The addition circuit 51 repeatedly adds the output of the addition value setting circuit 50 to the cycle information output according to the operation timing of the data latch 46,
Gradually bring the cycle setting value closer to the external cycle setting value. Therefore, when the mode signal indicates asynchronous, the cycle information gradually operates to match the external cycle information.

Next, consider the case where the mode signal shifts from the asynchronous state to the synchronous state.

In the first case, when the cycle information matches the external cycle information and also matches the target cycle information, the comparison circuit 49 sets the RS flip-flop 42 and the comparison circuit 45. Resets the RS flip-flop 42 via the AND circuit 43 and the OR circuit 41. However, the previous state was that the mode signal was asynchronous and RS
Since the flip-flop 42 has been reset, it holds the reset state. Therefore, the selection circuit 48 keeps selecting the output of the comparison circuit 49, and the cycle information continues to maintain a value equal to the external cycle information and the target cycle information.

In the second case, when the cycle information is different from the external cycle information, the RS flip-flop 42 is neither set nor reset, and thus holds the reset state which is the previous output state. Therefore, as in the asynchronous case, the cycle information gradually changes so as to match the external cycle information. When the cycle information matches the external cycle information, the comparison circuit 49 sets the RS flip-flop 42, and as a result, the selection circuit 48 selects the output of the comparison circuit 45. If the cycle information matches the target cycle information, the comparison circuit 45 outputs a signal indicating equality to the addition value setting circuit 50, so that the cycle information continues to maintain a value equal to the external cycle information and the target cycle information. If the cycle information does not match the target cycle information, the comparison circuit 45 outputs a signal indicating that it is different to the addition value setting circuit 50, so that the cycle information gradually changes to a value equal to the target cycle information. Further, since the target cycle information is selected to have a value equal to the external cycle information when the phase difference matches the set value, the cycle information converges to a value equal to the external cycle information. At this time, the comparison circuit 49 causes the RS flip-flop 4 to
2 is released, but it is not reset, so R
The S flip-flop 42 remains set. When the cycle information matches the target cycle information and the external cycle information, the comparison circuit 45 resets the RS flip-flop 42 via the AND circuit 43 and the OR circuit 41, and as a result, the selection circuit 48 selects the output of the comparison circuit 49. To do. As described above, in this embodiment, the control signal can be synchronized with the external reference signal in a short time without abruptly changing the cycle and the phase of the control signal.

In the embodiment shown in FIG. 12, the terminal 47
By making the cycle of the clock from the same as the cycle of the external reference signal, the timing of the cycle information output from the terminal 53 can be matched with the timing of the target cycle information, and more accurate control becomes possible.

In the embodiment shown in FIGS. 8 and 12,
Period setting value supplying means 27 is entirely hardware processing.
However, the processing procedure of the flowcharts shown in FIGS. 7, 9 and 10 may be executed by a microcomputer and software. FIG. 13 shows an embodiment of the control signal generating means including the cycle setting value supplying means 27 configured as described above. In FIG. 13, a microcomputer 115 is a microcomputer to which a program that operates according to the flowchart shown in FIG. 7, FIG. 9 or FIG. 10 is input. Microcomputer 1
15, the phase difference signal from the phase difference comparison means 26, the mode signal from the mode signal input terminal 16 and the external cycle information from the external cycle information input terminal 17 are supplied to FIG. 7, FIG. 9 or FIG. The cycle set value is supplied to the control signal generation means 25 in accordance with the operation procedure of 10. 8, FIG. 12 and FIG.
In the embodiment shown in FIG. 3, the cycle setting value is controlled so that the phase difference signal always matches the target value when the mode signal indicates synchronization. However, when the mode signal shifts from asynchronous to synchronous, Only the phase difference signal may be used to control the cycle setting value.

Here, as an example of application to the control signal generating means of the VTR, the external reference signal to be input is 15
The color frame signal of Hz is 0.1% for the amount of change in the period information per field, 0 degrees for the phase difference of the control signal at the time of synchronization with the external reference signal, and the phase difference data. The target period information output from the conversion means 32 has a value of the period information that changes the value of the period information from an arbitrary phase so that the phase difference becomes 0 degree when the control signal matches the period of the external reference signal. Can be used. Further, these values are not limited to the above values, and the effect of the present invention does not change even if other values are used. FIG. 14 shows an example of the phase comparison means 26 which outputs a phase difference signal. Reference numeral 9 is an external reference signal input terminal, 60 is a control signal input terminal, 61 is a counter, 62 is a back calculation means, 63 is a latch, and 64 is a phase difference signal output terminal. FIG. 15 is a diagram showing the timing of the main signal of FIG. 14, (A) of FIG. 15 is an external reference signal input from the external reference signal input terminal 9, and (B) is input from the control signal input terminal 60. Control signal, (C) is latch 6
3 is the phase difference signal.

In FIG. 14, the control signal input from the control signal input terminal 60 is supplied to the counter 61. Further, an external reference signal from the external reference signal input terminal 9 is supplied to the counter 61. The counter 61 starts counting at the rising edge of the external reference signal (t1 in FIG. 15A), ends counting at the falling edge of the control signal (t2 in FIG. 15B), and outputs the count number. Back calculation means 62
Then, the count number from the counter 61 is inversely calculated, and the phase difference signal (PH2 in FIG. 15B) is output. Latch 6
In 3, the phase difference signal from the back calculation means 62 is held at the rising edge of the external reference signal, and the phase difference signal output terminal 64 outputs the phase difference signal.

FIG. 16 shows an example of the control signal generating means 25 in the embodiment described above. In FIG. 16, the control signal generation means 25 is composed of a program counter, the cycle set value from the cycle set value supply means 27 becomes the count number, and the cycle of the output control signal changes according to the change of the count number. The above embodiment is one example when applied to the control signal generation means of the VTR, but it is also applicable to the signal generation means for other systems, and particularly to a system that requires phase control. It works effectively.

[0035]

According to the present invention, the phase of the control signal generated with respect to the phase of the external reference signal can be controlled, and the speed of response required by the system operating on the basis of the control signal is required. , The period and phase of the control signal can be controlled. Therefore, when the control signal is used for servo control, a stable control signal can be generated without being affected by changes in the external reference signal during special reproduction. Further, there is an effect that the reproduced image is not disturbed when shifting from the special reproduction to the normal reproduction.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional configuration of servo means for realizing a special reproduction function.

FIG. 3 is a block diagram showing an example of a conventional device.

FIG. 4 is a block diagram showing an example of a conventional device of the control signal generating means of FIG.

5 is a block diagram showing an example of a conventional device of the control signal generating means of FIG.

6 is a diagram showing a waveform of each part of FIG.

7 is a flow chart showing an operation procedure of the cycle set value supply means of FIG.

8 is a diagram showing an embodiment of a cycle set value supply means for performing processing in accordance with the flowchart shown in FIG.

9 is a flow chart showing an operation procedure of the cycle set value supply means of FIG.

10 is a flow chart showing an operation procedure of the cycle set value supply means of FIG.

11 is a block diagram showing an embodiment of the cycle set value supply means of FIG. 1. FIG.

12 is a block diagram showing an embodiment of the period information determining means in FIG.

13 is a diagram showing an embodiment of a control signal generating means including a cycle setting value supplying means for performing processing in accordance with the flowcharts shown in FIGS. 7, 9 and 10. FIG.

14 is a block diagram showing an embodiment of the phase comparison means in FIG. 1. FIG.

FIG. 15 is a diagram showing timings of main part signals of FIG. 14;

16 is a diagram showing an embodiment of the control signal generating means of FIG.

[Explanation of symbols]

 25 ... Control signal generating means 26 ... Phase comparing means 27 ... Cycle set value supplying means 18 ... Control signal output terminal 17 ... External cycle information input terminal 16 ... Mode signal input terminal 9 ... External reference signal input terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kotaro Okiguchi Inventor Kotaro Okuguchi 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi Ltd. (72) Koji Fujita 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Video Media Laboratory (72) Inventor Hideo Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Video Media Laboratory

Claims (7)

[Claims] 1. A signal generating means for inputting a cycle setting value and outputting a control signal having a cycle corresponding to the cycle setting value; and a phase of an external reference signal for inputting the control signal and an external reference signal. And a phase comparison means for detecting a phase difference of the control signal and outputting a signal representing the phase difference, and a period and a phase of the signal representing the phase difference and the control signal from the phase comparison means are synchronized with an external reference signal. Mode signal and external period information that determines the period of the control signal are input, and when the mode signal indicates synchronization, the period of the control signal is equal to the external reference signal. And a cycle set value supply means for outputting a cycle set value such that the phase difference becomes a predetermined phase, and for outputting a cycle set value according to the value of the external cycle information when the mode signal indicates asynchronous. Consists of Signal generating means for said. 2. The cycle set value supplying means has a cycle in which the control signal has a cycle equal to the external reference signal and the phase difference has a predetermined phase only when the mode signal shifts from asynchronous to synchronous. 2. The signal generating means according to claim 1, wherein the cycle set value is controlled by a predetermined control procedure. 3. The cycle setting value supply means changes the cycle setting value so that the rate of change of the cycle of the control signal is equal to or less than a predetermined value. Signal generation means. 4. The control signal generating means comprises a program counter whose count is determined by the cycle set value from the cycle set value supply means, and outputs a control signal having a cycle corresponding to the cycle set value. Claims 1 and 2
Alternatively, the signal generating means described in 3. 5. The signal generating means according to claim 4, wherein when the mode signal indicates synchronization, the count number of the program counter is set in synchronization with the external reference signal. 6. The phase comparison means inputs a control signal, an external reference signal, and a clock synchronized with the external reference signal, counts the number of clocks from the rise of the external reference signal to the fall of the control signal, and outputs the clock. A counter for outputting a number, a counter circuit for inputting the number of clocks from the counter, and back-calculating from the number of clocks to output a signal representing the phase difference of the control signal with respect to the fall of the external reference signal, and the counter circuit And a flip-flop that inputs the signal indicating the phase difference and the external reference signal, latches the signal indicating the phase difference at the rising edge of the external reference signal, and outputs the signal indicating the phase difference synchronized with the external reference signal. The signal generating means according to claim 1, 2, 3, 4, or 5, which is configured. 7. The cycle set value supply means comprises a microcomputer and a program.
The signal generating means described in 2, 3, 4, 5 or 6.