JPH0513431A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide the title semiconductor device having the capability for high integration and rapid actuation. CONSTITUTION:A source electrode 6a and a drain electrode 6a are simultaneously formed when a gate electrode 6 is formed and then impurities are led in using these electrodes as masks so that inverse conductivity type P pocket layers 14, 15 may be formed respectively at the bottom parts of the second source diffused layer 17 and the second drain diffused layer 18. At this time, since only less than half bottom parts of the first source diffused layer 7 and the first drain diffused layer 8 are respectively covered with the P pocket diffused layers 14, 15, the junction capacity can be restricted to the value not exceeding half of the conventional junction capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, with higher integration and higher speed of semiconductor devices, MOS transistors, which are the main constituent elements, have been miniaturized, and the gate length has reached 0.5 μm. In such a transistor having a short gate length, the increase of the short channel effect becomes a big problem. A commonly used method for suppressing the short channel effect is to increase the impurity concentration of the semiconductor substrate. However, increasing the impurity concentration causes an increase in the substrate bias effect, and as a result, the speed of the semiconductor device becomes slow. Therefore, various solutions have been proposed for suppressing the short channel effect without increasing the substrate concentration.

A conventional method of manufacturing a semiconductor device will be described below with reference to the drawings. 4A to 4D are process cross-sectional views showing the manufacturing process of a conventional N-channel MOS transistor. First, as shown in FIG. 4A, a P-type silicon substrate 1
After forming the element isolation region 2 on the above, a gate oxide film 3 having a thickness of 10 nm is formed. Next, as shown in FIG. 4B, a polycrystalline silicon film 6 is formed on the gate oxide film 3 by 250.
nm, and further an oxide film 9 is deposited to 150 nm. Then, using the photoresist as a mask, dry etching is used to form a gate electrode (formed of the polycrystalline silicon film 6, which will be indicated by 6 below). Next, phosphorus (P) ions were added at a dose of 2.0 × 10 ¹³ cm ^-2 and an acceleration energy of 4
Lightly doped drain (Ligh
tly Doped Drein and hereinafter referred to as LDD diffusion layer) 12,
13 is formed. Next, as shown in FIG. 4C, after depositing an oxide film with a thickness of 150 nm, the sidewall 16 is formed by using the etch back method. Next, using the gate electrode 6 and the oxide film 9 as a mask, the dose amount is 4 × 10 ¹⁵ cm ⁻² and the acceleration energy is 40.
Arsenic (As) ions are implanted by KeV to form the source diffusion layer 1
7, the drain diffusion layer 18 is formed. Further, boron (B) ions are implanted at a dose amount of 2 × 10 ¹³ cm ^-2 and an acceleration energy of 180 KeV to form P pocket diffusion layers 14a, 1
5a is formed. Next, as shown in FIG. 4D, an interlayer insulating film layer 19 is deposited, contact holes are formed, and then the electrode 2 is formed.
Form 0.

N-channel MOS configured as described above
In the transistor, the P pocket diffusion layers 14a and 15 having a high concentration are formed around the source diffusion layer 17 and the drain diffusion layer 18.
Since a is present, the extension of the depletion layer from the source diffusion layer 17 and the drain diffusion layer 18 can be suppressed. Therefore, the short channel effect can be suppressed without increasing the substrate concentration.

[0005]

However, in the above conventional structure, since the high-concentration reverse conductivity type diffusion layer (P pocket diffusion layer) is present on the entire bottom surface of the source diffusion layer and the drain diffusion layer, the junction capacitance is increased. Grows larger. Therefore, there is a problem that the speed of the transistor becomes slow.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device in which the increase in capacitance due to the P pocket diffusion layer is small and a manufacturing method thereof.

[0007]

In order to achieve this object, the semiconductor device of the present invention is localized at the junction depth of the source diffusion layer and the drain diffusion layer and only in the vicinity of just below the end of the gate. The source diffusion layer and the drain diffusion layer are provided with a diffusion region (P pocket diffusion layer) having a conductivity type opposite to that of the source diffusion layer and the drain diffusion layer.

According to the method of manufacturing a semiconductor device of the present invention, the source electrode and the drain electrode are formed at the same time when the gate electrode is formed, and the source electrode and the drain electrode are formed at the place sandwiched between the gate electrode and the source electrode or between the gate electrode and the drain electrode. Grooves are formed respectively, and by implanting ions through these grooves,
It has a structure in which a P pocket diffusion layer is locally formed.

[0009]

With this structure, the junction capacitance of the source diffusion layer and the drain diffusion layer can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention, showing an example of an N-channel MOS transistor. In FIG. 1, 1 is P
Type silicon substrate, 2 is an element isolation region, 3 is a gate oxide film, 4 and 5 are contact holes, 6 is a gate electrode, 6a is a source or drain electrode, 7 is an N-type first source diffusion layer, and 8 is N-type first drain diffusion layer, 9 is an oxide film, 10 and 11 are trenches, 12 and 13 are N-type LDD diffusion layers, 14 and 15 are P-type P pocket diffusion layers, 16 is a side wall, and 17 is An N-type second source diffusion layer, 18 is an N-type second drain diffusion layer, 19 is an interlayer insulating film, and 20 is an electrode.

As described above, in this embodiment, the P pocket diffusion layers 14 and 15 are formed at the junction depths of the second source diffusion layer 17 and the second drain diffusion layer 18, respectively. Since 14 and 15 are localized only in the vicinity immediately below the end of the gate, the junction capacitance of the source diffusion layer and the drain diffusion layer can be reduced. Although the P pocket diffusion layers 14 and 15 depend on the mask alignment accuracy in the process of forming the trenches 10 and 11, the P pocket diffusion layers 14 and 15 are not in contact with the LDD diffusion layers 12 and 13, and the second source diffusion layer 17 and the second drain diffusion layer 18 are provided. It is desirable to be formed in the corner portion of.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention, showing an N-channel MOS transistor as an example. First, as shown in FIG. 2A, after forming an element isolation region 2 on a P-type silicon substrate 1, a gate oxide film 3 having a thickness of 10 nm is formed by dry oxidation or pyrooxidation. Next, as shown in FIG. 2B, after the gate oxide film 3 is etched to form the contact holes 4 and 5, the polycrystalline silicon film 6 is formed by using a well-known vapor phase growth method.
Is deposited to a thickness of 250 nm. Next, a phosphorus (P) diffusion process is performed on the polycrystalline silicon film 6 at 900 ° C. for 30 minutes to form a first source diffusion layer 7 and a first drain diffusion layer 8.
The diffusion of phosphorus (P) is performed by a diffusion using a liquid source (POCl ₃ ) or an ion implantation method. Next, as shown in FIG. 2C, an oxide film 9 is deposited to a thickness of 150 nm on the polycrystalline silicon film 6 by using a well-known vapor phase growth method. Next, using the photoresist as a mask, the gate electrode 6 and the source diffusion layer 7
And the polycrystalline silicon film 6 other than a part of the drain diffusion layer 8,
The oxide film 9 is etched to form trenches 10 and 11 at the end of the gate.
To form. The remaining polycrystalline silicon film 6 forms the gate electrode 6, the source electrode 6a and the drain electrode 6a.
Next, the gate electrode 6, the source electrode 6a, and the drain electrode 6
Using a as a mask, the acceleration energy in the grooves 10 and 11 is 30K.
The LDD diffusion layers 12 and 13 are formed by implanting phosphorus (P) ions under the conditions of eV and a dose amount of 3.0 × 10 ¹³ cm ^-2 . Next, using the gate electrode 6, the source electrode 6a and the drain electrode 6a as a mask, boron (B) ions are implanted under the conditions of an acceleration energy of 80 KeV and a dose amount of 2.0 × 10 ¹² cm ⁻² to form the P pocket diffusion layers 14 and 15. Form.
The oxide film 9 is formed in order to prevent boron from penetrating under the gate when boron (B) is ion-implanted with high acceleration energy. Next, FIG. 2 (d)
As shown in FIG. 3, an oxide film is deposited to a thickness of 150 nm and then etched by using an etch back method to form 1 on the side surfaces of the grooves 10 and 11.
The side wall 16 having a width of 30 nm is formed. Next, arsenic (As) ions are implanted under the conditions of an acceleration energy of 40 KeV and a dose amount of 4.0 × 10 ¹⁵ cm ⁻² to form the second source diffusion layer 1
7, the second drain diffusion layer 18 is formed. Figure 2 (d)
After the step (1), an oxide film is deposited, a contact hole is opened at a prescribed position, and an electrode 20 is formed, which is the semiconductor device of the embodiment shown in FIG.

As described above, in this embodiment, the source electrode 6a and the drain electrode 6a are formed at the same time when the gate electrode 6 is formed. At the same time, the groove 10 sandwiched between the gate electrode 6 and the source electrode 6a is formed. Then, the groove 11 sandwiched between the gate electrode 6 and the drain electrode 6a is formed. By implanting ions through these grooves 10 and 11, the P pocket diffusion layers 14 and 15 can be easily formed locally.

N-channel MOS configured as described above
The transistor will be described in comparison with the conventional example with reference to FIGS. 1, 3 and 4D. Note that FIG. 3 is a comparison diagram of the impurity distribution in the depth direction of the source and drain diffusion layers in one example of the present invention and the conventional example.

First, in the conventional example, as shown in FIG.
The P pocket diffusion layers 14a and 15a are the source diffusion layers 17 and
It is formed so as to cover the bottom surface of the drain diffusion layer 18.
Therefore, as shown by the dotted line in FIG. 3, the source diffusion layer 17,
At each junction of the drain diffusion layers 18, the N-type diffusion layer having an impurity concentration of about 10 ²⁰ and the P-type diffusion layer having an impurity concentration of about 10 ¹⁷ are in contact with each other, and the junction capacitance is about 1.
It becomes 7 fF.

On the other hand, in the embodiment of the present invention shown in FIG. 1, the second source diffusion layer 17 and the second drain diffusion layer 1 are provided.
The P pocket diffusion layers 14 and 15 are formed only on the bottom surface of No. 8. Therefore, as shown by the solid line in FIG. 3, the impurity concentration is about 10 ²⁰ at each junction of the first source diffusion layer 7 and the first drain diffusion layer 8 where the P pocket diffusion layers 14 and 15 are not formed. The N-type diffusion layer and the P-type diffusion layer of about 10 ¹⁶ are in contact with each other, and the junction capacitance is about 0.5 f.
Become F. In this way, the region where the P pocket diffusion layers 14 and 15 do not cover the source diffusion layer and the drain diffusion layer can be half or less of the total source diffusion layer and the drain diffusion layer. It is possible to reduce the junction capacitance to less than half compared with.

In this embodiment, the P pocket diffusion layer 1 is used.
Although the example in which 4 and 15 are in contact with the second source diffusion layer 17 and the second drain diffusion layer 18 has been described, a structure having a gap between them is also conceivable. In this case, although the effect as the P pocket diffusion layer is reduced, the breakdown voltage is improved. Although the example of the N-channel MOS transistor has been described in the present embodiment, the same effect can be obtained also in the P-channel MOS transistor if the conductivity type of the semiconductor substrate and each diffusion layer is reversed from that of the present embodiment.

[0018]

As described above, according to the present invention, the junction depth of the source diffusion layer and the drain diffusion layer of the other conductivity type formed on the semiconductor substrate of the one conductivity type, and only in the vicinity immediately below the end portion of the gate. By providing the localized one-conductivity-type diffusion layer, it is possible to realize a semiconductor device capable of high-speed operation in which the junction capacitance between the source diffusion layer and the drain diffusion layer is reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a comparison diagram of the impurity distribution in the depth direction of the source and drain diffusion layers in one example of the present invention and the conventional example.

FIG. 4 is a process sectional view showing a manufacturing process of a conventional N-channel MOS transistor.

[Explanation of symbols]

1 P-type silicon substrate (semiconductor substrate) 6 Gate electrode (gate) 14, 15 P pocket diffusion layer (diffusion layer) 17 Second Source Diffusion Layer (Source Diffusion Layer) 18 Second drain diffusion layer (drain diffusion layer)

Claims (2)

[Claims] 1. The junction depth of a source diffusion layer and a drain diffusion layer of another conductivity type formed on a semiconductor substrate of one conductivity type,
A semiconductor device having a diffusion layer of one conductivity type, which is localized only near the edge of the gate. 2. A step of forming a source diffusion layer and a drain diffusion layer after forming an element isolation region and a gate oxide film on a semiconductor substrate of one conductivity type, and between the source diffusion layer and the gate electrode and between the drain diffusion layer. Forming a gate electrode, a source electrode and a drain electrode by forming a groove between the gate electrodes, and ion-implanting through the groove, while contacting the bottom of the conductive type source diffusion layer and drain diffusion layer, and the end of the gate And a step of forming a diffusion layer of one conductivity type that is localized only in the vicinity of a portion directly below the semiconductor device.