JPH05134059A - Time correcting method - Google Patents

Abstract

PURPOSE:To realize time correction so as not to generate abnormality in specified-time starting with regard to the time correcting method in a time generating system, which generates the using time in an information processing system. CONSTITUTION:A time generating means 100 for generating a counter time TC and a time correcting means 200 for periodically correcting the counter time to a clock time TH generated with a clock device 1 are provided in a time generating system. In this system, the time difference between the counter time and the clock time is set within a unit time (the unit time is set so that the counter time does not exceed a specified time when the counter time is delayed) in the time correcting means. A dividing and correcting means 300, which divides the operation into a plurality of sections and corrects the time, is provided (the correcting time point is set so that counter time does not generate the specified time again when the counter time gains).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time correction method in a time generation system for generating a time used in an information processing system.

[0002] For example, an electronic exchange or the like has a built-in time generation system that generates a time required for calculating a call charge or collecting various statistical data.

The electronic exchange performs required processing at a predetermined time (for example, every 0 seconds for each minute) or at a predetermined time interval (for example, for every 1 second) with reference to the time generated by the time generation system. There are not a few cases to execute.

In order to maintain the error of the time generated by the time generation system within the allowable range, the time is corrected periodically based on a more reliable time, for example, the time generated by an external clock device. Often.

[0005]

2. Description of the Related Art FIG. 6 is a diagram showing an example of a conventional time generation system, FIG. 7 is a diagram showing an example of a time correction process in FIG. 6, and FIG. 8 is an example of a time delay correction process in FIG. FIG. 9 is a diagram showing an example, and FIG. 9 is a diagram showing an example of the time advance correction history in FIG. 6.

In FIG. 6, the clock oscillator 2 has a clock signal CLK having a constant period (for example, 10 milliseconds).
Is generated and supplied to the time counter 3,
Is a clock signal CL supplied from the clock oscillator 2.
K is counted, and the count value expressed in hours, minutes, seconds, and milliseconds (10 millisecond units) is output as the counter time T _C.

The time management unit 4 activates the periodic activation processing unit 5 at predetermined time intervals or the regular activation processing unit 6 at predetermined time intervals with reference to the counter time T _C output from the time counter 3. To do.

The counter time T _C generated by the time counter 3 is caused by, for example, an error included in the cycle of the clock signal CLK, or the load of the processor constituting the time generation system is congested, and the clock signal at the time counter 3 is clocked. It is unavoidable that an error occurs due to the fact that the counting process of CLK must be stopped.

A time correction unit 41 is provided to correct an error occurring at the counter time T _C. Time correction unit 4
1 is guaranteed to have a smaller error than the counter time T _C generated by the time counter 3 when it is activated every predetermined period (for example, one minute period) (see FIG. 7).
A clock time T _H but generated, compared with the counter time T _C that is time counter 3 occurs (step S1), the time difference between the counter time T _C and clock time T _H | T _C -T _H |
However, when the difference becomes equal to or more than the predetermined allowable time difference Δ (for example, 2 seconds) (step S2), the counter time T _C of the time counter 3 is made to match the clock time T _H (step S2).
3).

However, it is assumed that the time management unit 4 activates the scheduled activation processing unit 6 at a predetermined time (for example, every minute 0 seconds), and the time correction unit 41 is activated at the time t ₁ and the counter time. As a result of comparing T _C with the clock time T _H , as shown in FIG. 8, the counter time T _C shows 10: 6: 59.0 seconds and the clock time T _H shows 10: 7: 01.5 seconds. when was the time difference _{| T C -T H | (=} 2.5 seconds) for exceeding the difference allowed time delta (= 2 seconds), the counter time T
_C (= 10: 06: 59.0 seconds) is set to clock time T _H (= 10
Assuming that the correction is made so as to match the time 7: 01.5 seconds), the time management unit 4 determines that the counter time T _C is 10: 6: 5.
Jumped from 9.0 seconds to 10:07, 10:07
Since the time has shifted to 1.5 seconds, the scheduled activation processing unit 6 cannot be activated at 10: 7: 0.

Further, it is assumed that the time management unit 4 activates the fixed-time activation processing unit 6 at the above-mentioned predetermined time (for example, every minute 0 seconds), and the time correction unit 41 is activated at time t ₁ and the counter time T. As a result of comparing _C with the clock time T _H , as shown in FIG. 9, the counter time T _C shows 10: 07: 1.0 and the clock time T _H shows 10: 6: 58.5. If the the time difference _{| T C -T H | (=} 2.5 sec) is also for exceeding difference allowable time Δ the (= 2 seconds), the counter time T
_{If C} (= 10: 07: 1.0) is corrected to match the clock time T _H (= 10: 6: 58.5),
The counter time T _C output by the time counter 3 is the time t ₁
10: 7: 1.0 is shown twice before and after (time points t ₀ and t ₂ ), and the time management unit 4 starts the scheduled activation processing unit 6 twice at 10: 7: 0. Become.

[0012]

[Problems to be Solved by the Invention]
In the conventional time generation system,
The time correction unit 41 is set to the counter time T_CAnd clock time T
_HTime difference with | T_C-T _H｜ exceeds the allowable time difference Δ
If identified, the counter time T immediately_CClock time T
_HSince it was corrected so that it coincides with
Cannot start because the time to start the startup processing unit 6 was skipped
Or the same time because the time to start is indicated twice
It will be activated twice for each time, and the scheduled activation processing unit
There was a problem that 6 could not be started correctly.

It is an object of the present invention to realize a time correction method that does not cause an abnormality in scheduled activation even when the counter time indicated by the time generation means is corrected.

[0014]

FIG. 1 is a diagram showing the principle of the present invention. In Figure 1, 100, time generating means for generating a counter time T _C counts the clock signal having a predetermined period, 1 clock unit for generating a clock time T _H as a reference of the counter time T _C, 200 is the counter time T _C that time generating means 100 generates a time correcting means for periodically correcting the clock time T _H of timepiece apparatus 1 is generated.

Reference numeral 300 denotes a time correction means 20 according to the present invention.
It is a division correction means provided at 0.

[0016]

The dividing correction means 300 determines the time difference between the counter time T _C generated by the time generation means 100 and the clock time T _H generated by the timepiece device 1 as a predetermined unit time T _U.
Divide within and correct multiple times.

It should be noted that the division correction means 300 has a unit time T _U.
When the counter time T _C generated by the time generation means 100 is behind the clock time T _H generated by the timepiece device 1, correction is performed so that discontinuity does not occur in the effective minimum digit of the counter time T _C. Setting is considered.

When the counter time T _C generated by the time generation means 100 is ahead of the clock time T _H generated by the timepiece device 1, the division correction means 300 corrects the correction time of the counter time T _C by correction. It is considered to set the predetermined time so as not to occur again.

Therefore, when the counter time is corrected, the predetermined time is surely generated only once, and it is possible to prevent the processing started at the constant time from being disturbed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a time generation system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the time division correction processing in FIG. 2, and FIG. 4 is an example of a time delay correction process in FIG. FIG. 5 is a diagram showing an example of the time advance correction history in FIG. 3. The same reference numerals denote the same objects throughout the drawings.

2, a clock oscillator 2, a time counter 3, and a time management unit 4 are shown as the time generation means 100 in FIG. 1, and the time correction means 2 in FIG.
A time correction unit 41 is shown as 00, and a time division correction unit 42 including a delay correction unit 421 and a preceding correction unit 422 is further provided as the division correction unit 300 in FIG.

In the time generation system illustrated in FIG. 2, as in the case of FIG. 6, the clock oscillator 2 generates the clock signal CLK having a constant cycle (for example, 10 milliseconds) and supplies it to the time counter 3, The counter 3 counts the clock signal CLK supplied from the clock oscillator 2,
The count value expressed in hours, minutes, seconds, and milliseconds (10 millisecond unit) is output as the counter time T _C , and the time management unit 4
However, with the counter time T _C output from the time counter 3 as a reference, the scheduled start-up processing unit 6 is started every predetermined time (for example, every 0 seconds for each minute).

However, the time management unit 4 employs seconds as the least significant digit of the counter time T _C generated by the time counter 3 when activating the scheduled activation processing unit 6, and rounds down milliseconds. ..

Therefore, the time division correction unit 42 sets the minimum effective digit (1) as the unit time T _U for correcting the counter time T _C.
500 ms is used so that discontinuity does not occur.

2 to 5, the time correction unit 41
Is started at every predetermined cycle (for example, 1 minute cycle) (see FIG. 3), the counter time T _C generated by the time counter 3 is generated.
If, by comparing the clock time T _H of timepiece apparatus 1 as a reference is generated (step S11), and the time difference between the counter time T _C and clock time T _H | acceptable, predetermined | T _C -T _H If the time difference Δ (for example, 2 seconds) or more (step S12), it is further analyzed whether the counter time T _C is delayed from the clock time T _H (step S13), and the counter time T _C is the clock time. If it is delayed from T _H , the delay correction unit 421 is activated, and if the counter time T _C is earlier than the clock time T _H , the advance correction unit 422 is activated.
To start.

For example, in FIG. 2, FIG. 3 and FIG. 4, the time correction unit 41 is activated at time t ₁ , and the counter time T _C
Indicating a place of comparing the clock time T _H, the time counter 3 shows the 6 minutes 59.0 seconds at the counter time T _C = 10, timepiece apparatus 1 is a 7-minute 1.5 seconds at clock time T _H = 10 Upon detecting that, two counter time T _C is from the clock time T _H.
The delay correction unit 421 is activated after identifying the delay of 5 seconds.

The activated delay correction unit 421 activates a built-in timer (step S21), and when the timer measures a predetermined timing time T ₁ (500 milliseconds in FIG. 4) (step S22), The timer is stopped (step S23), and the unit time T is further added at the counter time T _C (= 10: 6: 59.5 seconds) indicated by the time counter 3.
_U (= 500 milliseconds) is added and counter time T _C (=
It is corrected to 10: 7: 0) (step S24), and the corrected counter time T _C (= 10: 7: 0) is set to the timepiece device 1.
When it is identified that the clock time _TH (= 10: 07: 2.0) indicated by is not reached (step S25), step S21 and subsequent steps are repeated again.

Similarly, the delay correction unit 421 corrects the unit time T _U (= 500 milliseconds) every time 1.0 seconds, 1.5 seconds, and 2.0 seconds elapse from the time point t _1. , Counter time T _C at 10: 07: 1.0, 10: 07: 2.0,
The counter time T _C is corrected to 10: 07: 3.0, and the unit time T _U (= 500 milliseconds) is corrected when 2.5 seconds have passed from the time t _1, so that the counter time T _C is 10: 07: 4. When it is identified that the time becomes 0.0 seconds and the clock time T _H (= 10: 07: 4.0 seconds) or more, the counter time T _C is corrected so as to match the clock time T _H at the same point (step S41), the correction is completed.

In the above-mentioned correction process, the time management unit 4 sets the effective digit of the counter time T _C of the time counter 3 to the time point (t).
_Since it is read as 10: 7: 0 in ( ₁ +0.5 seconds) to (t ₁ +1.0 seconds), it is possible to reliably start the scheduled activation processing unit 6 at 10:07.

2, 3 and 5, the time correction unit 41 is activated at time t ₁ and the counter time T _C is compared with the clock time T _{H. As} a result, the time counter 3 shows the counter time T _C. = 10:00 indicates 6 minutes 56.8 seconds, the timepiece apparatus 1 detects that shows the 6 minutes 54.0 seconds at clock time T _H = 10, 2 counter time T _C is from the clock time T _H.
The leading correction unit 422 is activated after it is identified that the leading time is 8 seconds.

The pre-correction unit 422 which has been activated is
₁Counter time T_CIs the predetermined time T _A(Eg 5 per minute
8.2 seconds) to T_BWithin the range (for example, 59.3 seconds per minute)
Is analyzed (step S31), and the present time t₁
Counter time T_CShows 10: 6: 56.8 seconds,
Built-in as soon as it is confirmed that it is not within the range
To activate the timer (step S32)
Specified timing time T₂(1.5 in FIG. 5)
When the second is measured (step S33), the timer is stopped.
(Step S34), the counter indicated by the time counter 3
Time T_C(= 10: 06: 58.3 seconds) to unit time T_U
(= 500 milliseconds) is subtracted and the counter time T_C(= 1
0: 6: 57.8) (step S35)
Corrected counter time T_C(= 10: 06: 57.8)
Clock time T generated by the clock device 1_H(= 10:06 5
If it is identified that it is preceded by 5.5 seconds (step
(Step S36), and step S31 and subsequent steps are repeated again.

Then, as a result of repeating steps S31 to S36 once, after 3.0 seconds have elapsed from the time point t ₁ , the unit time T
As a result of correcting only _U (= 500 milliseconds), the counter time T _C is corrected to 10: 6: 58.8 seconds, and then the preceding correction unit 422 again sets the current counter time T _C to the predetermined time T in step S31. analyzing whether there within the _a (e.g. every minute 58.2 seconds) to T _B (e.g. every minute 59.3 seconds), this identifies that exist within the range.

Here, the counter time T _C is 10: 6: 5.
When step S32 and the subsequent steps are executed in the state of showing 8.5 seconds, the counter time T _C is 10: 7 at the time when the timer is stopped.
After the number of seconds has been reached, the unit time T _{U is} subtracted and corrected to 10: 06: 59.5 seconds, and after 500 milliseconds have elapsed, 10 is again set.
The time reaches 7: 0, the counter time T _C indicates twice 10: 7: 0, and the time management unit 4 causes the scheduled start processing unit 6 to operate at the same time 10: 7: 0. It will be activated twice.

Further, the counter time T _C is 10: 06: 5.
When step S32 and subsequent steps are executed in a state of indicating 9.0 seconds, the counter time T _C is 10:07 after 1.0 second has elapsed.
Sec reached, after reaching the 10 o'clock 7 minutes 0.5 seconds further timer stop time will be corrected again at 10 7 minutes 0 seconds is subtracted by the unit time T _U, the counter time T _C are two The time management unit 4 also indicates 10: 07: 0.
Will activate the scheduled activation processing unit 6 twice at the same time of 10: 7: 0.

Therefore, the advance correction unit 422 executes the corrections of the steps S32 to S35 on the time counter 3 to set 10: 7: 0 as a range in which it does not occur twice at a predetermined time T _A (= 58.2 per minute). sec.) to T _B (= per minute 59.
3 seconds) is provided, and while the counter time T _C is within the above range, the correction after step S32 is not immediately started, and the step waits until the counter time T _C exceeds the predetermined time T _B. The correction after S32 is started.

Therefore, in FIG. 5, the time point (t₁+3.
Counter time T at 0 seconds)_CIs 10: 6 58.8
Is corrected to seconds and identifies that it is within the range
Then, immediately after step S32 is not executed, and further 500
Milliseconds have elapsed, counter time T _CAt 10:06 59.3
Time point (t₁+3.5) or later (step S3
1), execution of step S32 and subsequent steps is started.

As a result, the counter time T _C becomes the time point (t ₁
+4.2 seconds), 10: 7: 0 seconds are reached, and at time point (t ₁ +5.0 seconds), 10: 7 minutes 0.8 seconds are reached, after which the unit time T _U (= 500 milliseconds) is subtracted. Been 10
It is corrected to 7 minutes and 0.3 seconds, during which time counter 3
Reliably generates the counter time T _C = 10: 7: 0 only once.

Similarly, the preceding correction unit 422 determines the time point.
t₁Unit time T every 6.5 seconds or 8.0 seconds
_U(= 500 ms) Address correction, counter time T_CTo
Corrected to 10: 07: 1.3, 10: 07: 2.3,
Point t₁Unit time T when 9.5 seconds have passed_U(= 5
Counter time T _C
Becomes 10: 07: 3.3 and clock time T_H(= 10:00
7 minutes 3.5 seconds) or less
Time T_CClock time T_HAfter correction to match
Step S41), the correction is completed.

As is apparent from the above description, according to the present embodiment, when the counter time T _C is delayed from the clock time T _H by the allowable time difference Δ or more, the delay correction unit 421 is activated to set the time difference | Since T _C -T _H | is corrected to the unit time T _U (= 500 milliseconds) at intervals of 500 milliseconds, it is displayed once without skipping the predetermined time (10: 7: 0). Further, when the counter time T _C precedes the clock time T _H by the allowable time difference Δ or more, by starting the advance correction unit 422, the time difference | T _C −T _H |
By correcting the unit time T _U (= 500 msec) at 1500 msec intervals and suspending the measurement of the correction interval while the counter time T _C is within the predetermined time T _{A to} T _B range. Therefore, the predetermined time (10: 7: 0) does not occur twice, and it surely occurs once.

2 to 5 are merely examples of the present invention until now. For example, the values of the counter time T _C and the clock time T _H , the start time of the scheduled start-up processing unit 6, and the counter time T _C are shown. The minimum significant digit and the like are not limited to those illustrated, and therefore the timing time T _{1 of the} delay correction unit 421 is
Also, the timing time T ₂ of the advance correction unit 422 and the correction unit time T _U are not limited to the exemplified ones, and many other modifications can be considered. The effect does not change. Furthermore, it goes without saying that the time generation system which is the subject of the present invention is not limited to the one shown in the figure.

[0041]

As described above, according to the present invention, in the time generation system, when the counter time is corrected, the predetermined time is surely generated only once, and the process started at the fixed time is performed. It becomes possible to prevent trouble.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a time generation system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of time division correction processing in FIG.

FIG. 4 is a diagram showing an example of a time delay correction process in FIG.

FIG. 5 is a diagram showing an example of a time advance correction history in FIG.

FIG. 6 is a diagram showing an example of a conventional time generation system.

7 is a diagram showing an example of time correction processing in FIG.

FIG. 8 is a diagram showing an example of a time delay correction process in FIG.

9 is a diagram showing an example of a time advance correction history in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 clock device 2 clock oscillator 3 time counter 4 time management unit 5 cycle activation processing unit 6 timed activation processing unit 41 time correction unit 42 time division correction unit 100 time generation unit 200 time correction unit 300 division correction unit 421 delay correction unit 422 precedent Correction unit

Claims (3)

[Claims] 1. Counting a clock signal having a predetermined period
Counter time (T _C) Generating means (10)
0) and a counter generated by the time generation means (100).
Time (T_C) Is the clock time generated by the clock device (1)
(T_H) And a time correction means (200) for periodically correcting
In the time generation system comprising: the time correction means (200), the time generation means (1
00) occurs at the counter time (T_C) And the watch
Clock time (T)_H) With the
Therefore, it is divided within the specified unit time and divided into multiple times for supplementation.
A corrective division correction means (300) is provided.
Time correction method. Wherein said dividing correcting means (300), said unit time, said time generating means (100) is generated counter time (T _C) of said timepiece device (1) is generated clock time (T _H 2. The time correction method according to claim 1, wherein the effective minimum digit of the counter time (T _C ) is set to such an extent that discontinuity does not occur due to the correction when the time is later than that. 3. The counter correction time (T _C ) generated by the time generation means (100) in the division correction means (300).
If There had advances from the clock device (1) is generated clock time (T _H), the correction time of the counter time (T _C), set to so as not to generate a predetermined time again by the correction The time correction method according to claim 1, wherein: