JPS61237510A - Pulse signal generator - Google Patents

Abstract

PURPOSE:To improve the reliability by accumulating a quantized error caused at each pulse generation and correcting a pulse repetitive interval (PRI) data every time when the accumulated result reaches a correctable data so as to correct the pulse repetitive interval (PRI) data thereby eliminating the need for a pulse counter realizing a long period. CONSTITUTION:When the initial set is finished, a mircocontroller 1 starts the count of a pulse generating circuit 3, a PRI data is extracted from a memory, the data are added and when the added value is in carry-up, the data subject to carry-up are added as the PRI data, loaded as a comparison data. When no carry-up takes place, the PRI data is loaded to the pulse generating circuit 3 as the comparison data. The microcontroller 1 detects periodically whether or not a coincidence detection signal 5 is generated, and when the coincidence detection signal 5 is generated, it is reset to reset the counter of the pulse generating circuit 3, and the processing extracting PRI data from the memory and adding it is executed again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generator that generates pulses.

[Conventional technology]

FIG. 6 is a diagram showing a conventional pulse generator.

In the figure, (l) is a microcontroller that controls according to the program, (a program memory that stores the second control procedure, and (3) counts at the minimum clock, counts value and pulse repetition interval (PRl) data. (4) A pulse generation circuit that generates a pulse train when the
is an address/data bus that interfaces with the fibrocontroller, (6) is a pulse train, (7) is a long-period pulse generation circuit that counts at the minimum clock and generates a synchronization pulse when the long-period PRl value is reached, (8) is synchronized
Figure 7 shows the data format given to the pulse generation circuit (3) and the long period pulse generation circuit (7).
FIG. 8 shows a pulse train (6) generated from the bus generator.

Next, the operation will be explained. Microcontroller (
υ is controlled by a pre-stored program.
Ru. Data is exchanged using an address data bus (4).

microcontroller (υ is a long-period pulse generation circuit (7
) is loaded with long-period PRI data. The long-period pulse generation circuit (7) counts with the minimum clock and generates a long-period P
When the Rl value is reached, a synchronizing pulse (8) is generated, and the long-period pulse generation circuit is driven again to create a long-period synchronizing pulse with a period T.

The microcontroller tlJ loads the PRl data into the pulse generator circuit (3). Pulse generation circuit (3)
counts the fi clock, compares the count value and the PRI data value, and if they match, generates a pulse train (6).

The long period synchronization pulse (8) resets the counter of the pulse generation circuit (3) and minimizes the accumulation of quantization errors in the pulse train (6).

The timing diagram of FIG. 8 shows that the quantization error of the PRI is corrected by the synchronization pulse of period T at point A of the pulse train of period .

[Problem that the invention seeks to solve]

Conventional bus generators have the following configuration, so a pulse counter that realizes a long cycle is required, and there are also problems such as the need to calculate the long cycle value in advance. was there.

This invention was made to solve the above problems.
The purpose of this invention is to create a bus generating device that can eliminate the need for a pulse counter that realizes a long period and can improve reliability.

[Means for Solving the Problems] The pulse generator according to the present invention separates PRI data into data that can be counted at the minimum clock and data below that, and generates a pulse when the minimum clock count and the PRI data match. , and at the same time add the data below it, and when the added value reaches countable data,
At that time, add countable data to PR1 data °C
It generates pulses.

[For production]

Pulse generation in this invention accumulates quantization errors that occur each time a pulse is generated, reaches correctable data, and then corrects the PRI data each time.
I Minimize the deviation of the pulse train due to data.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. In FIG. 1, C1 (1) is a microcontroller that controls C according to a program, (22 is a program memory that records control procedures, (3) is a minimum clock count,
The count value and PRI data are compared and [pulse generation time m14 for generating a coincidence detection signal and pulse train] is an address/data bus that interfaces with the microcontroller, (5) is a coincidence detection signal, and (6) is a pulse train. FIG. 2 shows the data format used by the pulse generation circuit (3) and the fibrocontroller. FIG. 8 shows a pulse train generated from the pulse generating circuit, and FIG. 4 is a program flowchart showing the contents of the control process.

Next, I will explain the operation. Microcontroller (
1) is controlled by a pre-stored program. Data is exchanged using an address data bus (4).

Follow the flowchart in Figure M4 [explained]. step a
In G, the microcontroller (1) initializes the internal registers used for control.

In Step 1, the pulse generation circuit (3) starts counting, and in step (B), PRI data (MSB is 1/2 of the minimum clock unit) is taken out from the memory and added. In step 4, if the added value is carrier-busted (n), that is, if lτ is higher than the minimum clock, then the PRI data (LSB
is the minimum clock unit) and the uploaded data, C,
While loading the comparison data of the pulse generation circuit (3), the added value is carrier-filled and fJ0 is P at step Q.
The RE data (LSB is the minimum clock unit) is loaded as comparison data to the pulse generation circuit (3)1.After this, the microprocessor periodically detects whether the coincidence detection signal (5) is generated in step (to). If a CU occurs, it will be transferred to another process. When the count value of the pulse generation circuit (3) and the comparison data match and a coincidence detection signal (5) is generated, the coincidence detection signal is reset in step Q5' [and the counter of the pulse generation circuit (3) is reset]. The process of retrieving the PRI data from the memory and adding it is re-executed.

The timing in Figure 8 is the pulse train (6) and the coincidence detection signal (
The coincidence detection signal (5) showing the relationship of 5) was detected, and in step (B), 4, 04, the added value was ∆[, which was less than the mosquito small lock unit], so the pulse train (5) was The repetition time is t
It changes from t+Δt.

In the embodiment described above, fixed PRI data was used, but variable data as shown in FIG. 5 can also be handled.

In other words, when the PRI data is taken out from the memory in step QJ), it is taken out in sequence #l to #n [addition processing is performed, and in the same way, the PRE data in step Q or o4 is used in sequence #l to #n [pulse Load the comparison data into the generation circuit and add the PRE data in the sequence #1 to #n-1. By loading the data, it is possible to generate a pulse train having pulse intervals grouped by the PRI Ic of #1 to #n1 and pulse intervals generated by the PRI of #n and the phase correction data.

〔Effect of the invention〕

As described above, according to the present invention, since the structure is configured to eliminate the accumulation of quantization errors every time a pulse is generated, the device can be manufactured at a low cost and has the advantage of being highly accurate.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a path generation device according to an embodiment of this invention, Fig. 2 is a data format diagram used in an embodiment of this invention, and Fig. 8 is a pulse train generated by this invention and coincidence detection. FIG. 4 is a timing diagram showing the relationship between signals; FIG. 4 is a data format diagram used in another embodiment of this invention; FIG.
7 is a diagram of the configuration of a conventional pulse generator, FIG. 7 is a diagram of a conventional data format, and FIG. 8 is a timing diagram showing the relationship between a conventional synchronizing signal and a pulse train. In the figure, C, 111 is a microcontroller, (2) is a memory, (3) is a pulse generation circuit, and (4) +! address data bus, (5) is a match detection signal, (6) I! Pulse train, (7) is a long-period pulse generation circuit, (8) is a synchronizing pulse, OQ is an initial setting step, U1j is a step of adding below the minimum clock, side is a step to judge whether it is below the minimum clock, 0 is a minimum clock The step of loading unit data to the pulse generation circuit, 04 is the step of adding rl data and the minimum clock unit data to the minimum clock unit stage, and loading it to the pulse generation circuit. is the step of resetting the coincidence detection signal. Note that the same reference numerals in each Q indicate the same or corresponding parts.

Claims (1)

[Claims] A pulse generator that generates a pulse train based on pulse repetition interval data counts at the minimum clock and generates a coincidence detection signal when it matches the pulse repetition interval data, and a pulse generation circuit that generates a pulse train from memory to the pulse repetition interval data. Control to extract and load data, control to add pulse repetition interval data less than the minimum clock value for each load mentioned above, and when the addition result exceeds the minimum clock value, add that data with the PRI data and load it to the pulse generation circuit. A pulse signal generating device comprising: a program memory that stores in advance a procedure for controlling and executing the load when a coincidence detection signal is detected; and a microcontroller for executing the control.