JPH0785209B2 - Timer monitoring method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a timer monitoring system in which a processor monitors various types of elapsed time.

[Conventional technology]

In a system including a processor, a conventional timer monitoring method that monitors that an elapsed time from a certain time reaches a predetermined time is provided with a single counter that generates a carry-out signal at a specific time outside the processor. Provided,
In general, the carry-out signal of the counter is used as an interrupt factor for the processor, and monitoring is performed depending on whether or not the number of interrupts reaches a value corresponding to the monitoring time.

[Problems to be solved by the invention]

By the way, according to the above-mentioned conventional method, when there are a plurality of types of time to be monitored, for example, from a relatively short time of 16 ms to a relatively long time of 1 s, the interrupt period is at least commensurate with the minimum time. It is necessary to set different times, and in addition to the interrupts required for other processing of the processor, frequent interrupts only for such timer monitoring occur, increasing the overhead of the processor and decreasing its processing capacity. There was a drawback of inviting.

The present invention has solved such a conventional drawback, and an object of the present invention is to provide a timer monitoring system with less processor overhead.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention provides a timer monitoring method in which a processor monitors the passage of a plurality of predetermined times, and a clock oscillation circuit and a clock generated by the clock oscillation circuit are provided outside the processor. A plurality of serially connected counters for counting pulses and a gate circuit for reading a count value of a counter suitable for the monitoring time of the plurality of counters are provided, and the processor requires timer monitoring. At the time
A timer for reading a count value of a counter suitable for the monitoring target time through the gate circuit, and storing an expected count value obtained by adding the read count value and a value corresponding to the monitoring target time in a memory A monitoring target set in advance by executing the startup process and periodically reading and comparing the expected count value set in the memory by the timer startup process and the count value of the corresponding counter during the steady process. It is configured to monitor whether time has elapsed.

Further, in a preferred embodiment of the present invention, the counter suitable for the monitoring time is counted up every integer fraction of the monitoring time and has a capacity of at least the monitoring time length.

[Action]

The operation of the present invention will be described with reference to a specific example.
When monitoring two types of time, i.e., 2s, one of the plurality of counters (hereinafter referred to as the first counter) is composed of, for example, a 4-bit counter that counts up every 4ms, One of the counters (hereinafter referred to as the second counter) is composed of, for example, a 4-bit counter that counts up every 400 ms, and a gate circuit is provided so that the count values of both counters can be read by the processor.

When the processor needs to start the 16ms timer, it reads the value of the first counter and adds an expected count value (hereinafter referred to as the first expected count value) obtained by adding the value "4" corresponding to 16ms. If you want to store it in memory and start the 400ms timer, read the value of the second counter
The expected count value (hereinafter referred to as the second expected count value) to which the value “5” corresponding to 400 ms is added is stored in the memory.

The processor periodically reads and compares the first and second expected count values and the first and second count values stored in the memory during the steady processing, and is preset by the comparison result. Monitors whether the monitoring target time of 16ms, 2s has elapsed.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a clock oscillator circuit 1, an l-ary counter 2a, an m-ary counter 2b, an n-ary counter 2c, and gate circuits 3a to 3c.
It is composed of a processor 6, a buffer memory 7, and a processor bus 5.

The clock oscillating circuit 1 generates a clock pulse a having a predetermined cycle. The clock pulse a is generated by the counter 2a.
The counter 2a counts the clock pulse a, and outputs 1 pulse b from the terminal co every time counting 1 clock pulse a. This pulse b
Is input to the terminal cp of the counter 2b in the latter stage, and the counter 2b
Counts its pulse b, and outputs one pulse c from the terminal co every time it counts m pulses b. This pulse c is further input to the terminal cp of the counter 2c in the subsequent stage, and the counter 2c counts the pulse c.

The count values of the counters 2a to 2c are taken out from the terminal Q and added to the gate circuits 3a to 3c. The gate circuits 3a to 3c output the input count value to the processor bus 5 when the gate control signals 4a to 4c become "1", for example, and output them high when the gate control signals 4a to 4c are "0". Impedance.

The processor 6 has a ROM and a RAM for storing programs, data, etc. therein, executes various controls according to the programs, and outputs gate control signals 4a to 4c to the gate circuits 3a to 4c.
The value of the counters 2a to 2c is selectively read via the processor bus 5 to the processor 3c, and the timer monitoring process described later is executed. The buffer memory 7 is a memory that can be written and read by the processor 6, and is used for storing an expected count value as described later.

The cycle of the clock pulse a in FIG. 1 and the base numbers of the counters 2a to 2c are determined according to the monitoring target time. For example, when the monitoring target time is three types of 16 ms, 200 ms, and 2 s, for example, the cycle of the clock pulse a is 4ms, counter 2a is a 25-base number counter (l
= 25), the counter 2b is a quaternary counter (m = 4),
It is sufficient for the counter 2c to have at least a quinary number (n = 5).

When the timer monitoring is performed with the above-mentioned configuration, processor 6 is programmed to perform the processing shown in FIGS. Here, Fig. 2 and Fig. 3 show 16ms
An example of the timer monitoring process is shown. Of these processes, FIG. 2 shows a process example when the 16 ms timer is activated, and FIG. 3 shows a process example after the activation. 4 and 5 show an example of 200 ms timer monitoring processing, FIG. 4 shows an example of processing when the 200 ms timer is activated, and FIG. 5 shows an example of processing after activation. Further, FIGS. 6 and 7 show an example of the 2s timer monitoring process, FIG. 6 shows an example of the process when the 2s timer is activated, and FIG. 7 shows an example of the process after the activation. Note that the processes of FIGS. 3, 5, and 7 are inserted in the middle of the steady process of the processor 6, and the process of FIG.
It is inserted in the processing path such that it is always processed once within s or several ms, and similarly, the processing of FIGS. 5 and 7 is always processed once within the allowable error time. It is inserted in the processing path.

In FIG. 1, the clock oscillation circuit 1 constantly outputs the clock pulse a, and the counters 2a to 2c constantly perform the counting operation. In such a state, when the 16 ms timer needs to be started in various processing steps of the processor 6, this is discriminated in step S1 of FIG. 2, and the processor 6 sets the gate control signal 4a to "1". 16
Count value of counter 2a at that time suitable for ms timer
Read CNTa internally via the processor bus 5 (S2),
A value "4" corresponding to the monitoring timer value of 16 ms is added to the count value CNTa to obtain the expected count value RCNTa (S3), and the expected count value RCNTa is stored in the area R16 in the buffer memory 7 (S4).

When the 16 ms timer starting process as described above is completed, when the processor 6 next executes the process shown in FIG. 3, it is determined in step S10 that the 16 ms timer is being started, and step S11
~ S15 is executed. That is, first, the gate control signal 4a is set to "1" to read the value CNTa of the counter 2a at that time (S11), and then the expected count value RCNTa stored in the area R16 of the buffer memory 7 is read ( S12), whether or not they match, and if they do not match, the expected count value
It is determined whether or not the value obtained by adding "1" to RCNTa is equal to the count value CNTa read in step S11 (S13, S14).
As described above, since the processing of FIG. 3 is inserted in the processing path that is executed once every 1 ms or every several ms, it is determined that both steps S13 and S14 are NO during the first time, and step S15 is skipped. Then, the next process is performed. However, when the process of FIG. 3 is executed when 16 ms or more has elapsed from the 16 ms timer starting process of FIG. 2, a match between the count value CNTa and the expected count value RCNTa is detected in step S13, or step S14 is executed. At, the coincidence between the count value CNTa and the expected count value plus "1" is detected, and it is detected that 16 ms has elapsed since step S15 was executed. The processing in step S14 is provided when the loop execution time is slightly delayed and the processing in FIG. 3 is not executed while the count value CNTa matches the expected count value RCNTa. It can be omitted if it is surely executed in the meantime, and the expected count value if the delay time is predicted to be longer.
The value added to RCNTa is not "1" but the accuracy is poor, but it may be increased, for example, "2".

Further, when it is necessary to start the 200 ms timer in various processing steps of the processor 6, this is discriminated in step S20 of FIG. 4, and the processor 6 sets the gate control signal 4b to "1", which is suitable for the 200 ms timer. The count value CNTb at that time of the counter 2b is read internally via the processor bus 5 (S21), and the value "2" corresponding to the monitoring timer value of 200 ms is added to the count value CNTb to obtain the expected count value RCNTb.
Is calculated (S22), and this expected count value RCNTb is stored in the area R200 in the buffer memory 7 (S23).

When the 200 ms timer starting process as described above is completed, when the next processor 6 executes the process shown in FIG. 5, it is determined in step S30 that the 200 ms timer is starting, and the value CNTb of the counter 2b at that time is read. Then, the expected count value RCNTb stored in the area R200 of the buffer memory 7 is read (S31, S32). Then, the count value CNTb
And the expected count value RCNTb is detected (S3
3), step S34 is executed and it is detected that the time of 200 ms has elapsed.

Similarly, when the 2s timer needs to be started in various processing steps of the processor 6, this is discriminated in step S40 of FIG. 6, and the processor 6 sets the gate control signal 4c to “1” to set the 2s timer. The counter value CNTc at that time of the suitable counter 2c is read internally via the processor bus 5 (S41), and the value "5" corresponding to 2s which is the monitoring timer value is added to the counter value CNTc and the expected count value RCNTc.
Is calculated (S42), and this expected count value RCNTc is stored in the area R2 in the buffer memory 7 (S43). Therefore, when the processor 6 next executes the processing shown in FIG. 7, it is determined in step S50 that the 2s timer is being activated, and the value CNTc of the counter 2c at that time is read and stored in the area R2 of the buffer memory 7. The expected count value RCNTc that has been set is read (S51, S52), and at the time when a match between the two is detected, it is detected that 2 seconds have elapsed (S53, S5).
Four). It should be noted that in FIGS. 5 and 7, the process of step S14 of FIG. 3 is not provided because the process of FIGS. 5 and 7 is significantly faster than the monitoring target time of 200 ms, 2 s. It depends on the assumption that it will be executed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various other additions and modifications can be made. For example, in the embodiment of FIG.
Although three counters 2a to 2c are provided to monitor three types of timers, two or four or more counters may be provided to perform two or four or more types of timer monitoring. In addition, a counter for adjusting the count-up cycle of another counter used for monitoring may be included in the plurality of counters. Further, it is preferable that the count-up cycle of the counter used for monitoring is set to be an integral fraction of the monitoring target time, but if it is within the allowable range of error, it is not always necessary to do so. It is also possible to configure the same timer monitoring to be activated from different processing steps of the processor at different times.

〔The invention's effect〕

As described above, the present invention is provided outside the processor.
Provide a counter row that includes a counter whose count-up period and capacity are suitable for the monitored time, read the value of the counter suitable for the monitored time when the timer starts, and store the expected count value that is the sum of the monitored time in the memory However, during the subsequent steady processing, the timer is monitored by periodically determining whether or not the value of the counter has reached the expected count value. A plurality of types of timer monitoring can be realized without using the carry-out signal as an interrupt factor for the processor, and the processor overhead can be reduced. Therefore, there is an effect that the processing capability of the processor can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart showing an example of processing when the 16 ms timer is started, FIG. 3 is a flowchart showing an example of processing after starting the 16 ms timer, and FIG. 4 is a 200 ms timer. 5 is a flowchart showing an example of processing at the time of starting, FIG. 5 is a flowchart showing an example of processing after starting the 200 ms timer, FIG. 6 is a flowchart showing an example of processing at the time of starting the 2s timer, and FIG. It is a flow chart showing an example of processing. In the figure, 1 ... Clock oscillator circuit, 2a-2c ... Counter, 3a-3c ... Gate circuit, 4a-4c ... Gate control signal, 5
... processor bus, 6 ... processor, 7 ... buffer memory.

Claims (2)

[Claims] 1. A timer monitoring system in which a processor monitors the passage of a plurality of predetermined times, and a clock oscillator circuit and a serial connection for counting clock pulses generated in the clock oscillator circuit outside the processor. A plurality of counters, and a gate circuit for reading the count value of a counter suitable for the monitoring time of the plurality of counters, and the processor, when the timer monitoring is required,
A timer for reading a count value of a counter suitable for the monitoring target time through the gate circuit, and storing an expected count value obtained by adding the read count value and a value corresponding to the monitoring target time in a memory A monitoring target set in advance by executing the startup process and periodically reading and comparing the expected count value set in the memory by the timer startup process and the count value of the corresponding counter during the steady process. A timer monitoring scheme configured to monitor whether time has elapsed. 2. The timer monitoring system according to claim 1, wherein the counter suitable for the monitoring time is counted up every integer fraction of the monitoring time, and at least the monitoring time. A timer monitoring method characterized by having a long capacity.