CN115486059A

CN115486059A - Signal processing method, device, equipment, storage medium and computer equipment

Info

Publication number: CN115486059A
Application number: CN202080094524.5A
Authority: CN
Inventors: 尹前澄; 胡玉昕; 杨焕刚; 葛敏锋; 周晶晶
Original assignee: Xian Novastar Electronic Technology Co Ltd
Current assignee: Xian Novastar Electronic Technology Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2022-12-16
Also published as: WO2022104653A1

Abstract

A signal processing method, a signal processing device, a storage medium and a computer device are provided. The method comprises the following steps: acquiring a phase difference between a first output field sync signal VS of the video signal and a reference field sync signal VS (S802); determining a phase adjustment value according to the phase difference (S804); a target pixel clock frequency is obtained according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal (S806).

Description

Signal processing method, device, equipment, storage medium and computer equipment

Technical Field

The present invention relates to the field of display technologies, and in particular, to a signal processing method, apparatus, device, storage medium, and computer device.

Background

In various application scenarios of video signal processing equipment, it is necessary to ensure that output video signals of each equipment are synchronized with reference signals, so as to achieve synchronization among multiple equipments. In the related art, a method for synchronizing an output video signal with a reference signal includes: when the output field sync signal (VSYNC, abbreviated as VS) of the video signal is synchronized with the reference signal VS of the reference signal, it is considered that the output video signal is synchronized with the reference signal. However, in the related art, the output VS and the reference VS cannot be strictly synchronized.

In the related art, when the adjustment output VS is synchronized with the reference VS, there is a problem that the adjustment accuracy is rough.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

Embodiments of the present invention provide a signal processing method, apparatus, device, storage medium, and computer device, so as to at least solve a technical problem in the related art that an adjustment precision is relatively coarse when an adjustment output VS is synchronized with a reference VS.

According to an aspect of an embodiment of the present invention, there is provided a signal processing method including: acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS; determining a phase adjustment value according to the phase difference; and obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.

Optionally, the determining a phase adjustment value according to the phase difference includes: and determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller.

Optionally, the determining, by the PID controller, a phase adjustment value corresponding to the phase difference includes: setting a control coefficient of the PID controller, wherein the control coefficient comprises: a proportionality coefficient, an integral coefficient, and a differential coefficient; and determining a phase adjustment value corresponding to the phase difference through the PID controller after setting the coefficient.

Optionally, the determining, by a PID controller, a phase adjustment value corresponding to the phase difference includes: determining a phase adjustment value corresponding to the phase difference by:

incr _ phase = KP, fresh _ phase + KI, total _ phase + KD (fresh _ phase-last _ phase); wherein, fresh _ phase is the phase difference, total _ phase is the accumulated sum of fresh _ phase within the counted historical adjustment times, last _ phase is the phase difference of the last adjustment of the current adjustment, incr _ phase is the phase adjustment value, KP is the proportionality coefficient, KI is the integral coefficient, and KD is the differential coefficient.

Optionally, the obtaining a target pixel clock frequency according to the phase adjustment value includes: determining a frequency adjustment value according to the phase adjustment value; and obtaining the clock frequency of the target pixel according to the frequency adjustment value.

Optionally, the obtaining a target pixel clock frequency according to the phase adjustment value includes: determining a percentage of the phase adjustment value in N frame periods, wherein N is a positive integer; determining the target pixel clock frequency according to the current pixel clock frequency of the video signal and the percentage.

Optionally, the percentage of the phase adjustment value over N frame periods is determined by: incr _ freq _ percentage = incr _ phase/gen _ vs _ T, where incr _ freq _ percentage is the percentage, incr _ phase is the phase adjustment value, and gen _ vs _ T is the N frame periods.

Optionally, the target pixel clock frequency is determined according to the current pixel clock frequency of the video signal and the percentage by: fresh _ freq = last _ freq (1 + incr _ freq _ percent), wherein, freq _ freq is the target pixel clock frequency and last _ freq is the current pixel clock frequency.

Optionally, the acquiring a phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS includes: receiving the phase difference sent by an FPGA chip; or, receiving the first output VS and the reference VS through a phase detector, and obtaining the phase difference between the first output VS and the reference VS.

Optionally, after obtaining the target pixel clock frequency according to the frequency adjustment value, the method further includes: generating configuration information according to the target pixel clock frequency; and sending the configuration information to a clock chip, wherein the configuration information is used for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency.

Optionally, after the sending the configuration information to the clock chip, the method further includes: and sending the timing parameter of the video signal to a timing generator, wherein the timing parameter is used for generating the second output VS by the timing generator after being combined with a target pixel clock generated by the clock chip.

Alternatively, the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency is repeatedly performed in a frame period.

Optionally, before obtaining the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS, further comprising: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; in the case that the detection result is yes, determining to perform an operation of acquiring the phase difference between a first output VS of the video signal and the reference VS; and/or, in the case that the detection result is negative, returning to the operation of determining whether the periodic fluctuation of the reference VS is smaller than a predetermined fluctuation threshold.

According to another aspect of the present invention, there is provided a signal processing apparatus including: the acquisition module is used for acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS; the determining module is used for determining a phase adjustment value according to the phase difference; and the processing module is used for obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.

According to still another aspect of the present invention, there is provided a signal processing apparatus including: a first processor, configured to run a program, wherein the program is configured to perform any one of the signal processing methods when running.

Optionally, the apparatus further comprises: a second processor, wherein the second processor is configured to determine the phase difference between the first output VS of the video signal and the reference VS and send the phase difference to the first processor.

Optionally, the second processor comprises: a phase detector and a timing generator, wherein the phase detector is configured to receive inputs of the first output VS and the reference VS and output the phase difference between the first output VS and the reference VS; and the timing generator is used for receiving the timing parameters of the video signals sent by the processor and generating the second output VS according to the timing parameters and the target pixel clock generated by the clock chip.

Optionally, the apparatus further comprises: the clock chip is configured to receive configuration information sent by the first processor, where the configuration information is generated by the first processor according to the target pixel clock frequency; the clock chip is further used for generating a target pixel clock according to the target pixel clock frequency configured by the configuration information.

According to still another aspect of the present invention, there is provided a storage medium including a stored program, wherein when the program is executed, a device on which the storage medium is located is controlled to execute any one of the signal processing methods described above.

According to still another aspect of the present invention, there is provided a computer apparatus comprising: a memory and a third processor, the memory storing a computer program; the third processor is configured to execute a computer program stored in the memory, and when the computer program runs, the third processor is configured to execute any one of the signal processing methods described above.

In the embodiment of the present invention, a phase difference between the first output VS of the video signal and the reference VS is obtained, and a phase adjustment value is determined according to the phase difference, and a target pixel clock frequency is obtained according to the phase adjustment value, so that a purpose of determining a specific phase adjustment value according to the phase difference, and obtaining a specific target pixel clock frequency according to the specific phase adjustment value is achieved, and a technical effect of improving an adjustment precision is achieved by determining the specific phase adjustment value and obtaining the specific target pixel clock through conversion between the phase adjustment and the frequency adjustment when the output VS of the video signal is adjusted to be synchronous with the reference VS, thereby solving a technical problem of a coarse adjustment precision when the output VS is adjusted to be synchronous with the reference VS in the related art.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

fig. 1 is a schematic diagram of an application scenario 1 of a video processing apparatus in an embodiment of the present invention;

fig. 2 is a schematic diagram of an application scenario 2 of the video processing apparatus in the embodiment of the present invention;

FIG. 3 is a schematic diagram of output video timing in the case of frame synchronization according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a first scheme for synchronizing the regulated output VS with the reference VS according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a second scheme for synchronizing the regulated output VS with the reference VS according to an embodiment of the present invention;

fig. 6 is a schematic diagram of information obtained by the synchronization signal detection comparing unit in the second solution provided in the embodiment of the present invention;

fig. 7 is a schematic diagram of the phase difference count obtained by the synchronization signal detection comparing unit in the second solution provided in the embodiment of the present invention;

FIG. 8 is a flow chart of a signal processing method according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a signal processing apparatus for implementing a signal processing method according to an alternative embodiment of the present invention;

FIG. 10 is a schematic diagram of a signal processing method according to an alternative embodiment of the invention;

fig. 11 is a block diagram of a signal processing apparatus according to embodiment 2 of the present invention;

fig. 12 is a block diagram of a computer terminal according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

First, some terms or terms appearing in the description of the embodiments of the present application are applicable to the following explanations:

the function of the row sync signal (HSYNC, HS for short) is to select the active row signal interval on the display panel.

The field sync signal (VSYNC, VS) is used to select the active field signal interval on the display panel.

The Genlock (Genlock) can synchronize one or more systems with the same synchronization source, for example, can control the timing parameters (PCLK, HS, VS) of the output video signal of the video processing device to synchronize with the external reference signal, so as to achieve the purpose of synchronizing the output video signal with the reference signal.

Frame synchronization (Framelock), in which the frame frequency of the output video signal of the control device is synchronized with the frame frequency of the external reference signal, to achieve the purpose of synchronizing the frame frequency of the output video signal with the reference signal.

The PID (Proportion Integration Differentiation, PID for short) controller and the PID controller form control deviation according to a given value and an actual output value, and the control algorithm is simple, good in robustness and high in reliability.

An FPGA (Field Programmable Gate Array, FPGA for short) chip, a Field Programmable logic Gate Array, belongs to a semi-custom circuit in the Field of special integrated circuits.

Example 1

In accordance with an embodiment of the present invention, there is provided a method embodiment of a signal processing method, it should be noted that the steps illustrated in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than that herein.

In many application scenarios of the video processing device, it is necessary to ensure that the video signal output by the video processing device is synchronized with the reference signal. In this case, the Genlock function has an important meaning to the video processing apparatus. In order to illustrate the significance of the Genlock function to the video processing device, the following application scenarios of several video processing devices are illustrated, and in the following application scenarios, the video signal output by the video processing device is abnormal because the Genlock function is not used.

For example, fig. 1 is a schematic diagram of an application scenario 1 of a video processing device in an embodiment of the present invention, and as shown in fig. 1, when multiple video processing devices (e.g., video stitchers) work cooperatively to splice a large video frame, it is necessary to ensure that output video signals of all the video processing devices are synchronized, and thus a single video processing device needs to start a Genlock function to synchronize output video signals with the same reference signal. Without Genlock functionality, tearing may occur at the edges of the output image between video processing devices. As shown in fig. 1, genlock is not used by the video processing apparatus 3, resulting in the output picture of the video processing apparatus 3 being out of sync with the output pictures of other video processing apparatuses.

For another example, fig. 2 is a schematic diagram of an application scenario 2 of a video processing device in an embodiment of the present invention, as shown in fig. 2, in a studio environment, the video processing device outputs a video signal to a screen, and when a video camera shoots a scene including the screen, it is required to ensure that video sampling of the camera is kept synchronous with refreshing of an output picture on the screen, otherwise, a rolling stripe may be caused in an image shot by the camera on the screen. To solve this problem, a Genlock function is also added to the video processing apparatus, and may be implemented using frame synchronization, for example.

Fig. 3 is a schematic diagram of the output video timing in the case of frame synchronization according to an embodiment of the present invention, as shown in fig. 3, the ideal state between the output video timing and the reference signal in the case of frame synchronization, i.e. the output VS remains synchronized with the reference VS. In the figure, vtotal represents the period of the output VS; htotal represents the period of outputting HS.

To achieve frame synchronization, the following steps may be employed: firstly, measuring the frame frequency of a reference VS; generation of frame frequency input clock of measured reference VSThe device generates an output pixel clock and determines output timing sequence parameters according to the output resolution and the like set by a current user aiming at the video signal; thereafter, an output VS of the video signal is generated using a timing generator based on the output pixel clock and the output timing parameter, and the output VS of the video signal is substantially synchronized with the reference VS because the output VS of the video signal is generated based on the output pixel clock generated at the frame rate of the reference VS. The calculation formula of the output pixel clock frequency is as follows: f _PCLK ＝F _VS(ref) *Htotal*VTotal，F _VS(ref) For reference VS frame frequency, htotal is the period of outputting HS, VTotal is the period of outputting VS; 3) Keeping the output VS always in synchronization with the reference VS.

However, by using the above synchronization method, the output VS of the video signal is not strictly synchronized with the reference VS, and the output VS of the video signal is easily unlocked from the reference VS.

In order to always synchronize the regulated output VS and the reference VS, the following first scheme may be adopted, and fig. 4 is a schematic diagram of the first scheme for synchronizing the regulated output VS and the reference VS provided by the embodiment of the present invention, as shown in fig. 4, the first scheme includes: control unit realizes VS frame frequency F _VS(ref) Is measured and then calculated to obtain F _PCLK According to F _PCLK And configuring a programmable clock generator to obtain the PCLK, and generating a video time sequence by the time sequence generator under the drive of the PCLK according to the configured time sequence parameters.

In the first scheme, in order to ensure that the output VS and the reference VS are always synchronized, the video timing generator is reset each time when a new reference VS signal arrives, and the video timing of the next frame output is regenerated, so as to achieve the purpose of synchronizing the output VS and the reference VS. However, in the first solution, since the timing generator is directly reset by using the external reference signal to output the timing, since the reference signal is not controllable, there are the following disadvantages: first, forced resetting of the output timing results in a portion of the display device not accepting such video signals; second, since the output timing is reset every frame, frame rate conversion cannot be achieved.

In order to always synchronize the output VS with the reference VS, the following scheme two may also be adopted, and fig. 5 is a schematic diagram of the scheme two for synchronizing the output VS with the reference VS provided by the embodiment of the present invention, as shown in fig. 5, the scheme two includes: synchronous signal detection comparison unit for realizing frame frequency F of reference VS _VS(ref) Is measured, the control unit calculates F _PCLK Configuring a programmable clock generator to obtain a PCLK, and generating a video time sequence by the time sequence generator under the drive of the PCLK according to the configured time sequence parameters; the output VS is fed back to the synchronizing signal detection and comparison unit, and fine-tuned F under the comparison of the synchronizing signal detection and comparison unit _PCLK To ensure that the output VS is always synchronized with the reference VS.

Fig. 6 is a schematic diagram of information obtained by the synchronization signal detection comparing unit in the second solution provided in the embodiment of the present invention, and as shown in fig. 6, the synchronization signal detection comparing unit detects and compares the following information: the phase relationship between the output VS and the reference VS can be detected, specifically, the phase relationship includes phase advance and phase lag; the frequency relationship between the output VS and the reference VS can also be detected, specifically, the frequency of the output VS is higher than that of the reference VS and the frequency of the output VS is lower than that of the reference VS; the method can also comprise the following steps: and (4) counting the phase difference.

Fig. 7 is a schematic diagram of the phase difference count obtained by the synchronization signal detection comparing unit in the second scheme provided in the embodiment of the present invention, and as shown in fig. 7, the distance between the reference VS and the high-level edge of the output VS can be recorded as the phase difference; or the distance of the reference VS from the low-level edge of the output VS can also be recorded as a phase difference.

The change trend of the current output VS compared with the reference VS can be obtained through the information acquired by the synchronous signal detection and comparison unit, and the frequency of the output PCLK is correspondingly adjusted under different conditions, so that the synchronization of the output VS and the reference VS is kept.

Table 1 is a feedback adjustment strategy table performed according to a variation trend of the output VS compared to the reference VS, and as shown in table 1, the feedback adjustment strategy shown in table 1 may be provided for adjustment of the output VS according to detection of a phase difference between the reference VS and the output VS.

TABLE 1

The change trend of the current output VS compared with the reference VS can be obtained through the state parameters obtained by the synchronous signal detection and comparison unit, and the frequency of the output PCLK is adjusted under different conditions. When adjusting, the following method can be adopted: and comparing the phase difference between the output VS and the reference VS, and obtaining the variation trend of the output VS relative to the reference VS according to the phase difference, so as to correspondingly adjust the pixel clock frequency (the pixel clock frequency is used for generating a pixel clock which is used for generating the output VS). For example, when the phase difference between the output VS and the reference VS exceeds a threshold, a change trend of leading or lagging of the output VS with respect to the reference VS is obtained, and the synchronization of the output VS and the reference VS is realized by increasing or decreasing the frequency of the pixel clock used for generating the pixel clock. However, in this scheme, the adjustment of the trend is made in accordance with the comparison of the phase difference between the output VS and the reference VS with a threshold value, and thus the adjustment accuracy is rough. Since the threshold setting of the phase difference determines the adjustment speed, frequent adjustments are required when the threshold setting is too low; and the threshold is set too high, the swing amplitude of the output VS with respect to the reference VS is large. The preset threshold determines the maximum swing amplitude of the output VS relative to the reference VS, i.e., the performance of genlock, and is limited by hardware capability, and the threshold cannot be set very low. Therefore, the system cannot realize high-precision phase locking due to the high preset threshold value, and the system cannot work in the optimal state. This way of adjustment does not lead to a converged result.

In view of the above problem of coarse adjustment precision when the adjustment output VS is synchronized with the reference VS, in an embodiment of the present invention, a signal processing method is provided, and fig. 8 is a flowchart of the signal processing method according to an embodiment of the present invention.

Optionally, the method may be performed by a video processing device, wherein the video processing device may comprise: a video processor, a video switcher, a video splicer, or the like for performing video processing or control.

Optionally, the method may be further performed by a processing chip, and the processing chip may include: a Micro Controller Unit (MCU) or a microprocessor (hereinafter, referred to as MCU), an enhanced Reduced Instruction Set Computer processor (RISC) Machines or an FPGA, and other chips for data processing.

As shown in fig. 8, the method includes the steps of:

step S802, obtaining a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS;

step S804, determining a phase adjustment value according to the phase difference;

step S806, obtaining a target pixel clock frequency according to the phase adjustment value, where the target pixel clock frequency is used to generate a second output VS of the video signal.

Through the steps, the phase difference between the first output VS of the video signal and the reference VS is obtained, the target pixel clock frequency is obtained according to the phase difference and the phase adjustment value, so that the purposes of determining the specific phase adjustment value according to the phase difference and obtaining the specific target pixel clock frequency according to the specific phase adjustment value are achieved, the technical effect of improving the adjustment precision is achieved by determining the specific phase adjustment value and obtaining the specific target pixel clock through the conversion between the phase adjustment and the frequency adjustment when the output VS of the video signal is adjusted to be synchronous with the reference VS, and the technical problem that the adjustment precision is rough when the output VS is adjusted to be synchronous with the reference VS in the related technology is solved.

As an alternative embodiment, the method may be applied to a video processing device, that is, a processor of the video processing device may be used as an execution subject of the method. It should be noted that the video processing apparatus may be of various types, for example, a terminal for processing a video signal, a server for executing a function of processing a video signal, or the like.

As an alternative embodiment, when determining the phase adjustment value according to the phase difference, various manners may be adopted, for example, the phase adjustment value corresponding to the phase difference may be determined by a PID controller. That is, the phase adjustment value is output from the PID controller by inputting the phase difference of the output VS and the reference VS to the PID controller. The proportional-integral-derivative PID controller comprises a proportional unit (P), an integral unit (I) and a derivative unit (D), can form control deviation according to a given value and an actual output value, basically maintains stable variable, and is a controller with simple algorithm, good robustness and high reliability. Based on the above problem of the accuracy of Genlock, in this optional embodiment, the video processing device adjusts the frequency of PCLK according to the calculation result of the control algorithm by adding the control algorithm adopted by the PID controller, so as to achieve the optimal locking state of hardware. The accuracy of Genlock can be further improved by adding a control algorithm of a PID controller.

As an alternative embodiment, when determining the phase adjustment value corresponding to the phase difference through the PID controller, the following manner may be adopted: setting a control coefficient of the PID controller, wherein the control coefficient comprises: a proportionality coefficient, an integral coefficient, and a differential coefficient; and determining a phase adjustment value corresponding to the phase difference through the PID controller after the coefficient is set. And setting the control coefficient of the PID controller, so that the convergence speed and the overshoot amplitude can be balanced, and a core calculation formula of the algorithm is obtained. And determining a phase adjustment value corresponding to the phase difference through the PID controller after setting the coefficient to obtain an accurate phase adjustment value, and providing a basis for obtaining an accurate target pixel clock frequency subsequently.

As an alternative embodiment, when determining the phase adjustment value corresponding to the phase difference through the PID controller, the phase adjustment value corresponding to the phase difference may be determined in the following manner:

incr _ phase = KP, fresh _ phase + KI, total _ phase + KD (fresh _ phase-last _ phase); the fresh _ phase is a phase difference, the total _ phase is an accumulated sum of the fresh _ phase within the counted historical adjustment times, last _ phase is a phase difference adjusted last time at this time, incr _ phase is a phase adjustment value, KP is a proportionality coefficient, KI is an integral coefficient, and KD is a differential coefficient.

As an optional embodiment, when the target pixel clock frequency is obtained according to the phase adjustment value, the adopted parameters may also be different according to different manners of obtaining the target pixel clock frequency.

For example, the target pixel clock frequency may be obtained in the following manner: firstly, obtaining a frequency adjustment value according to the phase adjustment value; and finally, obtaining the clock frequency of the target pixel according to the frequency adjustment value. It should be noted that, the phase adjustment value has positive and negative values, which indicates whether the phase of the output VS is advanced or delayed relative to the reference VS; the frequency adjustment value also corresponds to positive or negative, i.e. to a value corresponding to the frequency adjustment value is added or subtracted on the basis of the current pixel clock frequency of the video signal.

For another example, the target pixel clock frequency may also be obtained in the following manner: determining the percentage of a phase adjustment value in N frame periods, wherein N is a positive integer; a target pixel clock frequency is determined based on the current pixel clock frequency of the video signal, and the percentage. Wherein N frame periods represent the current phase value of the output VS of the video signal. The phase adjustment value and the N frame periods referred to above may be expressed by a time having a uniform unit, for example, may be expressed by seconds, or may be expressed by nanoseconds.

As an alternative embodiment, when determining the target pixel clock frequency from the current pixel clock frequency of the video signal, and the percentage, the percentage of the phase adjustment value over N frame periods is determined by: incr _ freq _ percent = incr _ phase/gen _ vs _ T, where incr _ freq _ percent is a percentage, incr _ phase is a phase adjustment value, and gen _ vs _ T is N frame periods. As described above, the incr _ phase and gen _ vs _ phase may be expressed by a time with a uniform unit, and when the unit is not uniform, a value converted by a formula may be added to the formula, for example, when the unit of gen _ vs _ T is second and the unit of incr _ phase is nanosecond, the gen _ vs _ T may be multiplied by the power of 9 of 10 to obtain a value with the unit of gen _ vs _ T being nanosecond, and then the percentage may be calculated according to the formula.

After determining the above percentage, when the target pixel clock frequency is to be determined, the target pixel clock frequency may be determined from the current pixel clock frequency of the video signal and the percentage by: fresh _ freq = last _ freq (1 + incr _ freq _ percent), wherein, fresh _ freq is the target pixel clock frequency and last _ freq is the current pixel clock frequency.

It should be noted that, the above-mentioned manner of obtaining the target pixel clock frequency through the frequency adjustment value and the manner of determining the target pixel clock frequency through the current pixel clock frequency and the percentage can be flexibly selected according to the needs, but no matter which manner is adopted, the relationship between the phase and the frequency is effectively utilized, the phase adjustment is converted into the frequency adjustment, and thus the pixel clock frequency can be conveniently and accurately configured for the subsequent clock generator.

As an alternative embodiment, the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS may be obtained in various ways, for example, the phase difference sent by the FPGA chip may be received; or, receiving the first output VS and the reference VS through a phase detector, and obtaining a phase difference between the first output VS and the reference VS. Through the above processing, the phase difference between the first output VS and the reference VS can be directly obtained by the FPGA chip, the phase detector, or a combination of the FPGA chip and the phase detector (for example, in the case where the phase detector is integrated in the FPGA chip).

As an optional embodiment, after obtaining the target pixel clock frequency according to the frequency adjustment value, the method further includes: generating configuration information according to the target pixel clock frequency; and sending configuration information to the clock chip, wherein the configuration information is used for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency. Through the processing, the target pixel clock frequency is configured to the clock chip, and the clock chip is used for generating the target pixel clock according to the target pixel clock frequency.

As an optional embodiment, after sending the configuration information to the clock chip, the method further includes: and sending the timing parameters of the video signal to a timing generator, wherein the timing parameters are used for generating a second output VS by the timing generator after being combined with a target pixel clock generated by a clock chip. Through the processing, the time sequence parameter of the video signal is sent to the time sequence generator, and the time sequence generator is used for generating the second output VS based on the target pixel clock generated by the clock chip and the time sequence parameter, so that the primary adjustment process of outputting the VS and synchronizing the reference VS is completed.

As an alternative embodiment, the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency may be repeatedly performed in a frame period, that is, the adjustment of the synchronization of the primary output VS and the reference VS is performed in a period of one frame time, thereby achieving high-precision frame synchronization.

As an alternative embodiment, before acquiring the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS, the method further includes: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; in the case where the detection result is yes, determining to perform an operation of acquiring a phase difference between the first output VS of the video signal and the reference VS; and/or, in the case that the detection result is negative, returning to the operation of determining whether the periodic fluctuation of the reference VS is smaller than a predetermined fluctuation threshold.

It should be noted that the predetermined fluctuation threshold corresponding to the reference VS may be set differently according to the reference VS. By setting a fluctuation threshold, it can be used to characterize the stability of the reference VS. The more stable the VS is, the more accurate the synchronization between the output VS and the reference VS is. For example, the fluctuation threshold may be set as a percentage of the periodic fluctuation with respect to the entire statistical period of the reference VS, for example, when the fluctuation of the reference VS is less than 30% of the fluctuation threshold, the reference VS is considered to be stable and may be used as a reference for synchronizing the output VS.

Based on the above embodiments and alternative embodiments, an alternative implementation of the present invention is described below.

Fig. 9 is a schematic diagram of a signal processing apparatus for implementing a signal processing method according to an alternative embodiment of the present invention. Alternatively, the signal processing apparatus may be a video processing apparatus, wherein the video processing apparatus may include: a video processor, a video switcher, or a video splicer, etc. for performing video processing or control. As shown in fig. 9, the signal processing apparatus may include the following: the signal processing arrangement is described below in terms of a clock chip 6208, an MCU, an FPGA chip (where the FPGA chip may be integrated with a timing generator and a phase detector).

The clock chip 6208 is configured to generate a clock source for controlling a system expected frequency, that is, to receive configuration information of the MCU, and generate a pixel clock according to a pixel clock frequency configured by the configuration information; the MCU is used for configuring a clock chip 6208 and running a control algorithm; the FPGA chip comprises a Timing generator and a phase detector, wherein the Timing generator is used for generating an output Timing (Timing _ gen) of a video signal according to a pixel clock (gen _ clk) and a Timing parameter (Timing _ para), and the phase detector (phase _ det) is used for receiving an output VS of the video signal and a reference VS, so that a phase difference (phase _ error) between the output VS and the reference VS is output, and the phase _ error is pushed to the MCU and used as an input parameter of a control algorithm.

It should be noted that, the MCU is for configuring a clock chip and controlling the operation of an algorithm more conveniently, and the MCU may be replaced by another main control device, for example, a Digital Signal Processor (DSP), a Personal Computer (PC), or even directly placed in an FPGA to be a main control.

Fig. 10 is a schematic diagram of a signal processing method according to an alternative embodiment of the present invention, as shown in fig. 10, the method comprising the steps of:

step 1) starting a Genlock function;

step 2) acquiring a reference VS period from the FPGA chip;

step 3) calculating the frequency of a Pixel Clock (PCLK) according to the current resolution, and configuring the PCLK frequency to a clock chip through configuration information;

step 4) determining the stability of PCLK from the FPGA chip, and starting phase detection of the FPGA chip, namely, detecting the phase difference between the output VS and the reference VS through a phase detector in the FPGA chip;

step 5) after the MCU receives the interrupt, reading the phase difference count and the reference VS period from the FPGA chip;

step 6) judging whether the reference VS cycle fluctuation is less than 30%, if yes, entering step 7), and if no, entering step 2);

step 7) executing an automatic adjustment algorithm and configuring the clock frequency of the target pixel;

and 8) finishing one adjustment, waiting for the arrival of the next interrupt, and entering the step 5) when the arrival of the next interrupt.

The tuning algorithm of an alternative embodiment of the present invention, based on the control logic of the PID controller, is as follows:

incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；

the fresh _ phase is the latest phase difference count obtained after each interrupt, namely the phase difference, which is the clock period (sample _ t) adopted by the FPGA, and is in the unit ns.

total _ phase is the cumulative sum of fresh _ phase received each time, i.e. the cumulative sum of fresh _ phase over the historical number of adjustments of the statistics referred to above.

last _ phase is the last fresh _ phase (i.e., the last adjusted phase difference for this adjustment).

incr _ phase is the phase value that needs to be adjusted (i.e., the phase adjustment value referred to above).

Three regulating coefficients are set by balancing the convergence speed and the overshoot amplitude: KP, KI and KD, and obtaining the above-mentioned calculation formula of the control algorithm.

After the phase value to be adjusted is calculated, the frequency value (i.e., the target pixel clock frequency) to be converted to the clock chip 6208 is obtained, and the relationship between the phase and the frequency adjustment is obtained by deduction according to the relationship between the clock and the phase as follows:

the frequency adjustment percentage may be calculated from the adjustment phase value in the following manner:

it should be noted that the 9 th power of 10 is because the unit of gen _ vs _ T is second, the unit of incr _ phase is nanosecond, and the unit of gen _ vs _ T is converted to ns in order to realize uniformity. last _ freq is the last configured frequency value (i.e., the current pixel clock frequency mentioned above), in hz.

Finally, the frequency value to be allocated to the clock chip (i.e. the above target pixel clock frequency) is obtained:

fresh_freq＝last_freq*(1+incr_freq_percent)

and allocating a new frequency value (namely the target pixel clock frequency) to the clock chip to complete an adjusting process.

And the microprocessor MCU waits for the FPGA chip to initiate the next interrupt, and then repeats the steps, and the characteristic of the algorithm can continuously approach the Gen _ VS to the reference VS (ref _ VS) along with multiple times of calculation processing, so that high-precision Genlock locking is achieved.

Through the optional embodiment, the rapid locking convergence of the video output VS to the reference VS is realized, so that the high-precision synchronization of the output VS and the reference VS is realized. Through actual measurement, the current following error of 10us can be reduced to 150ns, and the following error is improved by 60 times. The error is determined by the precision of the clock chip and the phase detection frequency of the phase detector, and under the condition of not replacing hardware, the optional implementation mode can ensure that the Genlock precision is pushed to the limit which can be reached by the hardware, so that good performance is obtained.

Example 2

According to an embodiment of the present invention, there is also provided a signal processing apparatus, and fig. 11 is a block diagram of a structure of a signal processing apparatus according to embodiment 2 of the present invention, and as shown in fig. 11, the signal processing apparatus 1100 includes: an acquisition module 1102, a determination module 1104, and a processing module 1106. The signal processing apparatus 1100 will be specifically described below.

An obtaining module 1102, configured to obtain a phase difference between a first output field sync signal VS of the video signal and a reference field sync signal VS;

a determining module 1104, connected to the obtaining module 1102, for determining a phase adjustment value according to the phase difference;

the processing module 1106 is connected to the determining module 1104, and configured to obtain a target pixel clock frequency according to the phase adjustment value, where the target pixel clock frequency is used to generate a second output VS of the video signal.

It should be noted that the acquiring module 1102, the determining module 1104 and the processing module 1106 correspond to steps S402 to S406 in embodiment 1, and the modules are the same as the examples and application scenarios realized by the corresponding steps, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as a part of the apparatus may be operated in the computer terminal provided in embodiment 1.

According to an embodiment of the present invention, there is also provided a signal processing apparatus including a first processor configured to execute a program, where the program executes to perform any one of the signal processing methods provided in the embodiment or the alternative embodiment of embodiment 1. It should be noted that the type of the first processor may be various, for example, the first processor may be the MCU described above, or an ARM.

As an alternative embodiment, the signal processing apparatus further includes: a second processor, wherein the second processor is configured to determine a phase difference between the first output VS of the video signal and the reference VS and to send the phase difference to the first processor. The first processor and the second processor may be the same processor, or may be two different processors. For example, when the first processor and the second processor are different processors, the first processor may be the MCU described above, and the second processor may be a field programmable gate array FPGA chip or the like.

As an alternative embodiment, the second processor may comprise: the phase detector is used for receiving the input of the first output VS and the reference VS and outputting the phase difference between the first output VS and the reference VS; and the time sequence generator is used for receiving the time sequence parameters of the video signals sent by the processor and generating a second output VS according to the time sequence parameters and the target pixel clock generated by the clock chip.

As an alternative embodiment, the signal processing apparatus may further include: the clock chip is used for receiving configuration information sent by the first processor, wherein the configuration information is generated by the first processor according to the clock frequency of the target pixel; and the clock chip is also used for generating a target pixel clock according to the target pixel clock frequency configured by the configuration information.

Example 3

According to the embodiment of the invention, the storage medium is also provided. Alternatively, in this embodiment, the storage medium may be configured to store the program code executed by the signal processing method provided in embodiment 1.

Optionally, in this embodiment, the storage medium may be located in any one of computer terminals in a computer terminal group in a computer network, or in any one of mobile terminals in a mobile terminal group.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS; determining a phase adjustment value according to the phase difference; and obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a phase adjustment value from the phase difference, comprising: and determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a phase adjustment value corresponding to the phase difference through a PID controller, comprising: setting a control coefficient of the PID controller, wherein the control coefficient comprises: a proportionality coefficient, an integral coefficient and a differential coefficient; and determining a phase adjustment value corresponding to the phase difference through the PID controller after setting the coefficient.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller, wherein the phase adjustment value comprises the following steps: determining a phase adjustment value corresponding to the phase difference by the following method:

incr _ phase = KP, fresh _ phase + KI, total _ phase + KD (fresh _ phase-last _ phase); the phase difference is set as fresh _ phase, the accumulated sum of fresh _ phase in the statistical historical adjustment times is set as total _ phase, last _ phase is the phase difference of the last adjustment, incr _ phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a frequency adjustment value according to the phase adjustment value; and obtaining the clock frequency of the target pixel according to the frequency adjustment value.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: obtaining a target pixel clock frequency according to the phase adjustment value, comprising: determining the percentage of the phase adjustment value in N frame periods, wherein N is a positive integer; a target pixel clock frequency is determined based on the current pixel clock frequency of the video signal, and the percentage.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a percentage of the phase adjustment value over the N frame periods by: incr _ freq _ percentage = incr _ phase/gen _ vs _ T, where incr _ freq _ percentage is a percentage, incr _ phase is a phase adjustment value, and gen _ vs _ T is N frame periods.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: determining a target pixel clock frequency from the current pixel clock frequency of the video signal, and the percentage, by: fresh _ freq = last _ freq (1 + incr _ freq _ percent), wherein, fresh _ freq is the target pixel clock frequency and last _ freq is the current pixel clock frequency.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: acquiring a phase difference between a first output field sync signal VS of a video signal and a reference field sync signal VS, comprising: receiving a phase difference sent by an FPGA chip of an editable logic gate array; or, receiving the first output VS and the reference VS through a phase detector, and obtaining a phase difference between the first output VS and the reference VS.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: after obtaining the target pixel clock frequency according to the frequency adjustment value, the method further includes: generating configuration information according to the clock frequency of the target pixel; and sending configuration information to the clock chip, wherein the configuration information is used for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: after sending the configuration information to the clock chip, the method further comprises the following steps: and sending the timing parameters of the video signal to a timing generator, wherein the timing parameters are used for generating a second output VS by the timing generator after being combined with a target pixel clock generated by a clock chip.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency is repeatedly performed in a frame period.

Optionally, in this embodiment, the storage medium is further configured to store program code for performing the following steps: before acquiring the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS, the method further comprises: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; in the case where the detection result is yes, determining to perform an operation of acquiring a phase difference between the first output VS of the video signal and the reference VS; and/or, in the case that the detection result is negative, returning to the operation of determining whether the periodic fluctuation of the reference VS is smaller than a predetermined fluctuation threshold.

Example 4

The embodiment of the invention can provide a computer terminal which can be any computer terminal device in a computer terminal group. Optionally, in this embodiment, the computer terminal may also be replaced with a terminal device such as a mobile terminal.

Optionally, in this embodiment, the computer terminal may be located in at least one network device of a plurality of network devices of a computer network.

In this embodiment, the computer terminal may execute program codes of the following steps in the signal processing method of the application program: acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS; determining a phase adjustment value according to the phase difference; and obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.

Alternatively, fig. 12 is a block diagram of a computer terminal according to an embodiment of the present invention. As shown in fig. 12, the computer terminal may include: one or more (only one shown) third processors 1202, memory 1204, and the like.

The memory 1204 may be used to store software programs and modules, such as program instructions/modules corresponding to the signal processing method and apparatus in the embodiments of the present invention, and the third processor 1202 executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implementing the above-described testing method for the internet of things. The memory may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include memory remotely located from the third processor, and the remote memory may be connected to the computer terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The third processor may call the information and the application program stored in the memory through the transmission device to perform the following steps: acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS; determining a phase adjustment value according to the phase difference; and obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.

Optionally, the third processor may further execute the program code of the following steps: determining a phase adjustment value from the phase difference, comprising: and determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller.

Optionally, the third processor may further execute the program code of the following steps: determining a phase adjustment value corresponding to the phase difference through a PID controller, including: setting a control coefficient of the PID controller, wherein the control coefficient comprises: a proportionality coefficient, an integral coefficient and a differential coefficient; and determining a phase adjustment value corresponding to the phase difference through the PID controller after the coefficient is set.

Optionally, the third processor may further execute the program code of the following steps: determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller, wherein the phase adjustment value comprises the following steps: determining a phase adjustment value corresponding to the phase difference by the following method:

Optionally, the third processor may further execute the program code of the following steps: determining a frequency adjustment value according to the phase adjustment value; and obtaining the clock frequency of the target pixel according to the frequency adjustment value.

Optionally, the third processor may further execute the program code of the following steps: obtaining a target pixel clock frequency according to the phase adjustment value, comprising: determining the percentage of the phase adjustment value in N frame periods, wherein N is a positive integer; a target pixel clock frequency is determined based on the current pixel clock frequency of the video signal, and the percentage.

Optionally, the third processor may further execute the program code of the following steps: determining a percentage of the phase adjustment value over the N frame periods by: incr _ freq _ percentage = incr _ phase/gen _ vs _ T, where incr _ freq _ percentage is a percentage, incr _ phase is a phase adjustment value, and gen _ vs _ T is N frame periods.

Optionally, the third processor may further execute the program code of the following steps: determining a target pixel clock frequency from the current pixel clock frequency of the video signal, and the percentage, by: fresh _ freq = last _ freq (1 + incr _ freq _ percent), wherein, fresh _ freq is the target pixel clock frequency and last _ freq is the current pixel clock frequency.

Optionally, the third processor may further execute the following steps: acquiring a phase difference between a first output field sync signal VS of a video signal and a reference field sync signal VS, comprising: receiving a phase difference sent by an FPGA chip of an editable logic gate array; or, receiving the first output VS and the reference VS through a phase detector, and obtaining a phase difference between the first output VS and the reference VS.

Optionally, the third processor may further execute the program code of the following steps: after obtaining the target pixel clock frequency according to the frequency adjustment value, the method further includes: generating configuration information according to the clock frequency of the target pixel; and sending configuration information to the clock chip, wherein the configuration information is used for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency.

Optionally, the third processor may further execute the following steps: after sending the configuration information to the clock chip, the method further comprises the following steps: and sending the timing parameters of the video signal to a timing generator, wherein the timing parameters are used for generating a second output VS by the timing generator after being combined with a target pixel clock generated by a clock chip.

Optionally, the third processor may further execute the program code of the following steps: the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency is repeatedly performed in a frame period.

Optionally, the third processor may further execute the program code of the following steps: before acquiring the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS, the method further comprises: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; in the case where the detection result is yes, determining to perform an operation of acquiring a phase difference between the first output VS of the video signal and the reference VS; and/or, in the case that the detection result is negative, returning to the operation of determining whether the periodic fluctuation of the reference VS is smaller than a predetermined fluctuation threshold.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technical content can be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

A signal processing method, comprising:

acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS;

determining a phase adjustment value according to the phase difference;

and obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.
The method of claim 1, wherein determining a phase adjustment value from the phase difference comprises:

and determining a phase adjustment value corresponding to the phase difference through a Proportional Integral Derivative (PID) controller.
The method of claim 2, wherein determining, by the PID controller, a phase adjustment value corresponding to the phase difference comprises:

setting a control coefficient of the PID controller, wherein the control coefficient comprises: a proportionality coefficient, an integral coefficient and a differential coefficient;

and determining a phase adjustment value corresponding to the phase difference through the PID controller after setting the coefficient.
The method according to claim 2 or 3, wherein the determining a phase adjustment value corresponding to the phase difference by a proportional-integral-derivative PID controller comprises:

determining a phase adjustment value corresponding to the phase difference by:

incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；

wherein, fresh _ phase is the phase difference, total _ phase is the accumulated sum of fresh _ phase within the counted historical adjustment times, last _ phase is the phase difference of the last adjustment of the current adjustment, incr _ phase is the phase adjustment value, KP is the proportionality coefficient, KI is the integral coefficient, and KD is the differential coefficient.
The method of claim 1, wherein obtaining a target pixel clock frequency based on the phase adjustment value comprises:

determining a frequency adjustment value according to the phase adjustment value;

and obtaining the clock frequency of the target pixel according to the frequency adjustment value.
The method of claim 1, wherein obtaining a target pixel clock frequency based on the phase adjustment value comprises:

determining a percentage of the phase adjustment value in N frame periods, wherein N is a positive integer;

determining the target pixel clock frequency according to the current pixel clock frequency of the video signal and the percentage.
The method of claim 6, wherein the phase adjustment value is determined as a percentage of N frame periods by:

incr_freq_percent＝incr_phase/gen_vs_T，

wherein incr _ freq _ percent is the percentage, incr _ phase is the phase adjustment value, and gen _ vs _ T is the N frame periods.
The method of claim 7, wherein the target pixel clock frequency is determined from a current pixel clock frequency of the video signal and the percentage by:

fresh_freq＝last_freq*(1+incr_freq_percent)，

wherein, fresh _ freq is the target pixel clock frequency, and last _ freq is the current pixel clock frequency.
The method of claim 1, wherein said obtaining a phase difference between a first output field sync signal VS of the video signal and a reference field sync signal VS comprises:

receiving the phase difference sent by an FPGA chip; or

Receiving the first output VS and the reference VS through a phase detector, and obtaining the phase difference between the first output VS and the reference VS.
The method of claim 1, further comprising, after obtaining a target pixel clock frequency according to the frequency adjustment value:

generating configuration information according to the target pixel clock frequency;

and sending the configuration information to a clock chip, wherein the configuration information is used for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency.
The method of claim 10, after said sending said configuration information to said clock chip, further comprising:

and sending the timing parameter of the video signal to a timing generator, wherein the timing parameter is used for generating the second output VS by the timing generator after being combined with a target pixel clock generated by the clock chip.
The method according to any one of claims 1 to 11, wherein the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency is repeatedly performed in a frame period.
The method of claim 12, further comprising, prior to said obtaining a phase difference between a first output field sync signal VS of the video signal and a reference field sync signal VS:

determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold;

in the case that the detection result is yes, determining to perform an operation of acquiring the phase difference between a first output VS of the video signal and the reference VS; and/or, in the case that the detection result is negative, returning to the operation of determining whether the periodic fluctuation of the reference VS is smaller than a predetermined fluctuation threshold.
A signal processing apparatus, characterized by comprising:

the acquisition module is used for acquiring a phase difference between a first output field synchronizing signal VS of the video signal and a reference field synchronizing signal VS;

the determining module is used for determining a phase adjustment value according to the phase difference;

and the processing module is used for obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used for generating a second output VS of the video signal.
A signal processing apparatus characterized by comprising: a first processor for executing a program, wherein the program is executed to perform the signal processing method of any one of claims 1 to 13.
The apparatus of claim 15, further comprising: a second processor, wherein the second processor is configured to determine the phase difference between the first output VS of the video signal and the reference VS and send the phase difference to the first processor.
The apparatus of claim 16, wherein the second processor comprises: a phase detector and a timing generator, wherein,

the phase detector is configured to receive inputs of the first output VS and the reference VS, and output the phase difference between the first output VS and the reference VS;

and the timing generator is used for receiving the timing parameters of the video signals sent by the processor and generating the second output VS according to the timing parameters and the target pixel clock generated by the clock chip.
The apparatus of claim 17, further comprising: the clock chip is configured to receive configuration information sent by the first processor, where the configuration information is generated by the first processor according to the target pixel clock frequency; the clock chip is further configured to generate a target pixel clock according to the target pixel clock frequency configured by the configuration information.
A storage medium, characterized in that the storage medium includes a stored program, wherein, when the program is executed, a device in which the storage medium is located is controlled to execute the signal processing method according to any one of claims 1 to 13.
A computer device, comprising: a memory and a third processor, wherein the first processor is connected to the memory,

the memory stores a computer program;

the third processor is configured to execute a computer program stored in the memory, and the computer program is executed to cause the third processor to execute the signal processing method according to any one of claims 1 to 13.