JPH05129583A - Charge transfer device and manufacture thereof - Google Patents
Charge transfer device and manufacture thereofInfo
- Publication number
- JPH05129583A JPH05129583A JP3288445A JP28844591A JPH05129583A JP H05129583 A JPH05129583 A JP H05129583A JP 3288445 A JP3288445 A JP 3288445A JP 28844591 A JP28844591 A JP 28844591A JP H05129583 A JPH05129583 A JP H05129583A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- film
- gate electrode
- charge transfer
- transfer device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高速転送CCD等の電
荷転送装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device such as a high speed transfer CCD and a method for manufacturing the same.
【0002】[0002]
【従来の技術】図2は従来の電荷転送装置の電極部近傍
の断面図である。図2において、21は半導体基板、2
2は絶縁膜、23は第1層ポリシリコン電極、24はシ
リコン酸化膜、25は第2層ポリシリコン電極である。2. Description of the Related Art FIG. 2 is a sectional view of a conventional charge transfer device in the vicinity of an electrode portion. In FIG. 2, 21 is a semiconductor substrate, 2
Reference numeral 2 is an insulating film, 23 is a first-layer polysilicon electrode, 24 is a silicon oxide film, and 25 is a second-layer polysilicon electrode.
【0003】従来のCCDの電極は、作り易さおよび安
定性の面から、図に示す2層ポリシリコンのオーバーラ
ップ構造が用いられていた。これは、まずCCDの電極
形成という立場から見てみると、第1層ポリシリコン電
極23を選択的に形成した後、第1層ポリシリコン電極
23を酸化して、第1層ポリシリコン電極23の周りに
絶縁膜であるシリコン酸化膜24を形成する。次に、第
1層ポリシリコン電極23の間を埋めるように第2層ポ
リシリコン電極25を形成するものである。For the electrodes of a conventional CCD, an overlapping structure of two-layer polysilicon shown in the figure has been used in terms of easiness of production and stability. From the standpoint of forming the CCD electrodes, this is because the first-layer polysilicon electrode 23 is selectively formed and then the first-layer polysilicon electrode 23 is oxidized to form the first-layer polysilicon electrode 23. A silicon oxide film 24 which is an insulating film is formed around the. Next, the second-layer polysilicon electrode 25 is formed so as to fill the space between the first-layer polysilicon electrodes 23.
【0004】[0004]
【発明が解決しようとする課題】従来構造は、プロセス
的には安定に作成できるが、電極材料にポリシリコンを
使用しているため、電極の抵抗値を30Ω/□以下に下
げることは困難であり、高速転送の際のクロックの遅延
は避けられない。The conventional structure can be stably formed in terms of process, but since polysilicon is used as the electrode material, it is difficult to reduce the resistance value of the electrode to 30Ω / □ or less. Yes, a clock delay during high-speed transfer is unavoidable.
【0005】本発明は上記課題を解決するもので、高速
転送にも十分対応でき、しかもプロセス上実現が容易な
電荷転送装置を提供することを目的とする。The present invention solves the above problems, and an object of the present invention is to provide a charge transfer device which can sufficiently cope with high-speed transfer and is easy to realize in the process.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明の電荷転送装置は、単層のポリサイド電極で構
成され、電極間の短縮のためにそのポリサイド電極の側
壁にポリシリコンからなるサイドウォールを形成したも
のである。In order to achieve the above object, the charge transfer device of the present invention comprises a single layer polycide electrode, and the side wall of the polycide electrode is made of polysilicon in order to shorten the distance between the electrodes. The side wall is formed.
【0007】[0007]
【作用】上記の構成により、転送電極のシート抵抗は4
Ω/□以下となり、クロックの遅延は大幅に改善され
る。With the above structure, the sheet resistance of the transfer electrode is 4
It becomes less than Ω / □, and the clock delay is greatly improved.
【0008】[0008]
【実施例】本発明の一実施例を図1に基づいて説明す
る。図1において、図2の従来例と同一部分には同一番
号を付し、説明を省略する。すなわち本発明の特徴は半
導体基板21上に絶縁膜22を形成した後、ポリシリコ
ン膜1とシリサイド膜2を重ねたポリサイド膜よりなる
単層のゲート電極をパターン形成する。そのポリサイド
膜とポリサイド膜の間隔は、フォトリソグラフィーにお
けるパターン形成の最小寸法を用いる。例えばその寸法
を0.8μmとする。次に全面にポリシリコン膜を上記
寸法の約半分の0.4μm堆積した後、RIE(リアク
ティブイオンエッチング)法で全面エッチングし、ポリ
シリコン膜1とシリサイド膜2からなるポリサイド膜の
側壁にのみポリシリコンからなるサイドウォール3を残
す。最終仕上がりのポリサイド膜からなるゲート電極間
の寸法は、サイドウォール3の隙間で決定される。この
間隔は、CCDの転送効率を決定する上で非常に重要で
あり、従来構造では約0.2μm程度であり、この寸法
は上記製造方法においても十分対応可能である。また、
本発明による構造においては、ゲートが単層構造という
ことで、従来構造に比べると平坦性も良好で、後工程の
加工も容易となり素子の微細化にも対応しやすくなる。
しかも、ゲート材料そのものが光の透過を阻止するため
特にエリアセンサー等で問題となるスミアの抑制能力も
増大する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. In FIG. 1, the same parts as those of the conventional example of FIG. That is, the feature of the present invention is that after forming the insulating film 22 on the semiconductor substrate 21, a single-layer gate electrode made of a polycide film in which the polysilicon film 1 and the silicide film 2 are superposed is patterned. As the distance between the polycide film and the polycide film, the minimum dimension of pattern formation in photolithography is used. For example, the dimension is 0.8 μm. Then, a polysilicon film is deposited on the entire surface at a thickness of 0.4 μm, which is about half of the above size, and then the entire surface is etched by the RIE (reactive ion etching) method so that only the side wall of the polycide film including the polysilicon film 1 and the silicide film 2 is formed. The sidewall 3 made of polysilicon is left. The size of the final finished polycide film between the gate electrodes is determined by the gap between the sidewalls 3. This interval is very important in determining the transfer efficiency of the CCD, and is about 0.2 μm in the conventional structure, and this dimension is sufficiently compatible with the above manufacturing method. Also,
In the structure according to the present invention, since the gate has a single layer structure, the flatness is better than that of the conventional structure, the post-process can be easily processed, and the device can be easily miniaturized.
Moreover, since the gate material itself blocks the transmission of light, the ability to suppress smear, which is a problem especially in area sensors, is increased.
【0009】以上の実施例ではゲート電極としてポリシ
リコン膜1とシリサイド膜2を重ねたポリサイド膜で説
明したが、シリサイド膜を省いたポリシリコン膜のみで
も可能である。In the above embodiments, the polycide film in which the polysilicon film 1 and the silicide film 2 are overlapped has been described as the gate electrode, but it is also possible to use only the polysilicon film without the silicide film.
【0010】[0010]
【発明の効果】以上説明したように本発明によれば、半
導体基板上にパターン形成されたポリサイド膜からなる
単層のゲート電極と、そのゲート電極側壁に形成された
サイドウォールとを有する構成であるので、ゲート電極
の抵抗値を大幅に低減でき、高速運転に対応可能とし、
しかも構造的にシンプルで、平坦性もよく、またスミア
制御能力も向上させることができる電荷転送装置を提供
できる。As described above, according to the present invention, a single-layer gate electrode made of a polycide film patterned on a semiconductor substrate and a sidewall formed on the side wall of the gate electrode are provided. As a result, the resistance value of the gate electrode can be greatly reduced, enabling high-speed operation,
Moreover, it is possible to provide a charge transfer device that is structurally simple, has good flatness, and can improve smear control capability.
【図1】本発明の一実施例の電荷転送装置のゲート電極
近傍の断面図FIG. 1 is a cross-sectional view near a gate electrode of a charge transfer device according to an embodiment of the present invention.
【図2】従来の電荷転送装置のゲート電極近傍の断面図FIG. 2 is a sectional view of the vicinity of a gate electrode of a conventional charge transfer device.
1 ポリシリコン膜 2 シリサイド膜 3 サイドウォール 21 半導体基板 22 絶縁膜 1 Polysilicon Film 2 Silicide Film 3 Sidewall 21 Semiconductor Substrate 22 Insulating Film
Claims (3)
ターン形成されたポリシリコン膜とシリサイド膜を重ね
た単層のポリサイドゲート電極と、そのポリサイドゲー
ト電極側壁に形成されたポリシリコンからなるサイドウ
ォールとを少なくとも有することを特徴とする電荷転送
装置。1. A single-layer polycide gate electrode formed by stacking a patterned polysilicon film and a silicide film on a semiconductor substrate that has been subjected to a predetermined process, and polysilicon formed on a sidewall of the polycide gate electrode. And a sidewall including at least.
単層のポリサイドゲート電極に代えて、ポリシリコンゲ
ート電極としたことを特徴とする請求項1記載の電荷転
送装置。2. The charge transfer device according to claim 1, wherein a polysilicon gate electrode is used in place of the single-layer polycide gate electrode in which the polysilicon film and the silicide film are stacked.
リシリコン膜またはポリサイド膜からなるゲート電極を
パターン形成する工程と、そのゲート電極を含む前記半
導体基板上にポリシリコンを形成する工程と、そのポリ
シリコンをエッチバックすることにより前記ゲート電極
の側壁にのみ選択的にポリシリコンを残す工程とを少な
くとも有することを特徴とする電荷転送装置の製造方
法。3. A step of patterning a gate electrode made of a polysilicon film or a polycide film on a semiconductor substrate which has been subjected to a predetermined process, and a step of forming polysilicon on the semiconductor substrate including the gate electrode. And a step of selectively leaving the polysilicon only on the side wall of the gate electrode by etching back the polysilicon, the method for manufacturing a charge transfer device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3288445A JPH05129583A (en) | 1991-11-05 | 1991-11-05 | Charge transfer device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3288445A JPH05129583A (en) | 1991-11-05 | 1991-11-05 | Charge transfer device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05129583A true JPH05129583A (en) | 1993-05-25 |
Family
ID=17730305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3288445A Pending JPH05129583A (en) | 1991-11-05 | 1991-11-05 | Charge transfer device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05129583A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7420235B2 (en) | 2005-08-09 | 2008-09-02 | Fujifilm Corporation | Solid-state imaging device and method for producing the same |
US7795654B2 (en) | 2005-08-09 | 2010-09-14 | Fujifilm Corporation | Solid-state imaging device and method for producing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05114617A (en) * | 1991-10-21 | 1993-05-07 | Oki Electric Ind Co Ltd | Charge coupled element |
-
1991
- 1991-11-05 JP JP3288445A patent/JPH05129583A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05114617A (en) * | 1991-10-21 | 1993-05-07 | Oki Electric Ind Co Ltd | Charge coupled element |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7420235B2 (en) | 2005-08-09 | 2008-09-02 | Fujifilm Corporation | Solid-state imaging device and method for producing the same |
US7772017B2 (en) | 2005-08-09 | 2010-08-10 | Fujifilm Corporation | Method of producing a solid state imaging device including using a metal oxide etching stopper |
US7795654B2 (en) | 2005-08-09 | 2010-09-14 | Fujifilm Corporation | Solid-state imaging device and method for producing the same |
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