TW508718B - Manufacturing method of analog capacitor for mixed type integrated circuit - Google Patents

Abstract

A kind of method for manufacturing analog capacitor of mixed type integrated circuit is disclosed in the present invention. The better procedures conducted are described in the following. The first dielectric layer is deposited on a semiconductor substrate and is followed by forming the bottom electrode of the analog capacitor on the first dielectric layer. A capacitance dielectric layer is then deposited on the first dielectric layer and the bottom electrode. The capacitance dielectric layer and the first dielectric layer are patterned to form an opening so as to expose the active region of the semiconductor substrate. A silicon epi-layer is then deposited to fill up the opening and is followed by conducting a thermal oxidization process to form a gate oxide on the silicon epi-layer surface. The first conducting layer is deposited on the gate oxide layer and the capacitance dielectric-layer, and is patterned to form the gate and the upper electrode of the analog capacitor. Thus, the analog capacitor is completed.

Description

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CC A7 __________B7 V. Description of the Invention (/) '(I) Field of Invention ... The present invention relates to a method of manufacturing a capacitor of the age of a hybrid integrated circuit, especially a capacitor which can provide a flat analog capacitor (analogcapaci㈣). System Method 0 (1) Description of Conventional Technology: An analog digital hybrid integrated circuit (Anabg / Digital Mixed_ MQde needs to produce an accurate capacitor voltage coefficient (voltage

Coefficient of Capacitor (VCC), especially when, when the structure of electrical components is increasingly miniaturized (Shnnk) and enters the sub-micron or deep sub-micron technology field, [analog produced by traditional process technology [Capacitor voltage coefficient] of analog capacitors is more difficult to grasp. Therefore, the reproduction and improvement of product f have become urgent problems for the industry. ~ Conventional hybrid capacitor manufacturing method, such as the first patented polycrystalline silicon layer 4 is deposited on the semiconductor substrate 3 of the interlayer oxide layer 2 of the U.S. patent. As shown in Fig. 1 β: 'A photoresist layer 5 is formed on the surface of the first-multicrystalite layer 4. As shown in FIG. 1c, with the photoresist layer 5 as an etching mask, the first polycrystalline silicon layer 4 is etched to form the gate electrode 4a and the lower electrode of the capacitor. After forming a gap wall 6 between the gate 4a and the side wall at the lower electrode, a method of ion implantation is applied to form a source / drain 7 on the semiconductor substrate 3 on both sides of the gate surface. As shown in FIG.-D, a first insulating layer 8 and a second polycrystalline silicon layer 9 are sequentially deposited. As shown in FIG. 1E, the second polycrystalline silicon layer 9 above the lower electrode 4b is a 9-inch Zhangjia Standard (CNS) A4 specification (21GX297 mm factory ------- 2 I ---- ------ ,, (Please read > i: Issue on the back before filling in this page} Order S, Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 A7 Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The invention description (the upper electrode of the wool capacitor, analogy capacitor K) is completed. The method composed of the lower electrode 4b and the upper electrode 9b uses f-know-type capacitors such as wiring, lithography, and other processes. Japan: The substrate surface is extremely uneven, which is not easy, and the manufacturing process becomes more difficult, and the quality control number is not changed: the capacitor voltage system of the capacitor loses the market's reproducibility, and It will make the quality of the product impossible to improve, brothers, and other competitors after the loss. (2) Brief description of the invention: 1 The main purpose of 2Θ is to provide a kind of hybrid integrated circuit, which is analogous to the electric valley. Manufactured ridge-tank-specific capacitor H (anabgeapacitor). The analog capacitor system of the integrated circuit is used to increase the accuracy of the control of the capacitor voltage wire. -The purpose of the present invention is to provide a hybrid analog circuit of the integrated circuit, which is a manufacturing method to simplify the manufacturing process and reduce costs. In order to achieve the above object, the invention proposes a method for manufacturing an analog capacitor of a hybrid integrated circuit. The preferred implementation steps are: depositing a first dielectric layer on a semiconductor substrate, and depositing the first dielectric layer on the semiconductor substrate. An analog capacitor lower electrode is formed, and then a capacitor dielectric layer is deposited on the first dielectric layer and the lower electrode, and a 4 capacitor dielectric layer and the first dielectric layer are patterned to form an opening, so that the semiconductor The active area of the substrate is exposed; epitaxiai silicon is deposited to fill the opening, and then a thermal oxidation process is performed. On the surface of the epitaxial silicon, the paper size applies the Chinese National Standard (CNS) M specification (no, 〆297 公 餐 —. ^ Order (please read the Italian notice on the back before filling in this page) 508718 Α7 Β7 Description of the five inventions == chemical layer, and then deposited-the-conductive layer is oxidized at the leisure electrode ~ electricity, and pattern Turn into The first conductive layer is to form a grid electrode and: as above, the analog capacitor is completed at this time. For a further explanation of the present invention, the detailed description of the invention is intended to enable your review committee to review The second (four) diagram is briefly explained: Fig. 1A and E are schematic diagrams of analog electric circuits of conventional hybrid integrated circuits. Figs. A to Η show the preferred embodiment of the present invention, and the schematic diagram of the hybrid specific capacitor manufacturing method. Description: 1 ~ field oxide 2 ~ gate oxide layer 3 ~ semiconductor substrate 4 ~ polycrystalline layer 4a ~ gate 4b ~ lower electrode 5 ~ photoresist layer 6 ~ spacer 7 ~ source / drain 8 ~ One insulation layer This paper size is applicable to Chinese National Standard (CNS) M specifications (21 × 297 mm)

7 8 ο 5 8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ('9 ~ Second polycrystalline silicon layer' 9b ~ Upper electrode 10 ~ Analog capacitor 11 ~ Semiconductor substrate 12 ~ First dielectric Layer 12a ~ Capacitance opening 13 ~ Capacitance conductive layer 13a ~ Lower electrode * 14 ~ Capacitance dielectric layer 15 ~ Opening 16 ~ Broken crystal 17 ~ Gate oxide layer 18 ~ First conductive layer 18a ~ Gate 18b ~ Upper electrode ( 5. Detailed description of the present invention: A hybrid integrated circuit analog capacitor manufacturing method, a preferred embodiment of which includes the following steps: (a) As shown in FIG. 2A, a first is deposited on a semiconductor substrate 11 The dielectric layer 12 is patterned to form a capacitor opening 12a, and the capacitor opening 12a does not expose the semiconductor substrate 11. (b) As shown in FIG. 2B, a capacitor conductive layer is further deposited. 13 to fill the capacitor opening 12a, where the conductive layer 13 of the capacitor contains at least poly-silicon, please read * Please fill in this page if you have any background information. F The paper size is subject to the Chinese National Standard (CNS) A4. Specifications (210X 297 mm) 508718 A7 B7 Wujing Shi Xi (US Slllcon), mixed metal shirt and other similar materials. ⑹ As shown in FIG. 2C, a time-of-day technology, such as chemical mechanical polishing (olisliing) π '·, is used to planarize the capacitor conductive layer 13' below the specific capacitance n, and then deposit-the capacitor dielectric layer 14 On the first dielectric layer 12 and the lower electrode 13a, a dielectric layer of an analog capacitor is used. The lower electrode 13a is of course the same as that of the materials and materials used, including at least polycrystalline silicon (pdy_silicOn), amorphous chopping (Yijia fertilizer s mountain con), silicidated metal (sillclde) and the like The first dielectric layer 12 includes at least one of nitride, dream dioxide, and other similar materials. As shown in Figure 2D, a photoresist layer is formed on the capacitor dielectric layer 14 and the photoresist layer is used as a side mask to perform photolithography m_ of the capacitor dielectric layer 14 and the first dielectric layer. 12 to form an opening 15 to expose an active area of the semiconductor substrate ^. "As shown in Fig. 2E", the re-deposited wormwood stone foundation fills the opening as a part of a conductive substrate of a transistor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 3, it is heated in an oxygen-containing environment to perform a thermal oxidation process, which forms the surface of Worm Crystal 16—the gate oxide layer 17. For the dream of dioxide. (g) As shown in FIG. 2G, a first-conducting layer 18 is re-deposited on the free-electrode oxidation and the capacitor dielectric layer 14, wherein the first conductive layer 18 includes at least crystalline silicon and amorphous stone. And similar materials such as polycrystalline metal (pdyside) and other similar materials 0 〆, the paper size applicable fiii " standard (CNS) A4 specifications (2l0x ^^ y B7 V. Description of the invention (G) ⑻ ^^ The analog capacitor of the hybrid integrated circuit can be completed without 'patterning the first to conductive layer 18 to form a gate electrode and a similar circuit.' This is the upper electrode of the capacitor. ⑽ 闲闲 极 18_ can be formed in the same step, and its surface profile is relatively flat. Without conventional technology, the surface profile is not flat due to extreme strictness, the accuracy of f manufacturing, and the increase in manufacturing process _ Lin disadvantages, 2 = It can confirm the reproducibility of the quality of the production system and its products, strengthen the competitive advantage of the market, and not be eliminated by the times. '... The formula and description of the present invention are described above in a preferred embodiment, which is easy to associate. Various t: such as making it similar or completing the previous process, etc. After understanding the spirit of the present invention, those skilled in the art can implement it. Therefore, the description of the preferred embodiment of the present invention is only used to help the Erjieshi invention to limit the spirit of the present invention without departing from the spirit of the present invention. In the area of "God of the Gods", it is possible to make a few changes and retouching and equivalent changes, without departing from the spirit and scope of the present invention. As mentioned above, the present invention has no related technical disclosure in the field of conventional technology. The technical content of the present invention can surely solve the problems in this field 'and the principle of the method is not easy to be completed based on the know-how. Its efficacy has been described in detail, it is progressive, and it has met the requirements of the Patent Law. Essentials of invention patents' I would like to ask your reviewing committee to review and grant the patent as a prayer.

Claims (1)

18 The range of I includes a composite capacitor manufacturing method of processing type integrated Wei. The steps include ---------------- --------------- 一 (Please read the precautions on the back before filling this page) (a ) Cold ^ Lifeline wire: a first dielectric layer 'on a Fengfeng conductor substrate and forming the lower electrode of an analog capacitor on the first dielectric cladding layer, ... (-) (b) depositing a capacitor dielectric layer on the first dielectric layer Two dielectric layers and (C) pattern the capacitor dielectric layer and the dielectric layer on the capacitor dielectric to form an opening so that the active area of the substrate is exposed; Xi (_ Butterfly SiUcon) fills the opening; performs a thermal oxidation process on the Lei s layer; 々, Θ Hao Ri-ri formed a gate oxide on the silicon surface (0 deposition ~ M ^ ^ ^ 订, ' ^ Layer on the gate oxide layer and the capacitor dielectric layer σ, transform a conductive layer to form a gate electrode and an analog capacitor electrode. ^ The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the patent scope of Rushen Patent. The analog Raguchi method of the hybrid integrated circuit according to item 1, wherein the step of forming the lower electrode in step (2) includes: ( U patterning the first dielectric layer to form a capacitor opening; (2) / pre-productive-a capacitor conductive layer to fill the capacitor opening; (3) flattening the capacitor conductive layer to form the lower electrode. 3 · An analog capacitor manufacturing method for a hybrid integrated circuit as described in the second item of the patent application, wherein the capacitor opening in step (1) does not expose the semiconductor substrate. 4. The hybrid as described in the second item of the patent application The paper of the integrated circuit; ^ 顾 ^ 国 ^^ 1 eight 4 secrets (inflated 29t! ¥ T A8 Βδ —— _____ C8 、 l, ′ --- D8 X, the scope of patent application-: one ^:-container manufacturing method , 豆 nr%. Α ', ^ lower pole contains at least one of polycrystalline silicon, amorphous silicon, and silicided metal. 5, = Please refer to the analog integrated circuit of the hybrid integrated circuit described in the patent scope. The first dielectric layer contains at least one of nitrogen cut and silicon dioxide. 6 The method of analog electric A 5 for the hybrid integrated circuit described in Patent Patent No. W, wherein the first conductive layer includes at least a complex crystal and an amorphous One of Shi Xi and polycrystalline silicide metal. 7. = Please mix as described in item 1 of patent scope An analog electric hybrid method of integrated circuit, in which the thermal oxidation process described in step (e) refers to heating in an oxygen-containing environment. 8. = of the hybrid integrated circuit described in item 丨 of the scope of patent application An analog capacitor manufacturing method, wherein the gate oxide layer is silicon dioxide. 9. An analog capacitor manufacturing method for a hybrid integrated circuit, the steps include: (a) depositing a first dielectric layer on a semiconductor substrate (B) patterning the first dielectric layer to form a capacitor opening; (c) depositing a capacitor conductive layer to fill the capacitor opening to form an analog capacitor as the lower electrode; (d) depositing a capacitor dielectric layer On the first dielectric layer and the lower electrode; (e) coating a photoresist layer and etching a portion of the capacitor dielectric layer and the first dielectric layer not covered by the photoresist layer to form a The opening exposes the active area of the semiconductor substrate; (f) Deposition of epitaxial silicon fills the opening; The paper m Standards (CNS) Α4 · (21QX297 public director)-( Please read the notes on the back before filling this page)-·! Order the Ministry of Economy Hui Property Office employees consumer cooperatives printed I process, forming on the surface of the Worm Crystal Dream-gate oxide (h)-product-the first conductive layer minus the gate oxide layer and the capacitor dielectric layer (1) pattern the first conductive layer to form Gate and analog capacitors: The method for manufacturing a hybrid integrated circuit described in item 10 of the patent application No. 11 of the patent application above, wherein the lower electrode includes at least a compound crystal: a metal. ^ Xi and Shi Xi u. = Scaling__Don't-like hybrid frequency circuit analog valley reading method, wherein the first dielectric layer contains at least one of nitride nitride and silicon dioxide. ‘12. The method of manufacturing an analog capacitor according to the hybrid integrated circuit as described in item 10 of the scope of the patent application ’, wherein the towel-conducting layer includes at least one of a compound, an amorphous stone, and a polycrystalline silicide metal. 13. An analog capacitor manufacturing method for a hybrid integrated circuit as described in item 10 of the scope of application for a patent, wherein the gate oxide layer is a silica. -Paper A4 \ p / S N C