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CC A7 __________B7 五、·發明説明(/ ) ' (一)發明領域·· ^ 本發明係有關-種混合式積體電路之齡電容器製 法,尤指-種可提供平坦的類比電容器(anal〇gcapaci㈣之製 法0 (一)習用技術的說明: 類比數位混合積體電路(Anabg/Digital Mixed_ MQde 需要製造一個具有準確的電容器電壓係數(voltageCC A7 __________B7 V. Description of the Invention (/) '(I) Field of Invention ... The present invention relates to a method of manufacturing a capacitor of the age of a hybrid integrated circuit, especially a capacitor which can provide a flat analog capacitor (analogcapaci㈣). System Method 0 (1) Description of Conventional Technology: An analog digital hybrid integrated circuit (Anabg / Digital Mixed_ MQde needs to produce an accurate capacitor voltage coefficient (voltage
Coefficient of Capacitor ; VCC)之類比電容器,尤其是當、當, 電性元件結構日益趨向小型化(Shnnk)而進入次微米或深次 微米的技術領域時,以傳統製程技術所製造出來的【類比數 ,混合,體電路】,其類比電容器的【電容器電壓係數】更 是不易掌握,故其再雛及品f的提升便成為產業界急於解 決的問題。 〜習知的混合式積體電路之類比電容器製法,如美國專利 間極氧化層2的半導體基板3上沈積第一複晶石夕層4。如圖一β 所:’在第-複晶石夕層4的表面形成光阻層5。如圖一c所示, 以光阻層5為蝕刻罩幕,對第一複晶矽層4進行蝕刻,形成閘 極4a與電容器的下電極处,再利用例如沈積二氧化秒層與回 蝕刻法在閘極4a與下電極处的側壁形成間隙壁6後,施以離子 佈植的程序,在閘極械面兩侧之半導體基板3上形成源極/ 汲極7。如圖—D所示,依序沈積第一絕緣層8和第二複晶矽 層9。如圖一E所示,於下電極4b上方位置的第二複晶矽層9 本·氏張家標準(CNS) A4規格(21GX297公釐厂 ------- 2 I----------,, (請先閲讀背面之>i:意事項再填寫本頁} 訂 S, 經濟部智慧財產局員工消費合作社印製 A7 A7 經濟部智慧財產局員工消費合作社印製 、發明説明( 毛成電容器的上電極此, 之類比電容器K)便完成。下電極4b和上電極9b所組成 法,,使用f知喊合式魏之電容哭f 佈線、微影餘刻等製程日士,:基板衣面極為不平整,於 不易,且對於、、Η人々才k成製程困難度增加,品質控制 數更是不轉:電容器的電容器電壓係 而失去市場的㈣再現性,也將使產品品質無法提升, 兄f饭勢,洛後其他競爭對手。 (二)發明之簡要說明: 一2 Θ之主要目的為提供—種混合式積體電路之類比電 谷的衣^ ’以製造岭坦醜比電容H(anabgeapacitor)。 六龟月之再目的為提供一種混合式積體電路之類比電 容器製=,以增加對電容器電壓絲控制的精確度。 —本發明之再—目的為提供-種混合式積體電路之類比電 各為製法,以簡化製程、降低成本。 帝本發明為達上述目的,故提出一種混合式積體電路之類 比電容器製法,其較佳實施步驟係為··於一半導體基板上沈 積第一介電層,並於該第一介電層形成類比電容器之下電 極’再沈積一電容介電層於該第一介電層和該下電極上,並 圖案化4電容介電層和該第—介電層以形成—開口,使該半 導體基板的主動區(active area)露出;沈積磊晶矽(epitaxiai silicon)填滿该開口,接著進行熱氧化製程,於該磊晶矽表面 本紙張尺度適用中國國家標準(CNS) M規格(no、〆297公餐 — . ^ 訂 (請先閲讀背面之€意事項再填寫本頁〕 508718 Α7 Β7 五 發明説明 ==化層,再沈積-第-導電層於該閑極氧化~ 電,並圖案化該第—導電層以形成閣極和: 如上兒極’此時類比電容器便完成。 、 為進-步對本發明有更深人的說明,乃藉由以 發明詳細說明,冀能對貴審查委員於審二 (四)圖式簡要說明: 圖一A芏E為習用的混合式積體電路之類比電 不意圖。 图—A至Η為本發明較佳實施例,混合式 比電容器製法示意圖。 圖號說明: 1〜場氧化物 2〜閘極氧化層 3〜半導體基板 4〜複晶珍層 4a〜閘極 4b〜下電極 5〜光阻層 6〜間隙壁 7〜源極/汲極 8〜第一絕緣層 本紙張尺度適用中國國家標準(CNS ) Μ規格(21〇X297公釐) 容器製法 路之類 積體電Coefficient of Capacitor (VCC), especially when, when the structure of electrical components is increasingly miniaturized (Shnnk) and enters the sub-micron or deep sub-micron technology field, [analog produced by traditional process technology [Capacitor voltage coefficient] of analog capacitors is more difficult to grasp. Therefore, the reproduction and improvement of product f have become urgent problems for the industry. ~ Conventional hybrid capacitor manufacturing method, such as the first patented polycrystalline silicon layer 4 is deposited on the semiconductor substrate 3 of the interlayer oxide layer 2 of the U.S. patent. As shown in Fig. 1 β: 'A photoresist layer 5 is formed on the surface of the first-multicrystalite layer 4. As shown in FIG. 1c, with the photoresist layer 5 as an etching mask, the first polycrystalline silicon layer 4 is etched to form the gate electrode 4a and the lower electrode of the capacitor. After forming a gap wall 6 between the gate 4a and the side wall at the lower electrode, a method of ion implantation is applied to form a source / drain 7 on the semiconductor substrate 3 on both sides of the gate surface. As shown in FIG.-D, a first insulating layer 8 and a second polycrystalline silicon layer 9 are sequentially deposited. As shown in FIG. 1E, the second polycrystalline silicon layer 9 above the lower electrode 4b is a 9-inch Zhangjia Standard (CNS) A4 specification (21GX297 mm factory ------- 2 I ---- ------ ,, (Please read > i: Issue on the back before filling in this page} Order S, Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 A7 Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The invention description (the upper electrode of the wool capacitor, analogy capacitor K) is completed. The method composed of the lower electrode 4b and the upper electrode 9b uses f-know-type capacitors such as wiring, lithography, and other processes. Japan: The substrate surface is extremely uneven, which is not easy, and the manufacturing process becomes more difficult, and the quality control number is not changed: the capacitor voltage system of the capacitor loses the market's reproducibility, and It will make the quality of the product impossible to improve, brothers, and other competitors after the loss. (2) Brief description of the invention: 1 The main purpose of 2Θ is to provide a kind of hybrid integrated circuit, which is analogous to the electric valley. Manufactured ridge-tank-specific capacitor H (anabgeapacitor). The analog capacitor system of the integrated circuit is used to increase the accuracy of the control of the capacitor voltage wire. -The purpose of the present invention is to provide a hybrid analog circuit of the integrated circuit, which is a manufacturing method to simplify the manufacturing process and reduce costs. In order to achieve the above object, the invention proposes a method for manufacturing an analog capacitor of a hybrid integrated circuit. The preferred implementation steps are: depositing a first dielectric layer on a semiconductor substrate, and depositing the first dielectric layer on the semiconductor substrate. An analog capacitor lower electrode is formed, and then a capacitor dielectric layer is deposited on the first dielectric layer and the lower electrode, and a 4 capacitor dielectric layer and the first dielectric layer are patterned to form an opening, so that the semiconductor The active area of the substrate is exposed; epitaxiai silicon is deposited to fill the opening, and then a thermal oxidation process is performed. On the surface of the epitaxial silicon, the paper size applies the Chinese National Standard (CNS) M specification (no, 〆297 公 餐 —. ^ Order (please read the Italian notice on the back before filling in this page) 508718 Α7 Β7 Description of the five inventions == chemical layer, and then deposited-the-conductive layer is oxidized at the leisure electrode ~ electricity, and pattern Turn into The first conductive layer is to form a grid electrode and: as above, the analog capacitor is completed at this time. For a further explanation of the present invention, the detailed description of the invention is intended to enable your review committee to review The second (four) diagram is briefly explained: Fig. 1A and E are schematic diagrams of analog electric circuits of conventional hybrid integrated circuits. Figs. A to Η show the preferred embodiment of the present invention, and the schematic diagram of the hybrid specific capacitor manufacturing method. Description: 1 ~ field oxide 2 ~ gate oxide layer 3 ~ semiconductor substrate 4 ~ polycrystalline layer 4a ~ gate 4b ~ lower electrode 5 ~ photoresist layer 6 ~ spacer 7 ~ source / drain 8 ~ One insulation layer This paper size is applicable to Chinese National Standard (CNS) M specifications (21 × 297 mm)
7 8 ο 5 8 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明(‘ 9〜第二複晶矽層 ‘ 9b〜上電極 10〜類比電容器 11〜半導體基板 12〜第一介電層 12a〜電容開口 13〜電容導電層 13a〜下電極 * 14〜電容介電層 15〜開口 16〜蟲晶碎 17〜閘極氧化層 18〜第一導電層 18a〜閘極 18b〜上電極 (五)本發明之詳細描述: 一種混合式積體電路之類比電容器製法,其較佳實施例 係包括以下之步驟: (a) 如圖二A所示,於一半導體基板11上沈積一第一介電層 12,並圖案化該第一介電層12以形成一電容開口 12a,且 電容開口 12a係未使半導體基板11露出。 (b) 如圖二B所示,再沈積一電容導電層13以填滿該電容開口 12a,其中電容導電層13至少包含複晶石夕(poly-silicon)、非 請 閲 讀* 背 意 事 項 再 填 寫 本 頁 f 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 508718 A7 B7 五 晶 石夕(麵幽US Slllcon)、雜金屬㈣恤)等相類似材料 其中一種。 ⑹如圖二C所示,使时坦化技術,例如:化學機械研磨法 olisliing) π'· ,將電容導電層13平坦 化’⑽細比電容n之下,再沈積—電容介電 層14於第-介電層12和下電極13a上,作為類比電容器的 介電層。其中下電極13a當然與電料電和所使用的材 料-致,至少包含複晶石夕(pdy_silic〇n)、非晶砍(議伽肥 s山con)、矽化金屬(sillclde)等相類似材料其中一種;該第 -介電層12至少包含氮化,二氧化梦及其它類似材料其 中一種。 、 ⑹如圖二D所示’於電容介電層14上形成光阻層,並利用利 用光阻層為侧罩幕,進行微影勤m _化電容介電層 14和第-介電層12,以形成一開口15,使該半導體基板^ 的主動區(active area)露出。 ⑹如圖二E所示’再沈積蟲晶石夕础㈣填滿該開 口,作為電晶體(transistor)的導電基底的部分。 經濟部智慧財產局員工消費合作社印製 ⑴如圖3所示,於含氧之環境下加熱,以進行熱氧化製程, 使蟲晶梦16表面形成—閘極氧化層17,該_氧化初 係為二氧化梦。 (g)如圖二G所示,再沈積—第—導電層18於該閑極氧化和 和該電容介電層14上,其中該第一導電層18至少包含^晶 矽、非晶石夕及多晶石夕化金屬(pdyside)等相類似材料其中一 種0 〆、 表紙張尺度適用fiii"標準(CNS ) A4規格(2l〇x^^y B7 五、發明説明(G ) ⑻^^所不’圖案化第~導電層18以形成閘極咖和類 私奋為之上弘極⑽’如此混合式積體電路之類比電容 益便完成。 本發·合式频電路之_電容器的上電極⑽盎閑 極18_可於同—步驟形成’且其表面輪廓較為平整,沒有習 用技術會因極為嚴制表面輪廓不平整, f製辦的精準度,及增加造成製程_麟缺點,2 =月可確貝彳工制叩質及其產品的再現性,加強市場的競爭優 勢,不被時代所淘汰。 ’· …本發明之®式與描述以較佳實施例說明如上,容易聯想 ^卜諸t:諸如使職它相類似之㈣或完成前製程之i 私不同等等,热悉此領域技藝者於領悟本發明之精神後,皆 可^到芰化實施之,故本發明較佳實施例之說明僅用於幫助 二解士發明以限定本發明之精神,在不脫離本發明之 知神圍内’當可作些許更動潤飾及同等之變化替換,其亦 不脫離本發明之精神和範圍。 币綜上所述,本發明於習知技術領域上無相關之技術揭 已具新穎性;本發明之技術内容可確實解決該領域之問 題’且方法原理屬非根據習知技藝而易於完成者,其功效性 業已經详述,實具進步性,誠已符合專利法中所規定之發明 專利要件’謹請貴審查委員惠予審視,並賜准專利為禱。7 8 ο 5 8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ('9 ~ Second polycrystalline silicon layer' 9b ~ Upper electrode 10 ~ Analog capacitor 11 ~ Semiconductor substrate 12 ~ First dielectric Layer 12a ~ Capacitance opening 13 ~ Capacitance conductive layer 13a ~ Lower electrode * 14 ~ Capacitance dielectric layer 15 ~ Opening 16 ~ Broken crystal 17 ~ Gate oxide layer 18 ~ First conductive layer 18a ~ Gate 18b ~ Upper electrode ( 5. Detailed description of the present invention: A hybrid integrated circuit analog capacitor manufacturing method, a preferred embodiment of which includes the following steps: (a) As shown in FIG. 2A, a first is deposited on a semiconductor substrate 11 The dielectric layer 12 is patterned to form a capacitor opening 12a, and the capacitor opening 12a does not expose the semiconductor substrate 11. (b) As shown in FIG. 2B, a capacitor conductive layer is further deposited. 13 to fill the capacitor opening 12a, where the conductive layer 13 of the capacitor contains at least poly-silicon, please read * Please fill in this page if you have any background information. F The paper size is subject to the Chinese National Standard (CNS) A4. Specifications (210X 297 mm) 508718 A7 B7 Wujing Shi Xi (US Slllcon), mixed metal shirt and other similar materials. ⑹ As shown in FIG. 2C, a time-of-day technology, such as chemical mechanical polishing (olisliing) π '·, is used to planarize the capacitor conductive layer 13' below the specific capacitance n, and then deposit-the capacitor dielectric layer 14 On the first dielectric layer 12 and the lower electrode 13a, a dielectric layer of an analog capacitor is used. The lower electrode 13a is of course the same as that of the materials and materials used, including at least polycrystalline silicon (pdy_silicOn), amorphous chopping (Yijia fertilizer s mountain con), silicidated metal (sillclde) and the like The first dielectric layer 12 includes at least one of nitride, dream dioxide, and other similar materials. As shown in Figure 2D, a photoresist layer is formed on the capacitor dielectric layer 14 and the photoresist layer is used as a side mask to perform photolithography m_ of the capacitor dielectric layer 14 and the first dielectric layer. 12 to form an opening 15 to expose an active area of the semiconductor substrate ^. "As shown in Fig. 2E", the re-deposited wormwood stone foundation fills the opening as a part of a conductive substrate of a transistor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 3, it is heated in an oxygen-containing environment to perform a thermal oxidation process, which forms the surface of Worm Crystal 16—the gate oxide layer 17. For the dream of dioxide. (g) As shown in FIG. 2G, a first-conducting layer 18 is re-deposited on the free-electrode oxidation and the capacitor dielectric layer 14, wherein the first conductive layer 18 includes at least crystalline silicon and amorphous stone. And similar materials such as polycrystalline metal (pdyside) and other similar materials 0 〆, the paper size applicable fiii " standard (CNS) A4 specifications (2l0x ^^ y B7 V. Description of the invention (G) ⑻ ^^ The analog capacitor of the hybrid integrated circuit can be completed without 'patterning the first to conductive layer 18 to form a gate electrode and a similar circuit.' This is the upper electrode of the capacitor. ⑽ 闲闲 极 18_ can be formed in the same step, and its surface profile is relatively flat. Without conventional technology, the surface profile is not flat due to extreme strictness, the accuracy of f manufacturing, and the increase in manufacturing process _ Lin disadvantages, 2 = It can confirm the reproducibility of the quality of the production system and its products, strengthen the competitive advantage of the market, and not be eliminated by the times. '... The formula and description of the present invention are described above in a preferred embodiment, which is easy to associate. Various t: such as making it similar or completing the previous process, etc. After understanding the spirit of the present invention, those skilled in the art can implement it. Therefore, the description of the preferred embodiment of the present invention is only used to help the Erjieshi invention to limit the spirit of the present invention without departing from the spirit of the present invention. In the area of "God of the Gods", it is possible to make a few changes and retouching and equivalent changes, without departing from the spirit and scope of the present invention. As mentioned above, the present invention has no related technical disclosure in the field of conventional technology. The technical content of the present invention can surely solve the problems in this field 'and the principle of the method is not easy to be completed based on the know-how. Its efficacy has been described in detail, it is progressive, and it has met the requirements of the Patent Law. Essentials of invention patents' I would like to ask your reviewing committee to review and grant the patent as a prayer.