JPH1187505A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which forms stable fine contact pillars, having a high aspect ratio for reducing damages to the source-drain layer of a MOSFET. SOLUTION: This manufacturing method has a passivation film 109 formed on an Si substrate 101 having a diffusion layer 103 and a gate, forming pillar holes 110 through the passivation film 109, forming a conductor film 107 in the holes 110 and on the passivation film 109, etching the conductor film 107 to form contact pillars 111 having bases in the pillar holes, removing the conductor film 107, forming a layer insulation film 106 on the passivation film 109, removing the insulation film 106 until the tops of the pillars appear, and forming a wiring to be connected to the pillars 111 on the insulation film 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a contact pillar, and more particularly, to a MOSFET.
And a method of manufacturing a semiconductor device having a contact pillar used for a multilayer wiring structure.

[0002]

2. Description of the Related Art Conventionally, a method of forming a contact pillar of a semiconductor device is roughly divided into a method of forming a contact pillar by providing a pillar hole in an insulating film and embedding a conductor film in the pillar hole, and a method of forming a contact pillar. To form a contact pillar by etching.

FIG. 7 shows a conventional M-type using pillar holes.
It is sectional drawing which shows the process of the formation method of the contact pillar of OSFET, (a) is the state in which the diffusion layer, the gate oxide film, and the passivation film were formed in the silicon substrate, (b)
Is a state where a pillar hole is formed in an insulating film laminated on the upper surface, (c) is a state where a conductor film is embedded in the pillar hole,
(D) shows a state in which the contact pillar is formed by polishing the conductive film. In the figure, reference numeral 701 denotes a silicon substrate, 702 denotes a trench element isolation, 703 denotes a diffusion layer, 704 denotes a gate oxide film, 705 denotes a gate polysilicon, 706 denotes an interlayer insulating film, 706 denotes a conductive film, 707 denotes a passivation film, and 71 denotes a passivation film.
0 is a pillar hole, and 711 is a contact pillar.

In the step of FIG. 7A, a silicon substrate 70 is formed.
1 is etched to a predetermined depth, for example, 0.5 μm to form a trench, and HTO (High T
A silicon oxide film formed by thermal oxidation (high-temperature thermal oxidation) or the like is buried, and the oxide film is polished to leave only the oxide film in the trench.
02 is formed. Thereafter, impurities are implanted into the source / drain formation positions to a depth of, for example, about 0.02 to 0.2 μm, and heat treatment such as RTA or hydrogen annealing is performed to recrystallize the diffusion layer 703. Next, the gate oxide film 704 and the polysilicon 705 are laminated on the entire surface, and the gate oxide film 704 and the polysilicon 705 are etched into a desired gate shape by dry etching. Next, a passivation film 709 is formed on the entire surface and etched back to form a sidewall on the gate made of the gate oxide film 704 and the polysilicon 705. Thereafter, a conductive film is formed on the entire surface, and the gate and the diffusion layer 703 are silicided,
The conductor film is removed (not shown).

In the step of FIG. 7B, an interlayer insulating film 706 is formed.
Is formed on the entire surface, and a pillar hole 710 is opened in the formed interlayer insulating film 706 until it reaches the source / drain diffusion layer.

In the step of FIG. 7C, the conductor film 70 is formed over the entire surface.
7, and the conductor film 707 is embedded in the pillar hole 710.

In the step of FIG. 7D, the conductor film 707 on the interlayer insulating film 706 is removed by polishing back by metal polishing or by etching back by dry etching or the like, and a contact pillar 711 is formed.

As a method of using a pillar hole, Japanese Patent Application Laid-Open No. 7-283308 discloses a method in which a metal film and an insulating film are laminated on a substrate, a pillar hole is formed in the insulating film by etching, and a metal film is formed on the insulating film including the pillar hole. The metal layer other than the contact pillar portion embedded in the pillar hole is removed, a resist pattern is formed at the lower wiring position, the lower wiring is formed by etching, an interlayer insulating film is formed on the entire surface, and then etched back. A method of forming a multilayer wiring structure by repeatedly exposing the upper surface of a contact pillar by exposure is disclosed.

FIG. 8 is a cross-sectional view showing a step of forming a plug (contact pillar) for multilayer wiring by patterning a conductor film disclosed in Japanese Patent Application Laid-Open No. 8-306779, and FIG. Lower wiring material film and first film
In which a plug forming material film is laminated and a resist pattern is provided in a plug forming position, (b) is a state in which a part of a plug is formed by patterning a first plug forming film, and (c).
Is a state where a second plug forming material film is formed on the entire surface,
(D) is a state in which a resist pattern is provided at the lower wiring position, (e) is a state in which the plug and the lower wiring are formed by patterning the second plug forming material film and the lower wiring material film,
(F) shows a state in which an interlayer insulating film is formed on the entire surface and the interlayer insulating film is removed to a position where the upper surface of the plug is exposed, and (g) shows a state in which an upper wiring is formed on the interlayer insulating film to obtain a multilayer wiring structure. It is. FIG. 9 shows a state in which misregistration has occurred in the resist pattern in the steps of FIGS.
8A shows a state corresponding to FIG. 8D, and FIG.
The state corresponding to (e) is shown. In the figure, reference numeral 831 denotes a multilayer wiring structure, 832 denotes an interlayer insulating film, 833 denotes a lower wiring material film, 833a denotes a first lower wiring material film, and 833b denotes a second wiring material film.
834 is a first plug forming material film,
835 is a resist pattern, 836 is a plug, 836a
Is a part of the plug, 836b is the rest of the plug, 837 is the second plug forming material film, 838 is the resist pattern, 8
39 is a lower wiring, 840 is an interlayer insulating film, 841 is an upper wiring, and 842 is a side etch. In the conventional example, the contact pillar is called a plug.

In the step shown in FIG. 8A, a lower wiring material film 833 and a first plug forming material film 834 are sequentially laminated on an interlayer insulating film 832 which is a base layer, and a position where a part of a plug is formed is formed. Is provided with a resist pattern 835.

In the step of FIG. 8B, the first plug forming material film 833 is patterned to form a part 836a of the plug.
To form

In the step of FIG. 8C, the lower wiring material film 8 is formed.
A second plug forming material film 837 is formed on 33.

In the step of FIG. 8D, a portion of the plug 8 is formed on the second plug forming material film 837 formed in FIG.
A resist pattern 838 is formed so as to cover 36a and the lower wiring position.

In the step of FIG. 8E, the second plug forming material 837 and the lower wiring material 833 are patterned,
After the plug remaining portion 836b is formed to form the plug 836 and the lower wiring 839, the resist pattern 838 is removed.

In the step shown in FIG. 8F, an interlayer insulating film 840 is formed on the interlayer insulating film 832 following the step shown in FIG. 8E, and the interlayer insulating film 840 is removed until the upper surface of the plug 836 is exposed.

In the step of FIG. 8G, an interlayer insulating film 840 is formed.
The upper wiring 841 is formed on the upper surface of the
Get.

As a method for forming a contact pillar by patterning a conductive film, besides this, Japanese Patent Application Laid-Open No. H8-1625
No. 32, an inter-layer insulating film is buried and a conductive layer is formed on the entire lower wiring which has been flattened, a conductive layer other than the contact pillar is removed by etching to form a contact pillar, and an inter-layer insulating film is formed on the entire surface. After that, the interlayer insulating film is removed by polishing or etch back until the upper surface of the contact pillar is exposed.
In JP-A-06-106, an insulating film is formed on the entire surface of a substrate, a groove corresponding to a lower wiring is formed by etching, a conductive film is laminated on the entire surface, a resist pattern is provided at a contact pillar position, and a conductive film is formed up to the upper surface of the insulating film. A method of forming a lower wiring and a contact pillar by etching a semiconductor device is disclosed in
JP-A-345053 discloses a method in which a conductive layer is formed on the entire surface of a silicon substrate, a resist pattern is provided at a predetermined position of the pillar hole on the diffusion layer, and the conductive layer is etched to the surface of the silicon substrate to form a pillar hole. It has been disclosed.

[0018]

However, the prior art has the following problems. According to the first method of forming a contact pillar using a pillar hole, it is difficult to process a pillar hole having a high aspect ratio and to bury a metal film in the pillar hole when the wiring structure forms a fine pillar hole. There is a problem. Furthermore, in dry etching for forming pillar holes, excessive etching is performed temporally to cover in-plane variation of the substrate and non-uniformity of processing called a microloading effect, but a contact hole having a high aspect ratio is formed. In the etching of silicon oxide, the excessive etching increases, and the crystal defects of the diffusion layer due to the damage by dry etching increase.

In the second method of forming a contact pillar directly from a conductive film by etching, when a plug having a high aspect ratio is formed only by a resist mask, the height of the contact pillar is higher than the supporting area, and thus the substrate is transported. There is a danger of the plug physically falling due to the impact of time or etching.

Further, by using the conventional multi-layer wiring forming method of forming contact pillars by etching shown in FIG. 8, in the conventional method of forming contact pillars using pillar holes, an etching resist pattern is aligned. The slit caused by the etching of the interlayer insulating film on the side surface of the lower wiring, which occurs when the displacement occurs, can be prevented. Even if the resist pattern is misaligned, the remaining portion 836b of the plug and the lower wiring 809 are formed as shown in FIG. In this structure, there is no problem even if the resist mask 838 is slightly misaligned when etching the plug portion 836a and the second plug forming material film 837. I have. However, in dry etching, there is an anisotropic etching defect called a side etch, and when forming pillars and wiring with a narrow pitch, not only a sufficient contact resistance of a contact plug cannot be obtained by dry etching, but also a side contact depending on dry etching conditions. The etching 342 becomes large, and the entire contact plug is etched, which may make it difficult to form a plug connecting the upper and lower wirings.

In the method of forming a contact pillar using a pillar hole, when an unnecessary conductive layer on an interlayer insulating film is removed by polishing to form a contact pillar, a conventional metal film polishing technique uses the conductive layer. Since the polishing rate of the tungsten to be formed is higher than the polishing rate of silicon oxide, which is an interlayer insulating film, there is a problem that excessive polishing occurs in the contact pillar and a desired shape cannot be obtained. Also, in a method of forming a contact pillar by etching a conductive layer, in a step of depositing an interlayer insulating film on a substrate surface on which the contact pillar is formed and exposing the top of the contact pillar by polishing, a tungsten film for forming a conductive layer is similarly formed. Is higher than the polishing rate of silicon oxide, which is an interlayer insulating film, the exposed contact pillars are excessively polished, so that a desired shape cannot be obtained.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which fine contact pillars having a stable high aspect ratio are formed and damage to source / drain layers of a MOSFET is reduced.

[0023]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a contact pillar for connecting conductive portions having different layers, the method comprising the steps of: Forming a second insulating film having a thickness smaller than the height of the contact pillar, forming a pillar hole at a position where the contact pillar is formed on the second insulating film, and forming a pillar hole on the second insulating film. Forming a contact film having a base in a pillar hole and removing the conductive film on the second insulating film by etching the conductive film; and forming a contact film on the second insulating film by etching the conductive film. 3rd in thickness beyond the top of the contact pillar
Forming an insulating film, removing the third insulating film until the top of the contact pillar is exposed, and forming a wiring connected to the contact pillar on the third insulating film.

The semiconductor device may be a MOSFET, the base layer of the insulating film having a conductive portion may be a silicon substrate, and the conductive portion may be a source / drain layer. The base layer of the insulating film may be a third insulating film in which the top of the contact pillar is exposed.

Further, the height of the pillar hole formed in the second insulating film may be not more than five times the width of the pillar hole, and the radius of the pillar hole is smaller than the radius of the contact pillar. May be substantially equal to the margin including the misalignment accuracy of the resist pattern for forming the contact pillar.

Further, the material of the contact pillar is tungsten, the third insulating film is silicon oxide, and either the silicon oxide film or the tungsten film covering the top of the contact pillar until the top of the contact pillar is exposed. The step of removing is performed by polishing using a polishing liquid, the polishing liquid is a polishing liquid in which an electrolyte, a pH adjuster, and an oxidizing agent are added to the slurry, and the polishing rate of silicon oxide is higher than the polishing rate of tungsten. Good. The electrolyte to be added to the polishing slurry is ammonium chloride, ammonium nitrate, or ammonium acetate, the pH adjusting agent is hydrochloric acid, nitric acid, glacial acetic acid, or phosphoric acid, and the oxidizing agent is hydrogen peroxide. Is also good. The amount of the electrolyte added to the polishing slurry is 7.7 g / l or more, the amount of the hydrogen peroxide added is 20 ml / l or more, and the amount of the pH adjuster adjusts the pH of the mixed solution to 5-1. It may be.

In the present invention, a pillar hole is formed in the passivation film, a metal film is buried in the pillar hole, and then a pillar is formed using a resist mask. Therefore, the base is buried in the passivation film and a stable high aspect ratio contact pillar is formed. Can be formed.

By setting the aspect ratio of the pillar hole to 5 or less, the embedding of the metal film into the pillar hole is stabilized, and the falling of the contact pillar is stabilized.

Further, by forming pillar holes in the passivation film, filling the pillar holes with a metal film, and then forming pillars using a resist mask, the over-etching performed to improve the non-uniformity of dry etching can be directly performed. Does not affect the source / drain layers,
Damage to the source / drain layers can be suppressed. When forming a pillar hole by dry etching or the like from a conductive film in accordance with the pillar hole, an obstacle caused by misalignment is suppressed by making the diameter of the pillar larger than the diameter of the pillar hole.

An electrolyte, a pH adjusting material, and an oxidizing agent are added to the slurry, and a selective polishing method is used using a polishing material having a polishing rate of 1 or more for a non-metal film relative to a polishing rate of 1 for a metal film. By polishing the interlayer insulating film with embedded contact pillars and the conductive film deposited on the interlayer insulating film,
Polishing can be performed so that the pillar protrudes from the upper surface of the interlayer insulating film, and connection between the wiring and the pillar is facilitated.

[0031]

Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are cross-sectional views showing steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a sectional view showing a trench isolation, a diffusion layer, and a gate oxide film on a silicon substrate. (B) is a state where a passivation film is deposited on the upper surface, (c) is a state where pillar holes are formed in the passivation film, and (d) is a conductor film on the passivation film and in the pillar holes. Is deposited and a resist pattern for contact pillars is arranged, (e)
FIG. 3F shows a state in which a contact pillar is formed by etching back a conductive film, FIG. 4F shows a state in which an interlayer insulating film is deposited, and FIG. 4G shows a state in which the top of the contact pillar is exposed by polishing the interlayer insulating film. In the figure, reference numeral 101 denotes a silicon substrate, 10
2 is a trench isolation, 103 is a diffusion layer, 104 is a gate oxide film, 105 is a gate polysilicon, 106 is an interlayer insulating film, 107 is a conductor film, 108 is a resist pattern,
109 is a passivation film, 110 is a pillar hole, 1
Reference numeral 11 denotes a contact pillar.

In the step of FIG. 1A, the silicon substrate 10
1 is dry-etched to a predetermined depth, for example, 0.5 μm to form a trench, and HTO (High)
Thermal Oxidation High Temperature Thermal Oxidation)
The silicon oxide film formed as described above is embedded, and the trench isolation 102 is formed by polishing the oxide film while leaving only the oxide film in the trench. Next, the gate oxide film 104 and the polysilicon 105 are laminated on the entire surface and dry-etched using a resist mask, so that the gate oxide film 104 and the polysilicon 105 are etched into a desired gate shape.
Thereafter, impurities are implanted into the source / drain formation positions to a depth of, for example, about 0.02 to 0.2 μm, and heat treatment such as RTA or hydrogen annealing is performed to recrystallize and activate the diffusion layer 103.

In the step of FIG. 1B, the passivation film 109, for example, Si ₃ N ₄ or SiO ₂
It is formed over the entire surface with a thickness of about μm.

In the step of FIG. 1C, the passivation film 109 at the position where the contact pillar is to be formed has a diameter of 0.3.
A pillar hole 110 of about μm is opened.

In the present embodiment, the thickness of the passivation film and the diameter of the pillar hole are set as described above. However, the aspect ratio of the pillar hole is desirably 5 or less. The flow of the conductive film into the pillar holes is good, and the stability of the contact pillar is also obtained.

In the step shown in FIG. 1D, a conductor film 107 such as tungsten is deposited at a height at which the contact pillar 111 can be formed, and a diameter of the pillar hole 110 for forming the contact pillar 111 is formed above the pillar hole 110. For example, 0.15 μm including the misalignment accuracy of the resist pattern and the margin of side etching and the like.
A resist pattern 108 having an outer diameter about m larger is arranged.

In the step of FIG. 1E, the contact pillar 111 is formed by anisotropic etching of the conductor film 107. The diameter of the contact pillar 111 is the pillar hole 110
Is designed to be larger than the diameter of the contact pillar, and even if there is some misalignment, the inside of the pillar hole 110 and the outside contact pillar do not cross each other.

In the step of FIG. 1F, the interlayer insulating film 106
Is 0.1 μm higher than the height of the contact pillar 111, for example.
It is formed so as to be thicker.

In the step shown in FIG. 1 (g), the step formed on the upper surface of the interlayer insulating film 106 by the contact pillar 111, the gate polysilicon 105, the trench isolation 102, etc. is flattened by using a polishing liquid. CMP (Chemi) until the upper surface of the contact pillar 111 is exposed.
Selective polishing is performed by cal mechanical polishing (chemical mechanical polishing method). At this time, the polishing liquid for selective polishing has a polishing rate of 1 to tungsten.
In this case, a polishing solution is used in which an electrolytic solution having a polishing rate ratio at which the polishing rate of silicon oxide is at least one or more, a pH adjuster, and an oxidizing agent are added to a slurry.

The contact pillar 1 is formed on the interlayer insulating film 106.
A wiring connected to the top of the semiconductor device is formed to complete a wiring structure connected to the source / drain layers of the semiconductor device. At this time, since the upper surface of the contact pillar 311 exposed by the selective polishing protrudes from the surface of the interlayer insulating film 306, the connection with the wiring is ensured.

The contact pillar is formed by using a polishing liquid obtained by adding a slurry containing an electrolytic solution having a polishing rate ratio at which the polishing rate of silicon oxide is at least one greater than the polishing rate of tungsten, assuming that tungsten is 1. Is a component of the present invention, in which the base is buried in the passivation film to form a contact pillar, which is a first embodiment of the present invention. Not only the method but also the method of forming a contact pillar directly in a diffusion layer as described in the third embodiment, polishing of an interlayer insulating film, forming a pillar hole in an interlayer insulating film, and Also applicable to the removal of the conductive film on the interlayer insulating film by polishing in the method of forming the contact pillar by depositing the conductive film on the insulating film. That.

As a specific configuration of the polishing liquid for the selective polishing, for example, a salt (NHCl) is added to a colloidal silica slurry.
And the like, and a polishing liquid to which HCl is added as a pH adjuster so as to have a pH of 5 to 6 is used. FIG. 2 is a graph showing a change in the processing speed of tungsten and an oxide film depending on the pH of a polishing liquid obtained by adding a salt (such as NHCl) to a colloidal silica slurry. It can be seen that at pH 9, the processing speed was substantially the same for tungsten and oxide film, but at pH 5, the processing speed for oxide film was about four times the processing speed for tungsten.

FIG. 3 is an SEM micrograph showing the shape of a contact pillar which is a fine pattern formed on a substrate formed by using the selective polishing method of the present invention.
(A) is a 2,500-fold micrograph, and (b) is a 50,000-fold micrograph showing a cross section. It can be seen that the top of the contact pillar protrudes from the surface of the interlayer insulating film by the selective polishing method of the present invention.

The structure of the polishing liquid for selective polishing will be described in detail. An electrolyte having a function of agglomerating fine particles, for example, ammonium chloride, ammonium nitrate, ammonium acetate, or the like is added to an ordinary colloidal silica slurry, and then a pH adjuster is added. For example, the polishing liquid is prepared by adding hydrochloric acid, nitric acid, glacial acetic acid, phosphoric acid and the like, and mixing, for example, hydrogen peroxide and the like as an oxidizing agent.

In this case, the amount of the electrolyte added was 7.7 g / l.
As described above, hydrogen peroxide H ₂ O ₂ is added at, for example, 20 ml / l or more, p
The H adjuster varies depending on the electrolyte concentration and the degree of electrolysis.
To about 5 to 1.

Next, a second embodiment of the present invention will be described with reference to FIG. 4A and 4B are cross-sectional views showing steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 4A shows a trench isolation and a diffusion layer and a gate oxide film on a silicon substrate. With gate polysilicon formed and a passivation film deposited on top,
(B) is a state in which pillar holes are formed in the passivation film and active impurities are implanted, (c) is a state in which a conductive film is deposited on the passivation film and in the pillar holes, and (d) is a contact pillar formed by etching back the conductive film. Is formed, (e) is a state where an interlayer insulating film is deposited, and (f) is a state where the interlayer insulating film is polished to expose the top of the contact pillar. In the figure, reference numeral 201 denotes a silicon substrate, 202
Is a trench element isolation, 203 is a diffusion layer, 204 is a gate oxide film, 205 is a gate polysilicon, 206 is an interlayer insulating film, 207 is a conductor film, 209 is a passivation film, and 2
10 is a pillar hole, 211 is a contact pillar, 21
2 is a second diffusion layer, and 213 is a silicide layer.

In the step of FIG. 4A, the silicon substrate 20
A trench is formed by dry-etching a predetermined position 1 to a predetermined depth of, for example, 0.5 μm to form a trench, burying a silicon oxide film formed by HTO or the like, and polishing the oxide film to leave only the oxide film in the trench. A separation 202 is formed. Next, the gate oxide film 204 and the polysilicon 205 are laminated on the entire surface and dry-etched using a resist mask.
5 is etched into a desired gate shape. Then, an impurity having a depth of, for example, 0.0
Diffusion layer 203 is recrystallized and activated by heat treatment such as RTA or hydrogen annealing to form a passivation film 209 such as Si ₃ N ₄ or SiO 2.
₂ is formed on the entire surface with a thickness of about 0.05 to 0.2 μm.

In the step of FIG. 4B, the passivation film 209 at the position where the contact pillar is to be formed has a diameter of 0.3.
A pillar hole 210 of about μm is opened. Next, using the passivation layer 209 as a mask, an active impurity is ion-implanted into the diffusion layer 203 of the silicon substrate to a depth of 0. Implantation is performed to about 1 μm, heat treatment is performed, and recrystallization is performed to form the second diffusion layer 212.

In the step shown in FIG. 4C, a conductor film 207, for example, tungsten or the like is deposited to a height of, for example, 0.3 to 0.5 μm on which the contact pillar 211 can be formed.
(Rapid Thermal Anneal) or hydrogen annealing to form the conductive film 207 and the second diffusion layer 21.
2 is reacted at about 400 ° C. to 900 ° C. to form a silicide layer 213. The conductor film 207 may be a single layer,
The conductive film 207 and the diffusion layer 203 are formed by stacking a laminated film of Ti / TiN or the like.
It may be created between. A pillar hole 21 for forming a contact pillar 211 is formed above the pillar hole 210.
A resist pattern (not shown) having an outer diameter larger than the diameter of 0 by, for example, 0.15 μm is arranged.

In the step of FIG. 4D, the contact pillar 211 is formed by anisotropic etching of the conductor film 207. The diameter of the contact pillar 211 is the pillar hole 210
Is designed to be larger than the diameter of the contact pillar, and even if there is some misalignment, the inside of the pillar hole 210 and the outside contact pillar do not cross each other.

In the step of FIG. 4E, the interlayer insulating film 206 is formed.
Is formed so as to be 0.1 μm or more thicker than the height of the contact pillar 211.

In the step of FIG. 4F, a step formed on the upper surface of the interlayer insulating film 206 by the contact pillar 211, the gate polysilicon 205, the trench element isolation 202 and the like is flattened by using a polishing liquid. The selective polishing is performed until the upper surface of the contact pillar 211 is exposed. At this time, the polishing solution for selective polishing includes an electrolytic solution having a polishing rate ratio at which the polishing rate of silicon oxide is at least 1 or more when the polishing rate is set to 1 with respect to tungsten as in the first embodiment. A polishing liquid obtained by adding an agent and an oxidizing agent to a slurry is used.

The contact pillar 2 is formed on the interlayer insulating film 206.
A wiring connected to the top of the semiconductor device is formed to complete a wiring structure connected to the source / drain layers of the semiconductor device.

In the second embodiment, the second diffusion layer 212 is formed by enlarging the diffusion layer 203 by using the pillar holes 210 of the passivation film 209,
07 and the second diffusion layer 212 are reacted at about 400 ° C. to 900 ° C. to form the silicide layer 213, so that damage to the source / drain layer due to etching can be reduced. Further, the upper surface of the contact pillar 211 exposed by the selective polishing protrudes from the surface of the interlayer insulating film 206, so that the connection with the wiring is ensured.

Next, a third embodiment of the present invention will be described with reference to FIG. FIGS. 5A and 5B are cross-sectional views showing steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 5A shows a trench isolation, a diffusion layer, and a gate oxide film in a silicon substrate. (B) is a state in which a single conductor film is deposited on the entire surface and the gate and the diffusion layer are silicided by heat treatment, and (c) is a state in which the conductor film is etched to form a contact pillar and impurities are formed. (D) shows a state in which an interlayer insulating film is deposited, and (e) shows a state in which the top of the contact pillar is exposed by polishing the interlayer insulating film. In the figure, reference numeral 301 denotes a silicon substrate, 302 denotes a trench element isolation, 303 denotes a diffusion layer,
304 is a gate oxide film, 305 is a gate polysilicon,
306 is an interlayer insulating film, 307 is a conductor film, 311 is a contact pillar, 312 is a second diffusion layer, and 313 is a silicide layer.

In the step of FIG. 5A, the silicon substrate 30
A trench is formed by dry-etching a predetermined position 1 to a predetermined depth of, for example, 0.5 μm to form a trench, burying a silicon oxide film formed by HTO or the like, and polishing the oxide film to leave only the oxide film in the trench. A separation 302 is formed. Thereafter, an impurity is implanted into the source / drain formation position to a depth of, for example, about 0.02 to 0.2 μm to form a diffusion layer 303, and then a gate oxide film 304 and polysilicon 305 are laminated on the entire surface to form a resist mask. Dry etching using a gate oxide film 304,
The polysilicon 305 is etched into a desired gate shape.

In the step of FIG. 5B, the single-layer conductor film 307 is formed.
For example, 0.3 to 0.5 μm of tungsten or the like is formed, and R
The conductor film 307 and the gate and diffusion layer 303 are reacted at about 400 to 900 ° C. by TA or hydrogen annealing to form a silicide, thereby forming a silicide layer 313.
Although the conductor film 307 may be a single layer, a laminated film of Ti / TiN or the like may be formed between the conductor film 307, the diffusion layer 303, and the gate.

In the step of FIG. 5C, the contact pillar 311 is formed by etching the conductor film 307 into a contact shape, for example, a cylindrical shape or a square shape. Next, an impurity is ion-implanted into the silicon substrate 301 to a depth of 0.1 μm.
m, and heat treatment is performed to recrystallize to form a second diffusion layer 312.

In the step of FIG. 5D, the interlayer insulating film 306 is formed.
At least 0.1 μm larger than the contact pillar 311
The contact pillar 311 is embedded so as to be thicker than the above.

In the step of FIG. 5E, the step formed on the upper surface of the interlayer insulating film 306 by the contact pillar 311, the gate polysilicon 305, the trench isolation 302 and the like is flattened by using a polishing liquid. The selective polishing is performed until the upper surface of the contact pillar 311 is exposed. At this time, as in the first embodiment, the polishing liquid for the selective polishing includes an electrolytic solution having a polishing rate ratio at which the polishing rate of silicon oxide is at least 1 or more when the polishing rate is 1 with respect to tungsten, and pH adjustment. A polishing liquid in which an agent and an oxidizing agent are added to a slurry is used.

The contact pillar 3 is formed on the interlayer insulating film 306.
A wiring connected to the top of the semiconductor device is formed to complete a wiring structure connected to the source / drain layers of the semiconductor device.

In the third embodiment, the step of burying the contact pillar in the pillar hole of the passivation film is not used, but the conductor film 307 and the diffusion layer 312 are
The silicide layer 313 is reacted at about 00 ° C. to 900 ° C.
After the formation of the contact pillar 311, the diffusion layer 303 is enlarged by ion implantation of impurities and heat treatment to form the diffusion layer 312, so that damage to the source / drain layer due to etching can be reduced. Further, the upper surface of the contact pillar 311 exposed by the selective polishing protrudes from the surface of the interlayer insulating film 306, and the connection with the wiring is ensured.

Next, a method of forming a contact pillar for a multilayer wiring according to the present invention will be described as a fourth embodiment with reference to FIG. FIG. 6 is a cross-sectional view showing steps of a method of forming a contact pillar for multilayer wiring in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The state of the contact pillar and the interlayer insulating film on the formed silicon substrate, (b) is a state in which wiring is formed at a predetermined position on the interlayer insulating film and the contact pillar, and (c) is a state in which the interlayer insulating film is deposited. (D) shows a state in which pillar holes are formed in the interlayer insulating film, (e) shows a state in which a conductor film is deposited on the interlayer insulating film and in the pillar holes, (f).
Is a state in which a contact pillar is formed by etching back the conductive film, and (g) is a step of depositing and polishing an interlayer insulating film, forming a wiring at a predetermined position on the exposed contact pillar and the interlayer insulating film, and further forming an interlayer. This is a state in which an insulating film is deposited to form a multilayer wiring. In the figure, reference numeral 401 denotes a silicon substrate, 40
2 is a trench element isolation, 403 is a diffusion layer, 404 is a gate oxide film, 405 is a gate polysilicon, 406 is an interlayer insulating film, 409 is a passivation film, 411 is a contact pillar, 413 is a silicide layer, and 421 is a first wiring. 426, a second interlayer insulating film; 427, a conductor film;
0 is a second pillar hole, 431 is a second contact pillar, 441 is a second wiring, 446 is a third interlayer insulating film, and 456 is a fourth interlayer insulating film.

In the step of FIG. 6A, a trench element isolation 402, a gate oxide film 404, and a gate polysilicon 40 are formed on a silicon substrate 401 by the manufacturing method of the second embodiment.
5, forming the diffusion layer 2 and then forming the passivation film 409
Is formed, a pillar hole is opened and a conductive film is buried,
The contact pillar 411 is formed by dry etching. Next, an interlayer insulating film 406 is formed on the contact pillar 41.
1 is concealed, the step on the surface reflecting the gate and the contact pillar under the interlayer insulating film is made flat, and polished by the selective polishing method until the contact pillar 411 is exposed.

In the step of FIG. 6B, the interlayer insulating film 406 is formed.
A conductive film is formed on the upper surface of the contact pillar 411 and the first layer is formed by dry etching and lithography.
Is formed.

In the step of FIG. 6C, a second interlayer insulating film 426 is formed, the first wiring 421 is buried, and the buried interlayer insulating film 426 is planarized. At this time, the thickness of the interlayer insulating film 426 left on the first wiring 421 is set to be five times or less the diameter of a second pillar hole 430 described later in FIG. This value depends on the aspect ratio of the burying limit of the conductive film 427.

In the step of FIG. 6D, a second pillar hole 430 is opened in the interlayer insulating film 426 at the position where the contact pillar 431 is provided, up to the first wiring 421.

In the step of FIG. 6E, the conductive film 42 is formed on the second pillar holes 430 and the second interlayer insulating film 426.
7 The second contact pillar 43 is made of, for example, tungsten or the like.
1 is deposited at a height capable of forming, for example, about 0.3 to 0.5 μm.

In the step of FIG. 6F, a second contact pillar 431 is formed by anisotropic etching of the conductor film 407.

In the step shown in FIG. 6G, the third interlayer insulating film 446 is placed at a height of 0.2 mm from the height of the second contact pillar 431.
The second contact pillar 431 is used to flatten the step formed on the upper surface of the third interlayer insulating film 446 and to form a second contact pillar 4.
The selective polishing is performed using the polishing liquid until the upper surface of the substrate 31 is exposed. Here, a conductive film is formed on the upper surface of the third interlayer insulating film 446 and the second contact pillar 431 in the same manner as in the step of FIG. 6B, and the second wiring 441 is formed by dry etching and lithography. 6C, a fourth interlayer insulating film 456 is formed, the second wiring 441 is buried, and the buried fourth interlayer insulating film 456 is buried.
Is flattened.

Thus, the first and second wirings are completed. If further multilayer wiring is required, the steps shown in FIGS. 6D to 6G are repeated. In this way, a semiconductor device having a multilayer wiring structure can be manufactured by using the method of forming a contact pillar and the method of selectively polishing an interlayer insulating film according to the present invention.

In the fourth embodiment, the method of manufacturing the multilayer wiring structure has been described based on the second embodiment. However, the multilayer wiring structure can be manufactured based on the first and third embodiments. It is.

[0073]

As described above, according to the present invention, a pillar hole for forming a part of a contact pillar is formed in a passivation film, a conductor film is deposited on the passivation film, and the conductor film is embedded in the pillar hole. Then, since the pillar is formed by etching the conductor film on the passivation film using the resist mask, it is possible to form a part of the contact pillar in the passivation film and to form a stable contact pillar. .

Since the base of the contact pillar is buried in the passivation film, there is no fear of falling during the manufacturing process, so that a pillar having a high aspect ratio can be formed. Therefore, there is an effect that a fine MOSFET having pillars with a high aspect ratio can be formed.

By setting the aspect ratio of the pillar hole formed in the passivation film to 5 or less, it becomes easy to embed the conductor film in the pillar hole, and a stable contact pillar can be formed.

Further, since the source / drain layers are protected by the passivation film, there is an effect that the damage to the source / drain layers caused by excessive etching performed to improve the non-uniformity of dry etching can be suppressed.

When the pillar hole is formed by dry etching or the like, the diameter of the contact pillar formed by etching is made larger than the diameter of the pillar hole, so that the source / drain layer generated due to misalignment of the resist pattern is formed. The applied etching defect can be suppressed. This eliminates defects in the source / drain layers due to poor alignment, so that a highly reliable MOSFET can be obtained.

An electrolyte, a pH adjuster and an oxidizing agent are added to the slurry to a polishing liquid used for polishing to expose the top of the contact pillar from the interlayer insulating film. By performing selective polishing using a polishing liquid having a polishing rate of 1 or more, a contact pillar having a top portion protruding from the insulating film surface can be formed, thereby facilitating connection between the wiring and the pillar.
This has the effect that a highly reliable contact pillar can be formed while having a high aspect ratio.

Further, by using the contact pillar manufacturing method and the selective polishing method of the present invention, it is possible to form a contact pillar which is surely connected to a wiring in a stable shape. Wiring can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a first embodiment of the present invention. (A) shows a state in which a trench isolation, a diffusion layer, a gate oxide film, and a gate polysilicon are formed on a silicon substrate. (B) shows a state in which a passivation film is deposited on the upper surface. (C) shows a state in which pillar holes are formed in the passivation film. (D) shows a state in which a conductor film is deposited on the passivation film and in the pillar holes and a resist pattern for contact pillars is arranged. (E)
Is a state in which a contact pillar is formed by etching back the conductive film. (F) shows a state where an interlayer insulating film is deposited. (G) shows a state in which the top of the contact pillar is exposed by polishing the interlayer insulating film.

Fig. 2 Salt (NHCl etc.) in colloidal silica slurry
4 is a graph showing a change in a processing speed of tungsten and an oxide film depending on a pH of a polishing liquid to which tungsten is added.

FIG. 3 is an SEM micrograph showing a shape of a contact pillar which is a fine pattern formed on a substrate formed by using the selective polishing method of the present invention. (A) is 2,5
It is a microscope photograph of 00 times. (B) shows a cross section 50,
It is a microscope photograph of 000 times.

FIG. 4 is a cross-sectional view showing steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a second embodiment of the present invention. (A) shows a state in which a trench isolation, a diffusion layer, a gate oxide film and a gate polysilicon are formed on a silicon substrate, and a passivation film is deposited on the upper surface. (B) shows a state in which pillar holes are formed in the passivation film and active impurities are implanted. (C) shows a state in which a conductor film is deposited on the passivation film and in the pillar holes.
(D) shows a state in which the contact pillar is formed by etching back the conductive film. (E) shows a state where an interlayer insulating film is deposited. (F) is a state where the interlayer insulating film is polished to expose the top of the contact pillar.

FIG. 5 is a cross-sectional view illustrating steps of a method of forming a contact pillar in a method of manufacturing a semiconductor device according to a third embodiment of the present invention. (A) shows a state in which a trench isolation, a diffusion layer, a gate oxide film, and a gate polysilicon are formed on a silicon substrate. (B) shows a state in which a single conductor film is deposited on the entire surface and the gate and the diffusion layer are silicided by heat treatment. (C) shows a state in which the contact layer is formed by etching the conductor film, and the diffusion layer is enlarged by ion implantation of impurities and heat treatment. (D) shows a state where an interlayer insulating film is deposited. (E) shows a state in which the top of the contact pillar is exposed by polishing the interlayer insulating film.

FIG. 6 is a sectional view showing steps of a method for forming a contact pillar for multilayer wiring in a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. (A) shows the state of the contact pillar and the interlayer insulating film on the silicon substrate formed by the manufacturing method of the second embodiment. (B) shows a state in which a wiring is formed at a predetermined position on the interlayer insulating film and the contact pillar. (C) shows a state where an interlayer insulating film is deposited.
(D) shows a state in which pillar holes are formed in the interlayer insulating film. (E) shows a state in which a conductor film is deposited on the interlayer insulating film and in the pillar holes. (F) shows a state in which a contact pillar is formed by etching back the conductive film. (G) shows a state in which an interlayer insulating film is deposited and polished, a wiring is formed at a predetermined position on the exposed contact pillar and the interlayer insulating film, and a multilayer wiring is formed by further depositing an interlayer insulating film.

FIG. 7 is a cross-sectional view showing steps of a method for forming a contact pillar of a MOSFET using pillar holes in a conventional example. (A) shows a state in which a diffusion layer, a gate oxide film, and a passivation film are formed on a silicon substrate. (B) shows a state in which pillar holes are formed in the insulating film laminated on the upper surface. (C) shows a state in which a conductive film is embedded in the pillar hole. (D) shows a state in which the contact pillar is formed by polishing the conductive film.

FIG. 8 is a cross-sectional view showing a process of forming a plug (contact pillar) for multilayer wiring by patterning a conductive film disclosed in Japanese Patent Application Laid-Open No. 8-306779. (A)
The figure shows a state in which a lower wiring material film and a first plug forming material film are laminated on a base interlayer insulating film, and a resist pattern is provided at a plug forming position. FIG. 2B shows a state in which a part of the plug is formed by patterning the first plug formation film.
(C) shows a state where a second plug forming material film is formed on the entire surface. (D) shows a state in which a resist pattern is provided at a lower wiring position. (E) shows a state in which the plug and the lower wiring are formed by patterning the second plug forming material film and the lower wiring material film. (F) forms an interlayer insulating film on the entire surface,
In this state, the interlayer insulating film is removed to a position where the upper surface of the plug is exposed. (G) shows a state in which an upper layer wiring is formed on the interlayer insulating film to obtain a multilayer wiring structure.

FIG. 9 shows a state in which misregistration has occurred in the resist pattern in the steps of FIGS. 8D and 8E. (A) shows a state corresponding to FIG. 8 (d). FIG. 8B shows a state corresponding to FIG.

[Explanation of symbols]

101, 201, 301, 401, 701 Silicon substrate 102, 202, 302, 402, 702 Trench element isolation 103, 203, 303, 403, 703 Diffusion layer 104, 204, 304, 404, 704 Gate oxide film 105, 205, 305, 405, 705 Gate polysilicon 106, 206, 306, 406, 706 Interlayer insulating film 107, 207, 307, 707 Conductive film 108 Resist pattern 109, 209, 409, 709 Passivation film 110, 210, 710 Pillar hole 111, 211, 311, 411, 711 Contact pillar 212, 312 Second diffusion layer 213, 313, 413 Silicide layer 421 First wiring 426 Second interlayer insulating film 427 Conductive film 430 Second pillar hole 431 Second core Tact pillar 441 Second wiring 446 Third interlayer insulating film 456 Fourth interlayer insulating film 831 Multilayer wiring structure 832 Interlayer insulating film 833 Lower wiring material film 833a First lower wiring material film 833b Second lower wiring material film 834 First plug forming material film 835 Resist pattern 836 Plug 836a Part of plug 836b Remaining plug 837 Second plug forming material film 838 Resist pattern 839 Lower wiring 840 Interlayer insulating film 841 Upper wiring 842 Side etch

Claims (15)

[Claims] 1. A method of manufacturing a semiconductor device having a contact pillar for connecting between conductive portions having different layers, wherein the semiconductor device has a thickness smaller than a height of the contact pillar on a base layer of an insulating film having the conductive portion. Forming a second insulating film, forming a pillar hole at a position of the second insulating film where the contact pillar is formed, and forming a conductive film on the second insulating film and in the pillar hole. Forming the contact pillar having a base in the pillar hole by etching the conductive film and removing the conductive film on the second insulating film; and forming the contact pillar on the second insulating film. Forming a third insulating film with a thickness exceeding the top of the contact pillar; removing the third insulating film until the top of the contact pillar is exposed; The method of manufacturing a semiconductor device comprising: the step of forming a wiring of connection between the contact pillars on the insulating film, comprising the. 2. The semiconductor device is a MOSFET,
The method according to claim 1, wherein a base layer of the insulating film having the conductive part is a silicon substrate, and the conductive part is a source / drain layer. 3. The semiconductor device has a multilayer wiring structure,
The base layer of the insulating film having the conductive portion is the third insulating film in which a top of the contact pillar is exposed.
13. The method for manufacturing a semiconductor device according to item 5. 4. The semiconductor device according to claim 1, wherein a height of said pillar hole formed in said second insulating film is not more than five times a width of said pillar hole. Manufacturing method. 5. The method according to claim 1, wherein a radius of the pillar hole is smaller than a radius of the contact pillar, and a difference between the pillar holes is substantially equal to a margin including a misalignment accuracy of a resist pattern for forming the contact pillar. 3
13. The method for manufacturing a semiconductor device according to claim 1. 6. The contact pillar is made of tungsten, the third insulating film is made of silicon oxide,
The step of removing the third insulating film until the top of the contact pillar is exposed is performed by polishing using a polishing solution, and the polishing solution is obtained by adding an electrolyte, a pH adjusting agent, and an oxidizing agent to a slurry, and adding silicon oxide. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said polishing liquid is a polishing liquid having a polishing rate higher than that of tungsten. 7. The method according to claim 6, wherein the electrolyte added to the slurry of the polishing liquid is any one of ammonium chloride, ammonium nitrate, and ammonium acetate. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the pH adjuster added to the slurry of the polishing liquid is any of hydrochloric acid, nitric acid, glacial acetic acid, and phosphoric acid. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the oxidizing agent added to the slurry of the polishing liquid is hydrogen peroxide. 10. The addition amount of the electrolyte to the slurry of the polishing liquid is 7.7 g / l or more, the addition amount of hydrogen peroxide is 20 ml / l or more, and the addition amount of the pH adjuster is pH of the mixed solution.
The method for manufacturing a semiconductor device according to claim 6, wherein the amount is adjusted to 5-1. 11. A method for manufacturing a semiconductor device having a contact pillar for connecting conductive portions having different layers, wherein the material of the contact pillar is tungsten, and an insulating film surrounding the contact pillar is silicon oxide; The step of removing any of the silicon oxide film and the tungsten film covering the top of the contact pillar until the top of the contact pillar is exposed is performed by polishing using a polishing liquid, and the polishing liquid converts the slurry into an electrolyte and a pH adjuster. And a oxidizing agent, wherein the polishing rate of silicon oxide is higher than the polishing rate of tungsten. 12. The method according to claim 11, wherein the electrolyte added to the slurry of the polishing liquid is any one of ammonium chloride, ammonium nitrate, and ammonium acetate. 13. A pH added to a slurry of the polishing liquid.
The method for manufacturing a semiconductor device according to claim 11, wherein the adjusting agent is one of hydrochloric acid, nitric acid, glacial acetic acid, and phosphoric acid. 14. The method according to claim 11, wherein the oxidizing agent added to the slurry of the polishing liquid is hydrogen peroxide. 15. The addition amount of the electrolyte added to the slurry of the polishing liquid is 7.7 g / l or more, the addition amount of hydrogen peroxide is 20 ml / l or more, and the addition amount of the pH adjuster is pH of the mixed solution.
15. The amount which adjusts to 5-1.
13. The method for manufacturing a semiconductor device according to claim 1.