JPH05129579A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To provide a solid state image sensor in which the photosensitive part can be a two-dimensional area though the sensor has a logarithmical compression converter. CONSTITUTION:A solid state image sensor has a photosensor 1 capable of generating an optical current corresponding to the amount of incident light, a logarithmical compression converter 2 for logarithmical compression-converting the current, and a transfer unit 3 for transferring signal charge logarithmical compression-converted by the converter. The photosensor is formed on an upper layer than the layer formed with the converter and the transfer unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device configured to convert an optical signal into an electric signal and transfer the electric signal toward an output side.

[0002]

2. Description of the Related Art FIG. 4 shows pixels and CCs in a solid-state image pickup device previously filed by the applicant (Japanese Patent Application No. 1-333472).
6 shows an example of the configuration of a charge injection unit for D. In the figure, (a) is a plan view, (b) is an electric circuit diagram, and (c).
FIG. 3 is a structural cross-sectional view. In this solid-state imaging device, the drain of the p-channel MOS transistor 2P also serves as the anode of the photodiode 1.

That is, in this example, an n well 5 is formed on a P type substrate 4, the n well 5 is used as the cathode of the photodiode 1, and the P + region 6 diffused and formed on the n well 5 is used as the anode. Further, a p-channel MOS transistor 2p is formed on the n-well 5, and the P
By using the + region 6 as the drain of the p-channel MOS transistor 2p, the P + region 6 is shared with the anode of the photodiode 1. The other P + region 7 on the n-well 5 is the P-channel transistor 2p.
Has become the source of.

In such a structure, the DC voltage VD is applied to the n-well 5 from the aluminum electrode 8 through the n + region 9.
D is the source 7 of the p-channel MOS transistor 2p
A DC voltage VP is applied to the gate and a precharge pulse ΦP is applied to the electrode 10 of the gate. Further, an n-channel MOS transistor 2a and a CCD are formed on the P-type substrate 4, and a logarithmic conversion circuit, a charge transfer unit, etc. are formed. The n-channel MOS transistor 2a has n + regions 13 and 14 as sources and drains, and 15 as a gate electrode.

In FIG. 4, the aluminum wiring 1 above the gate electrode 10 of the p-channel MOS transistor 2p.
1 is provided to reduce the resistance value of the gate wiring made of polysilicon. Reference numeral 12 is an insulating film. Further, a light-shielding aluminum 17 is provided on the entire surface of the solid-state imaging device except for the upper portion of the P + region 6 forming the anode of the photodiode 1 to prevent light from entering the portion other than the photodiode 1. Further, 16 is an insulating film.

The P-channel MOS transistor 2P
Is mainly for improving the light responsivity of the photodiode 1, and specifically, a pulse voltage is applied to the connection point with the photodiode 1. On the other hand, the N-channel MOS transistor 2a has a function of logarithmically compressing and converting an optical signal.

By the way, many solid-state image pickup devices have a narrow dynamic range as compared with a silver salt film. Therefore, it is necessary to precisely control the exposure amount. Has a drawback that it is likely to be crushed in black and saturated in bright areas.
A solid-state imaging device that solves these problems and has a wide dynamic range and is capable of imaging from high brightness to low brightness has been proposed. According to this, a photosensitive unit capable of generating a photocurrent according to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias for biasing the MOS transistor to a state of a threshold voltage or less and a subthreshold current can flow. Means is provided and the MOS transistor is used in the subthreshold current characteristic region so that the photocurrent can be logarithmically compressed and converted.
The N-channel MOS transistor 2a is used for this purpose.

[0008]

However, in such a solid-state image pickup device having a logarithmic compression conversion circuit built-in, the area of the photosensitive portion (photodiode) is narrowed by the amount of the logarithmic compression conversion circuit and the portion related thereto. Become. Therefore, there is a drawback that it is difficult to adopt a configuration in which the photosensitive portion is arranged in the area instead of the line.

On the other hand, in order to make the solid-state image pickup device correspond to a moving subject, it is desired to use an area sensor. If a line sensor is used, the line sensor must be mechanically moved in a direction perpendicular to the line direction to detect an image. At this time, if the object is stationary, no problem occurs. This is because there arises a problem that the subject cannot follow the movement of the subject.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state image pickup device having a logarithmic compression conversion circuit and capable of forming a photosensitive portion as an area.

[0011]

In order to achieve the above object, in the present invention, a photosensitive section capable of generating a photocurrent according to the amount of incident light, and a logarithmic compression conversion section for performing logarithmic compression conversion of the photocurrent, In a solid-state imaging device including a transfer unit that transfers the signal charges logarithmically compressed by the logarithmic compression converter, the photosensitive unit is formed in a layer above a layer in which the logarithmic compression converter and the transfer unit are formed. It has a configuration.

[0012]

With this structure, since the photosensitive portion is formed in a layer different from the layer in which the logarithmic compression conversion circuit and the transfer portion are provided, the space occupied by the photosensitive portion is a logarithmic compression conversion circuit. It can be widely used without being limited by the transfer unit. Therefore, it becomes easy to form the solid-state imaging device as an area sensor.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows the structure of a stacked solid-state image pickup device which is an area sensor having a logarithmic compression conversion function. Among them, (a) is its plan view, (b) is an equivalent circuit diagram, and (c) is X- which is shown in the plan view of (a).
A cross section at X'is shown. Here, the solid-state imaging device is roughly divided into a photoelectric conversion unit 1, a logarithmic compression conversion unit 2, and a transfer unit 3 which form a photodiode. In this embodiment, as shown in FIG. 1C, a photoelectric conversion part (photosensitive part) 1 is formed on the logarithmic compression conversion part 2 and the transfer part 3 in a laminated structure.

Here, the photoelectric conversion section 1 is composed of a transparent electrode 21, a photoconductor 22, and a pixel electrode 23, and each pixel is separated by a pixel separation layer 24. The pixel electrode 23 is connected to the P-type substrate 1 by the pixel electrode wiring 26 formed in the lower layer.
Connected to the n + region 14 in 00. The n + region 14 constitutes an accumulation diode together with the P-type substrate 100, and an N-channel MOS constituting the logarithmic compression conversion unit 2.
It also serves as the drain of the transistor 2a.

The drain 1 of this MOS transistor 2a
4 and the gate electrode 15 are connected by a pixel electrode wiring 26. The gate electrode 15 of the MOS transistor 2a and the first electrode 20 of the CCD forming the transfer section 3 are formed as a common electrode. The transfer unit 3 includes the first electrode 20, the second electrode 40 of the CCD, and the vertical C
It is composed of CD transfer gate electrodes 32, 33, 34 and 35, and a buried layer 18 in the n- region. Also, P + area 1
Reference numeral 9 is a channel stop layer that defines a path along which electric charges move, and reference numeral 31 is an insulating film.

The DC voltage and clock pulse applied to each part are shown below. The DC voltage VDD is applied to the transparent electrode 21. In the n + region 13 which is the source of the N-channel MOS transistor 2a, the DC voltage VSS is provided by the wiring 42 and the n + region 12 which forms the input diode of the CCD.
A clock pulse φD is applied to the line 41 by the wiring 41. On the other hand, the DC voltage VR is applied to the second electrode 40 of the CCD. In addition, a DC voltage V is applied to the back gate (substrate).
sub is applied. In the vertical CCD, the transfer gate electrodes 32, 33, 34 and 35 have φ1, φ2 and φ, respectively.
Clock pulses of 3 and φ4 are applied.

Next, the operation of the solid-state image pickup device configured as described above will be described. First, when light enters the photoelectric conversion unit 1, charges are generated in the photoconductor film 22, and an electric field between the transparent electrode 21 and the pixel electrode 23 causes a storage diode to pass from the pixel electrode 23 through the pixel electrode wiring 26. A photocurrent proportional to the intensity of light flows through the drain 14 of the N-channel MOS transistor 2a which also serves as a drain. The MOS transistor 2a
DC voltage VSS applied to the source 13 of the
Voltage Vsub to an appropriate voltage (the MOS transistor 2
By setting the voltage as the sub-threshold characteristic of a), the photocurrent can be converted into a logarithmically compressed voltage. This converted voltage is applied to the first electrode 20 of the CCD which is common with the gate electrode 15 of the MOS transistor 2a.

Next, the injection of signal charges into the CCD will be described with reference to FIGS. CCD at t = t2
When the pulse .phi.D applied to the n + region 12 forming the input diode becomes low level, electrons pass under the first electrode 20 and are injected under the second electrode 40. When φD becomes high level at t = t3, excess electrons return to the n + region 12.
The above corresponds to the reset operation, and after this operation, the integration state is entered. In this state, electrons immediately below the second electrode 40 pass below the first electrode 20 and are emitted to the n + region 12. This corresponds to the current flowing from the n + region 12 to the portion directly below the VD electrode 40, and this current value is an exponential function of the voltage difference between the first electrode 20 and the portion immediately below the second electrode 40. That is, the electrons accumulated directly under the second electrode 40 are determined by the logarithmically compressed voltage VG of the photocurrent detected by the photoelectric conversion unit 1.

Integration is performed as described above, and t = t4 '
After the integration period ends, at t = t5, φ1 and φ3 are VH
, And electrons accumulated directly under the second electrode 40 are transferred by the vertical CCD. Regarding the transfer of the vertical CCD, the relationship between the channel potential and the timing is shown on the right side of FIG. In the transfer gate 32, the signal charge is vertical C
Pixels transferred to the CD are odd-numbered, and pixels transferred by the transfer gate 34 are even-numbered.

At t = t1, which is the start of the even field, φ1 and φ3 become VH, so that the signal charges accumulated under the second electrodes 40 of the even and odd pixels are transferred to the vertical shift register. .. At this time, φ2 and φ
Since 4 is VL, the signal charge is also kept separated in the vertical shift register. φ1 and φ3 at t = t2
After returning to VM, φ2 becomes VM at t = t3, whereby the signal charges of the two pixels are mixed in the vertical shift register. Then, at t = t4, φ1 becomes VL, and thereafter, the vertical shift register is driven by normal four-phase driving. During this time, the pixels and the vertical shift register are separated from each other by the potential barrier formed below the vertical shift register electrode.

On the other hand, t = which is the start of the odd field
Also at t5, φ1 and φ3 become VH, so that the signal charges accumulated under the second electrodes 40 of all pixels are transferred to the vertical shift register. However, in this field, t
Since φ4 becomes VM at = t6, signal charges of two pixels are mixed in a combination different from that in the case of the even field, and transfer is achieved.

In the above embodiment, the photosensitive portion (transparent electrode 2
1, the photoconductor film 22, and the pixel electrode 23) are provided on the entire logarithmic compression conversion unit 2 and the transfer unit 3, but they do not necessarily have to be provided on the whole. Further, in the above-described embodiment, the photoconductor film 22 may be an avalanche amplification type laminated film using, for example, amorphous selenium or the like other than the hydrogenated amorphous silicon film. In such a case, Can further improve the sensitivity.

[0023]

As described above, according to the present invention, in a high-sensitivity solid-state image pickup device having a logarithmic compression converter,
Since the photosensitive area can be used as an area, it is possible to obtain a two-dimensional image signal without mechanically scanning, and it has good responsiveness to a moving subject, and the apparatus can be downsized. it can. In addition, it has an excellent characteristic that the aperture ratio of the photosensitive section can be increased and the logarithmic compression conversion function is provided, and the sensitivity is much higher than that of the conventional solid-state imaging device.

[Brief description of drawings]

FIG. 1 is a diagram showing a solid-state imaging device embodying the present invention.

FIG. 2 is an operation explanatory diagram thereof.

FIG. 3 is a similar operation explanatory diagram.

FIG. 4 is a diagram showing a conventional example.

[Explanation of symbols]

 2 Logarithmic compression conversion unit 3 Transfer unit 21 Transparent electrode 22 Photoconductor film 23 Pixel electrode

Claims (3)

[Claims] 1. A photosensitive section capable of generating a photocurrent according to the amount of incident light, a logarithmic compression conversion section for logarithmically compressing the photocurrent, and a signal charge logarithmically compressed and converted by the logarithmic compression conversion section. In the solid-state imaging device, the transfer unit is provided, and the photosensitive unit is formed in a layer above a layer in which the logarithmic compression conversion unit and the transfer unit are formed. 2. The solid according to claim 1, wherein the photosensitive section constitutes each pixel of the area sensor, and each of the pixels is provided with the logarithmic compression conversion section and a signal charge storage diode. Imaging device. 3. The solid-state imaging device according to claim 1, wherein the photosensitive portion is formed of an amplification type photoconductor film.