JPH07284024A - Solid-state image sensor - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a solid-state imaging device capable of suppressing blooming when capturing a high-brightness subject and obtaining a good image in a wide range of illuminance. A shift register 12a for sending a shift pulse and a MOS transistor Qp are provided as an output part of a reset vertical selection line in a vertical scanning circuit of an amplification type solid-state imaging device in which a reset MOS transistor is connected in series to a photoelectric conversion element. A driver circuit 12b formed of an inverter with a MOS transistor Qn, a first power supply line 12c for supplying a high level potential to the reset vertical selection line 9, and a low level potential supplied to the reset vertical selection line 9. A second power supply line 12d for setting the potential of the second power supply line to a threshold value of the reset MOS transistor or higher, and applying a voltage higher than the threshold value to the gate of the reset MOS transistor during storage. And it works as a horizontal overflow drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to improvement of an amplification readout type solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, in an image sensor, the area per pixel in the image sensor has been reduced and the amount of light incident on each pixel has been reduced as the resolution and density have been increased in the horizontal direction. . Therefore, the intensity of the signal read from the image sensor is lowered, and the S / N ratio (S is a signal, N is a noise) is lowered. In order to overcome such problems, it is considered desirable to use an amplification reading type image sensor.

FIG. 9 is a circuit diagram showing a typical example of a conventional amplification readout type image sensor. This image sensor includes, for example, a photoelectric conversion element 1 formed of a PN junction, an amplification read MOS transistor 2, a pixel selection MOS transistor 3 whose gate is connected to a vertical selection line, and a reset MOS transistor of the photoelectric conversion element 1. 4 are provided as one pixel, a horizontal power supply line 5 for supplying power to pixels including the functional elements 1 to 4, a vertical selection line 6 for selecting pixels arranged in the vertical direction, and a vertical arrangement line. Vertical signal line 7, horizontal selection MOS transistor 8 for selecting pixels arranged in the horizontal direction, horizontal signal line 13, I / V conversion amplifier 10 for converting signal current into voltage, horizontal scanning circuit 11, and vertical scanning circuit 1
Equipped with 2.

FIG. 10 is a circuit diagram for explaining the operation of any one pixel of the image sensor shown in FIG. In the above-described configuration of FIG. 9, the reset vertical selection line 9 is shared with the vertical selection line 6 of the next row in order to reduce the number of wirings arranged in the pixel array and increase the degree of integration. However, in the configuration of FIG. 10, the reset vertical selection line 9 and the vertical selection line 6 of the next row are shown separately, and the signals at the respective positions represented by various reference numerals are the same as those in FIG. It is represented by using the reference numeral.

FIG. 11 is a timing chart for explaining the operation of the circuit for one pixel shown in FIG. In FIG. 11, the period 1H is 1 in the normal television system.
In the horizontal period, the period H-BLK corresponds to the horizontal blanking period and the period Lead-out corresponds to the signal reading period. Further, the clock V1 and the clock H1 are the vertical scanning circuit 1 respectively.
2 and the clocks supplied to the horizontal scanning circuit 11 are schematically shown.

Now, at time T0 shown in FIG. 11, V
The potentials of the vertical selection line 6 shown by S and the horizontal power supply line 5 shown by VL are set to the high level, and the amplification read MOS transistor 2 and the vertical selection MOS transistor 3 are in a conductive state. Since the output terminal of the photoelectric conversion element 1 is connected to the gate electrode of the amplification / readout MOS transistor 2, the amplification / readout MOS transistor 2 is _rendered conductive by an impedance depending on the output potential V _pd of the photoelectric conversion element 1. Has become. After that, the time T within the read period Lead-out
1, the vertical signal line 7 is electrically connected to the I / V conversion amplifier 10 when the i-th output signal Hi from the horizontal scanning circuit 11 becomes high level and the horizontal selection MOS transistor 8 becomes conductive. Then, the signal current I _sig corresponding to the output potential V _pd of the photoelectric conversion element 1 is read out as a voltage signal.

At the time T2 in the next horizontal blanking period, the potential of the reset vertical selection line 9 indicated by VR becomes high level, and the photoelectric conversion element 1 has the vertical selection MOS transistor 3 and the reset MOS transistor. 4 is reset to the voltage level Vreset supplied from the horizontal power supply line 5. Then, from time T3 in the next horizontal blanking period, the photoelectric conversion element 1 enters the accumulation mode for integrating the signal charges generated depending on the incident light.

[0008]

Since the conventional amplification type image sensor is constructed as described above and the area per pixel in the image sensor is reduced to achieve high integration, high brightness is achieved. When capturing an image of a subject, signal charges generated in pixels due to excessive incident light become excessive, and the excess charges overflow into adjacent pixels, and as if light was originally entering the pixel areas not illuminated, There is a problem that the image quality is impaired by the so-called blooming phenomenon.

The present invention has been made in order to solve the above problems, and provides a solid-state image pickup device capable of suppressing blooming at the time of photographing a high-brightness subject and obtaining a good image in a wide range of illuminance. With the goal.

[0010]

According to another aspect of the present invention, there is provided a solid-state image pickup device, wherein a reset first MOS transistor having a photoelectric conversion element portion as a source region and a gate connected to the photoelectric conversion element portion. Second MO for amplified read-out
In a solid-state imaging device including a plurality of pixels each having an S transistor and a third MOS transistor for pixel selection connected in series to the second MOS transistor, the first photoelectric conversion element section is configured to store the charge when the photoelectric conversion element unit stores electric charges. It is characterized in that a scanning means for applying a voltage equal to or higher than the threshold value of the MOS transistor to the gate of the first MOS transistor is provided.

A solid-state image pickup device according to a second aspect of the invention is characterized in that the first MOS transistor is a depletion transistor.

A solid-state image pickup device according to a third aspect of the present invention is characterized in that the channel concentration of the first MOS transistor is equal to that of the substrate or well.

Further, the solid-state image pickup device according to claim 4 is
It is characterized in that the gate length of the first MOS transistor is constituted by a minimum line width.

[0014]

In the solid-state image pickup device according to the first aspect of the present invention, the gate of the first MOS transistor for resetting is set to be equal to or more than the threshold value of the MOS transistor when the photoelectric conversion element section stores the charge by the scanning means. A first unit for resetting the photoelectric conversion element unit by applying a voltage
Blooming is suppressed by turning on the MOS transistor of No. 2 during the accumulation period so that excess charge generated in the photoelectric conversion element unit is extracted from the source side of the first MOS transistor for resetting.

In the solid-state image pickup device according to the second aspect of the present invention, the voltage applied to the gate can be set to the ground level by configuring the first MOS transistor as a depletion transistor, and its power supply line is unnecessary. It becomes possible to

Further, in the solid-state imaging device according to the third aspect, by making the channel concentration of the first MOS transistor equal to the concentration of the substrate or well, the threshold voltage can be determined by the concentration. Reduces reset variations.

Further, in the solid-state image pickup device according to the fourth aspect, the pixel size can be reduced by configuring the gate length of the first MOS transistor with the minimum line width.

[0018]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. First, although the first embodiment has the same configuration as the image sensor shown in FIG. 9 and the circuit of one pixel shown in FIG. 10 according to the conventional example, in the circuit diagram shown in FIG. Vertical selection line for reset 9
The circuit configuration of the output part of the photoelectric conversion element 1 is different, and when the photoelectric conversion element 1 is charged, a voltage higher than the threshold value of the MOS transistor 4 is applied to the gate of the reset MOS transistor 4 to reset the photoelectric conversion element 1. The MOS transistor 4 is also turned on during the accumulation period, and the photoelectric conversion element 1
Resetting MOS transistor 4
Blooming is suppressed by pulling out from the source side.

That is, FIG. 1 relates to the first embodiment,
FIG. 11 is a circuit configuration diagram showing in detail the output portion of the reset vertical selection line 9 in the vertical scanning circuit 12 in the circuit configuration diagram of one pixel shown in FIG. 10. In FIG. 1, 1 to 12 indicate the same parts as in FIG. 10, 1 is a photoelectric conversion element formed of, for example, a PN junction, 2 is an amplification read MOS transistor,
3 is a pixel selection MOS whose gate is connected to a vertical selection line
Transistors 4 are reset MOS of the photoelectric conversion element 1.
A transistor forms one pixel of the image sensor. Further, 5 is a horizontal power supply line for supplying power to pixels including those functional elements 1 to 4, 6 is a vertical selection line for selecting pixels arranged in the vertical direction, and 7 is a vertical arranged line in the vertical direction. Signal line, 8 is a horizontal selection MOS transistor for selecting pixels arranged in the horizontal direction, 1
Reference numeral 0 is an I / V conversion amplifier for converting a signal current into voltage, 11 is a horizontal scanning circuit, 12 is a vertical scanning circuit, 13 is a horizontal signal line, and a reset vertical selection line 9 in the vertical scanning circuit 12 is provided. As the circuit configuration of the output section of the above, 12a is a shift register for transmitting a shift pulse, 12b is a driver circuit including an inverter of a p-channel MOS transistor Qp and an n-channel MOS transistor Qn, and 12c.
Is a high-level potential VR on the reset vertical selection line 9.
(H) is a first power supply line, and 12d is a second power supply line for supplying a low-level potential VR (L) to the reset vertical selection line 9, and this second power supply line is shown. VR
The potential of (L) is set to be equal to or higher than the threshold value of the reset MOS transistor 4.

FIG. 2 is a timing chart for explaining the operation of the first embodiment, and FIG. 3 shows a schematic sectional view and a potential flowchart of the reset MOS transistor 4 for explaining the operation of the first embodiment. Things
The operation of the image sensor according to the first embodiment will be described below with reference to FIGS. 2 and 3. In FIG. 2, the period 1
H is one horizontal period in the normal television system, the period H-BLK corresponds to the horizontal blanking period, and the period Lead-out corresponds to the signal reading period. A clock V1 and a clock H1 schematically represent clocks supplied to the vertical scanning circuit 12 and the horizontal scanning circuit 11, respectively. 3A is a schematic cross-sectional view of the reset MOS transistor 4, in which the gate 4a of the reset MOS transistor 4 is connected to the reset vertical selection line 9 and the drain 4b is connected to the horizontal power supply line 5. The source region is the photoelectric conversion element 1. Further, 4c indicates a substrate.

Now, in FIG. 2, from time T0 to T2, the operation is similar to the conventional example, and the photoelectric conversion element 1 is reset to the voltage level Vreset supplied from the horizontal power supply line 5 (FIG. 3 (D)). reference). That is, time T0 shown in FIG.
, The potentials of the vertical selection line 6 indicated by VS and the horizontal power supply line 5 indicated by VL are set to the high level, and the amplification read MOS transistor 2 and the vertical selection MOS transistor 3 are in a conductive state. Since the output terminal of the photoelectric conversion element 1 is connected to the gate electrode of the amplification read MOS transistor 2, the amplification read MOS transistor 2 is connected.
Is in a conducting state with an impedance that depends on the output potential V _pd of the photoelectric conversion element 1.

After that, the time T1 within the read period Lead-out is reached.
, The i-th output signal H from the horizontal scanning circuit 11
When i becomes high level and the horizontal selection MOS transistor 8 becomes conductive, the vertical signal line 7 is electrically connected to the I / V conversion amplifier 10 and corresponds to the output potential V _pd of the photoelectric conversion element 1. The signal current I _sig will be read out as a voltage signal. At time T2 in the next horizontal blanking period, the potential of the reset vertical selection line 9 indicated by VR becomes high level, and the photoelectric conversion element 1 is connected to the vertical selection MOS.
The voltage level Vreset supplied from the horizontal power supply line 5 is reset through the transistor 3 and the reset MOS transistor 4.

Then, from time T3, the photoelectric conversion element 1
Enters a storage mode in which signal charges generated depending on the incident light are integrated (see FIG. 3B). At this time, the potential potential of the gate 4a of the reset MOS transistor 4 is VR when the threshold voltage when the back gate of the reset MOS transistor 4 is not applied is Vthr (O). The low level VR of the reset vertical selection line 9 is set so that (L)> Vthr (O).
The potential is set to (L). That is, as shown in FIG. 1, the potential of the reset vertical selection line 9 is changed by the driver circuit 12b which is an inverter.
The high-level potential VR (H) of the first power supply line 12c at the timing of being inverted to the (n + 1) th shift pulse of 2a.
And the low-level potential VR (L) of the second power supply line 12d, and the low-level potential VR (L) set by the second power supply line 12d, that is, the reset MOS transistor 4 in the accumulation mode. A voltage equal to or higher than the threshold voltage is applied to the gate of the reset MOS transistor 4.

Therefore, the potential potential of the photoelectric conversion element 1, that is, the source potential φ _PD of the reset MOS transistor 4 is φ _PD > VR (L) −Vthr (φ _PD ) (Vt
When hr (φ _PD ) is the threshold voltage when the back gate is applied), the reset MOS transistor 4 is cut off, so that a normal accumulation operation is performed and φ _PD <VR
When (L) -Vthr (φ _PD ) is reached, the reset MOS transistor 4 is turned on, excess charge is extracted to the drain 4b, and the reset MOS transistor 4 acts as an overflow drain (FIG. 3C and FIG. 2 (see time T4), excess charges do not spread to adjacent pixels, and blooming is suppressed.

Here, the maximum accumulated charge amount Qmax of the photoelectric conversion element 1 is determined by {Vreset- (VR (L) -Vthr (L)} / C _PD . C _PD ; Capacity of the photoelectric conversion element 1 Vthr (L _{); φ PD = VR (L} ) -Vthr (Vthr satisfying φ _PD) (φ _PD)

Therefore, according to the first embodiment, the reset MO connected in series to the photoelectric conversion element 1 in the accumulation mode.
Since a voltage equal to or higher than the threshold voltage of the reset MOS transistor 4 set by the second power supply line 12d is applied to the gate of the S transistor 4, the reset MOS transistor 4 is kept in the ON state even during the accumulation period. The excess charge generated in the photoelectric conversion element 1
Blooming is suppressed by pulling out to the source side of the OS transistor 4, and a good image can be obtained in a wide range of illuminance.

Example 2. Next, a second embodiment will be described. FIG. 4 is a circuit diagram of one pixel according to the second embodiment.
The same parts as those in the first embodiment shown in FIG. In the circuit diagram of one pixel according to the second embodiment, as shown in FIG. 4, the gate of the reset MOS transistor 4 is connected to the horizontal power supply line 5 indicated by VL, and the configuration of the first embodiment shown in FIG. In contrast, the reset vertical selection line 9 is omitted, and when the vertical scanning circuit 12A accumulates charges in the photoelectric conversion element 1, the reset MOS transistor 4 is inserted through the horizontal scanning line 5 in the same manner as in the first embodiment. The voltage above the threshold is applied to the gate of the.

That is, FIG. 5 shows the vertical scanning circuit 12A.
3 is a circuit configuration diagram showing an output portion of a horizontal power supply line 5 in FIG. In FIG. 5, reference numeral 12Aa is a shift register for transmitting a shift pulse, and 12Ab is an inverter composed of a p-channel MOS transistor Qp1 and an n-channel MOS transistor Qn1 provided between first and second power supply lines, which will be described later, and n.
A driver circuit having a series body with a channel MOS transistor Qn2, a p-channel MOS transistor Qp2 provided between a second power supply line described later and the output terminal of the inverter, that is, the horizontal power supply line 5, and 12A
c is a first power supply line for supplying a high-level potential VL (H) to the horizontal power supply line 5, and 12Ad is the horizontal power supply line 5.
Is a second power supply line for supplying a low level potential VL (L) to the horizontal power supply line 12Ae, and 12Ae is a third power supply line for supplying a middle level potential VL (M) to the horizontal power supply line 5.
Here, the middle-level potential VL (M) of the third power supply line 12Ae is set to the power supply voltage for reading the signal above the threshold of the reset MOS transistor 4.

FIG. 6 is a timing chart for explaining the operation of the second embodiment, and FIG. 7 shows a schematic sectional view and a potential flow chart of the reset MOS transistor 4 for explaining the operation of the second embodiment. Things
Hereinafter, the operation of the image sensor according to the second embodiment will be described with reference to FIGS. 6 and 7. In FIG. 6, period 1
H is one horizontal period in the normal television system, the period H-BLK corresponds to the horizontal blanking period, and the period Lead-out corresponds to the signal reading period. A clock V1 and a clock H1 schematically represent clocks supplied to the vertical scanning circuit 12 and the horizontal scanning circuit 11, respectively. 7A is a schematic cross-sectional view of the reset MOS transistor 4, in which the gate 4a and the drain 4b of the reset MOS transistor 4 are connected to the horizontal power supply line 5, and the source region is the photoelectric conversion element 1. ing. Also,
Reference numeral 4c indicates a substrate.

Now, in FIG. 6, the operation is similar to the conventional example. That is, at time T2, when the potential of the horizontal power supply line 5 becomes high level, the potential potential φ _PD of the photoelectric conversion element 1 is reset to φ _PD = VL (H) −Vthr (H) (FIG. 7 (D )reference). Then, from time T3, similarly to the first embodiment, the storage mode is entered (see FIG. 7C). At this time, the potential potential of the gate 4a of the reset MOS transistor 4 is VL (L)> Vthr.
The potential of the horizontal power supply line 5 is set to the low level potential indicated by VL so as to be (O). In this second embodiment, VL
(L) = VL (M). Middle level VL (M)
Is a power supply voltage in signal reading at times T0 and T1.

That is, as shown in FIG. 1, the potential of the horizontal power supply line 6 is inverted to the (n + 1) th shift pulse of the shift register 12Aa by the driver circuit 12Ab at a high level of the first power supply line 12Ac. Potential VL (H) and the middle level potential VL (M) of the third power supply line 12Ae, and the middle level potential V set by the third power supply line 12Ae in the accumulation mode.
L (M), that is, the power supply voltage for signal reading equal to or higher than the threshold voltage of the reset MOS transistor 4 is applied to the gate of the reset MOS transistor 4.

Therefore, φ _PD > VL (L) -Vthr
At the time of (φ _PD ), the reset MOS transistor 4 is cut off and the normal accumulation operation is performed. φ _PD <VL
When (L) -Vthr (φ _PD ) is reached, the reset MOS transistor 4 is turned on, excess charges are extracted to the drain 4b, and the reset MOS transistor 4 functions as an overflow drain (see FIGS. 7C and 6). See time T4).

Here, the maximum accumulated charge amount Qmax of the photoelectric conversion element 1 is represented by {(VL (H) -Vthr (H))-(VL (M) -Vthr
(M)} / C _PD . Vthr (H); φ _PD = VR (H) −Vthr (φ _PD ) Vthr (φ _PD )

Therefore, according to the second embodiment, the reset MO connected in series with the photoelectric conversion element 1 in the accumulation mode.
Since a voltage equal to or higher than the threshold voltage of the reset MOS transistor 4 set by the third power supply line 12Ae is applied to the gate of the S-transistor 4, it is reset during the accumulation period as in the first embodiment. By turning on the use MOS transistor 4 and extracting excess charges generated in the photoelectric conversion element 1 to the source side of the reset MOS transistor 4, blooming is suppressed and a good image can be obtained in a wide range of illuminance.

Example 3. In the third embodiment, as shown in FIG.
0 and the reset MOS of the first and second embodiments shown in FIG.
By making the transistor 4 a depletion transistor, it is possible to eliminate the need for a power supply line connected to its gate. Normally, the threshold voltage Vth (O) of the MOS transistor is set to NM considering the noise margin.
In the case of the OS transistor, Vth (O)> 0 is set. Therefore, as shown in FIG. 10 and FIG. 2, the low level VR (L) of the reset vertical selection line 9 and the horizontal power supply line 5 is low.
And VL (L) require a power source separate from the low level of the vertical selection line 6, etc., but Vthr (O) <0, that is, if the reset MOS transistor 4 is a depletion transistor, the vertical selection for reset is performed. The low levels VR (L) and VL (L) of the line 9 and the horizontal power supply line 5 can be set to the ground level, and the power supply line can be eliminated.

Example 4. Further, in the first and second embodiments, the threshold voltage Vthr (O) of the reset MOS transistor 4 is equal to the Vth of other MOS transistors.
Since it may be smaller than (O), it is possible to use, as the reset MOS transistor 4, one having the minimum gate length L effective for the short channel effect and the like. Reset MOS in 2
By using a transistor having a minimum gate width as the transistor 4, the pixel size can be reduced.

Example 5. In the fifth embodiment, the reset variation is reduced by making the channel concentration of the reset MOS transistor 4 in the first and second embodiments equal to the concentration of the substrate or the well. That is, since Vth (O) of a normal MOS transistor has a margin, the acceptor concentration under the gate is made higher than the substrate (well) concentration by ion implantation or the like, but Vthr (O) does not require a margin. Vthr of reset MOS transistor 4
(O) can be determined by the substrate (well) concentration, and by determining the substrate (well) concentration, reset variations can be reduced.

Example 6. In addition, in the said Examples 1-5,
Although the MOS transistor is shown to be configured by NMOS, it may be PMOS, and in that case, the same effect can be obtained although the polarities are opposite.

Example 7. Next, FIG. 8 shows another embodiment of the present invention. In FIG. 8, 14 and 15 are pixel-mixing MOS transistors, and 16 is a pixel-mixing vertical selection line (VT). The pixel-mixing circuit elements 1 to 6 constituting the pixel of the second embodiment shown in FIG. The first group to which the MOS transistor 14 for use is added, the photoelectric conversion element 1,
The pixel mixing MOS transistor 15 and the second group of pixel mixing vertical selection lines 16 are alternately arranged in the vertical direction.

In this circuit configuration, the pixel mixing transistor 14 (the pixel mixing transistor 15 after the field switching) is turned on after the accumulation, and the signal charges accumulated in the photoelectric conversion elements 1 of the first and second groups are mixed. After that, the signal is read out and the reset operation is performed as in the second embodiment. Also in this embodiment, as in the second embodiment, the VL at the time of accumulation is stored.
By setting the low level of the horizontal power supply line 5 so that (L)> Vthr (O), the same effects as those of the first and second embodiments are achieved.

[0041]

As described above, according to the first aspect of the present invention, the first MOS transistor for resetting in which the source region is the photoelectric conversion element section and the gate is connected to the photoelectric conversion element section. In the solid-state image sensor including a plurality of pixels each having a second MOS transistor for amplification and reading and a third MOS transistor for pixel selection connected in series to the second MOS transistor, the photoelectric conversion element section is provided. Since a scanning means for applying a voltage equal to or higher than the threshold value of the MOS transistor to the gate of the reset first MOS transistor at the time of accumulating the electric charge of the first MOS transistor is provided, the first MOS for resetting the photoelectric conversion element section is provided. The transistor is turned on even during the accumulation period, and excess charge generated in the photoelectric conversion element section is pulled from the source side of the first MOS transistor for resetting. In the memorial can be suppressed blooming, there is an effect that it is possible to obtain a satisfactory image in a wide range of illuminance.

According to claim 2, the first MO
By configuring the S transistor as a depletion transistor, there is an effect that the voltage applied to the gate can be set to the ground level and the power supply line can be made unnecessary.

According to claim 3, the first MO
By making the channel concentration of the S-transistor equal to that of the substrate or well, the threshold voltage can be determined by the concentration, and reset variations can be reduced.

Further, according to claim 4, the first M
By configuring the gate length of the OS transistor with the minimum line width, there is an effect that the pixel size can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an output portion of a reset vertical selection line 9 in a vertical scanning circuit 12 for explaining a solid-state image sensor according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the solid-state image sensor according to the first embodiment of the present invention.

3A and 3B are a schematic sectional view and a potential flow diagram of the solid-state imaging device according to Embodiment 1 of the present invention.

FIG. 4 is a circuit configuration diagram of one pixel for explaining a solid-state image sensor according to a second embodiment of the present invention.

5 is a circuit configuration diagram illustrating an output portion of a horizontal power supply line 5 in the vertical scanning circuit 12A shown in FIG. 4 for explaining the solid-state image sensor according to the second embodiment of the present invention.

FIG. 6 is a timing chart illustrating the operation of the solid-state image sensor according to the second embodiment of the present invention.

7A and 7B are a schematic sectional view and a potential flow diagram of the solid-state image sensor according to the first embodiment of the present invention.

FIG. 8 relates to Example 7 of the present invention, and Example 2
A first group in which a pixel-mixing MOS transistor is added to the circuit configuring the pixel and a second group including a photoelectric conversion element, a pixel-mixing MOS transistor, and a pixel-mixing vertical selection line are alternately arranged in the vertical direction. It is a block diagram of the applied example.

FIG. 9 is a circuit diagram showing an amplification readout type solid-state imaging device according to the present invention and a conventional example.

FIG. 10 is a circuit configuration diagram of one pixel of the solid-state imaging device according to the first embodiment of the present invention and the conventional example.

FIG. 11 is a timing chart for explaining the operation of the solid-state image sensor according to the conventional example.

[Explanation of symbols]

1 photoelectric conversion element, 2 amplification read MOS transistor, 3 pixel selection MOS transistor, 4 reset MOS transistor, 5 horizontal power supply line, 6 vertical selection line, 7 vertical signal line, 9 reset vertical selection line, 12
Vertical scanning circuit, 12a shift register, 12b driver circuit, 12c first power supply line, 12d second power supply line, 12A vertical scanning circuit, 12Aa shift register, 12Ab driver circuit, 12Ac first power supply line, 12Ad second Power line, 12Ae Third power line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hikaru Kawashima 4-1-1 Mizuhara, Itami-shi In the ULS AI Development Laboratory, Mitsubishi Electric Corporation (72) Inventor Naofumi Murata 4-1-1 Mizuhara, Itami Mitsubishi Electric Corp. ULS Development Lab.

Claims (4)

[Claims] 1. A first MOS transistor for resetting in which a source region is a photoelectric conversion element section, a second MOS transistor for amplification and reading whose gate is connected to the photoelectric conversion element section, and the second MOS transistor. In a solid-state imaging device including a plurality of pixels each having a third MOS transistor for pixel selection connected in series to a MOS transistor, the charge is accumulated in the photoelectric conversion element section, and the charge is accumulated in the gate of the first MOS transistor. A solid-state image pickup device comprising a scanning means for applying a voltage equal to or higher than a threshold value of a MOS transistor. 2. The solid-state image sensor according to claim 1, wherein the first MOS transistor is a depletion transistor. 3. The solid-state imaging device according to claim 1, wherein the channel concentration of the first MOS transistor is equal to the concentration of the substrate or well. 4. The solid-state image pickup device according to claim 1, wherein the gate length of the first MOS transistor is constituted by a minimum line width.