JPH0251317B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device and a method for driving the same.

The first is a schematic plan view of a conventional solid-state imaging device. In the figure, a large number of n-type photodiodes 1 are arrayed and formed on the light-receiving side main surface of a p-type semiconductor substrate, and are connected to the substrate in a pn junction. A vertical signal line 2 is provided close to one side of the row of photodiodes 1, and this vertical signal line 2 is made of an n-type diffusion layer and aluminum wiring. A scanning line selection gate 3 is provided between the photodiode 1 and the vertical signal line 2, and this scanning line selection gate 3 is controlled by a vertical shift register 4. An n-type diffused junction 5 is provided corresponding to one end of each vertical signal line 2 . A first transfer gate 7 controlled by a first control line 6 is provided between the connection point 5 and the vertical signal line 2. A control capacitor 9 is provided between the connection point 5 and the second control line 8 . Recessed horizontal corresponding to connection point 5
A CCD (charge coupled device) register 10 is provided. A second transfer gate 12 controlled by a third control line 11 is provided between the horizontal CCD register 10 and the connection point 5. A part of the second transfer gate 12 adjacent to the horizontal CCD register 10 is a buried type gate in which a buried layer exists, and the remaining part adjacent to the junction 5 is a surface type gate. An output section 13 is provided at the end of the horizontal CCD register 10 in the transfer direction. horizontal CCD
A charge absorption section including a sink control gate 14 and a sink drain 15 is provided adjacent to the register 10 on the opposite side from the second transfer gate 12. In FIG. 2, a is a partial cross-sectional view, b is a potential diagram, and c is a timing diagram for explaining how charges are transferred from the vertical signal line 2 to the horizontal CCD register 10. The transferred charges will be referred to as transferred charges. In the figure,
16 is a p-type semiconductor substrate, 17 is an n-type buried layer, and V ₁ , V ₂ , and V ₃ are the first
The potentials of the control line 6, the second control line 8, and the third control line 11 are set. t1 is before the transfer charge is transferred from the vertical signal line 2 to the horizontal CCD register 10, and the potential of the node 5 is larger than the potential of the vertical signal line 2. We are currently considering an n-channel device, and the charge is electrons. For this reason, a potential is defined as having the opposite sign of a potential, and in the case of a p-channel device, a charge is a hole, and a potential is defined as a potential. The first control line 6 is turned on, and part of the charge is transferred from the connection point 5 to the vertical signal line 2. In the case of an n-channel type, the on level refers to a high potential level. This partial charge will be called a priming charge. This situation was shown at t2.
It is. The priming charge is transferred from the connection point 5 to the vertical signal line 2
When the signal is transferred to the second control line 8, the second control line 8 becomes on level, and the potential of the connection point 5 becomes smaller. t3 shows this situation. Then, the priming charge and the transfer charge are transferred from the vertical signal line 2 to the connection point 5. t4 shows this situation. 1st
Control line 6 becomes off level. This situation is shown at t5. The second control line 8 becomes off level, and the potential of the connection point 5 increases. This situation is shown at t6. The third control line 11 is turned on, and only the transferred charges are transferred to the horizontal CCD register 10. At this time, the gate of the horizontal CCD register 10 adjacent to the second transfer gate 12 is at the on level. This situation was shown by t
It is 7. The third control line 11 becomes off level,
The transfer of the transfer charge from the vertical signal line 2 to the horizontal CCD register 10 is completed. This situation was shown by t
It is 8. This series of charge transfer will be referred to as priming transfer.

When the amount of incident light is large and an amount of charge larger than the maximum amount of accumulated charge in the accumulation region is generated, excess charge flows out from the accumulation region to the vertical signal line, and this outflow charge is mixed with signal charges in other accumulation regions. It appears as a white line on the playback screen and deteriorates the image quality. This phenomenon is called blooming phenomenon. This two-dimensional solid-state imaging device performs an imaging operation as described below in order to suppress the blooming phenomenon. During the horizontal retrace period, the surplus charge flowing into the vertical signal line 2 is transferred to the horizontal CCD register 10 by the above-mentioned priming transfer, and further transferred to the sink drain 15 via the sink control gate 14 which is at the on level. It is absorbed by the sink drain 15. The voltages applied to the respective gates and drains are determined so that the potential decreases stepwise from the second transfer gate 12 to the horizontal CCD register 10, the sink control gate 16, and the sink drain. Next, a pulse for sequentially selecting scanning lines from the vertical shift register 4 is applied to the scanning line selection gate 3, and each signal charge is transferred from the photodiode 1 to the vertical signal line 2. Vertical shift register 4
When the second pulse becomes off level, the next accumulation of signal charge begins. The signal charge is transferred to the horizontal CCD register 10 by the above-mentioned priming transfer,
Further, by the action of the horizontal CCD register 10, the signal is transferred to the output section 13 and taken out as an output signal. In this way, since the signal charges are read out after the surplus charges flowing to the vertical signal line 2 are transferred to the sink drain 15, the signal charges are not mixed with the surplus charges, and the blooming phenomenon should be suppressed. However, as described below, such a conventional driving method for a solid-state imaging device has the disadvantage that sufficient characteristics cannot be obtained in the above-mentioned priming water transfer and the blooming phenomenon cannot be suppressed.
The priming water transfer will be discussed below using a diagram. In FIG. 2, at t4, the MOS field effect transistor (MOSFET), which has the first transfer gate 7 as its gate, the vertical signal line 2 as its source, and the junction 5 as its drain, is operating in the saturation region or weak inversion region. Further, at t7, the second transfer gate 12 is the gate, the connection point 5 is the source, and the second transfer gate 12 is the gate.
The buried gate part of the drain is used as the drain.
MOSFETs also operate in the saturation region or weak inversion region. FIG. 3 shows a circuit in which only the essential parts are extracted in order to explain the operation of the above-mentioned MOSFET. Consisting of one MOSFET, the gate 18 is connected to a pulse source, a source capacitor 21 with a capacitance of Cs farad is provided between the source 19 and the substrate, and the drain 20 is connected to a drain power source 22. The potential of the substrate is set to 0V, and the potentials of the gate 18, source 19, and drain 20 are set to V _G volts, V _S volts, and V _D volts, respectively. Figure 4 shows
This shows the current characteristics of the MOSFET shown in Figure 3. The horizontal axis is the source potential, and the vertical axis is log ₁₀ I when the current flowing through the MOSFET is I ampere. At this time, the gate potential is on level 5 volts,
The drain power supply 22 was set to 8 volts, which is sufficiently larger than that. Let the threshold voltage be V _T volts. However, the threshold voltage depends on the source voltage. V _S
When V S is smaller than V _G −V _T , the MOSFET operates in the saturation region of the strong inversion region, and when V _S is larger than V _G − V _T , the MOSFET operates in the weak inversion region. As V _S increases, current I decreases. Especially in the weak inversion region, it decreases logarithmically. The elementary charge is q coulombs,
Assuming that the Boltzmann constant is k coulomb volts/degree, the absolute temperature of the device is T degrees, and Io is a constant, the current characteristic equation in the weak inversion region is I=Io exp (-qVs/kT) (1). The size of Io is determined by the gate voltage V _G and MOSFET
It depends on the size etc. Now, in the circuit shown in FIG. 3, the temporal change in the source potential V _S when V _G is on level will be investigated in the case of weak inversion. Since the discharge from the source capacitance is the MOSFET current, V _S follows the following equation.

CsdVs/dt=I=Io exp(-qVs/kT) (2) Equation (2) can be integrated, and the source potential at t=0 seconds
When V _S is Vo, Vs (t; Vo) = kT/qlog {exp (qVo/kT) + kTCst/qIo} (3). Assume that the gate 18 is periodically turned on for an on-time of Ton seconds and that −Q coulombs of electrons are externally injected into the source capacitance each time the gate 18 is at the off level. In this case, if the source potential when the gate 18 changes from on level to off level is V _R , then
In steady state, Vs (Ton; V _R −Q/C _S )=V _R (4) holds true. Solving for V _R , V _R = kT/qlogkTCsTon/qIo−kT/qlog{l−exp(
− qQ/kTCs)} (5). It shows the reset potential V _R of the source capacitor after transfer when the amount of charge transferred is -Q.
Let the first term be _VRO . Equation (5) is illustrated in Figure 5. - When Q is sufficiently large compared to kTCs/q, V _R becomes a constant value of V _RO ;
– When Q becomes smaller than kTCs/q, V _R suddenly becomes
It can be seen that it is larger than V _RO . The above discussion was limited to the case of weak inversion, but the case where the gate 18 operates in the saturation region for a part of the time Ton that it is on level and operates in the weak inversion region for the remaining time. However, the above conclusion can be applied if there is a certain amount of time to operate in the weak inversion region. Furthermore, although we have discussed the case where the amount of charge injected into the source capacitance 21 -Q is constant, the case where -Q varies also.
Show similar properties.

Apply the above conclusion to priming water transfer. First t
4, in a MOSFET in which the first transfer gate 7 is the gate, the vertical signal line 2 is the source, and the connection point 5 is the drain, -Q is the surplus charge and the priming charge. When the capacitance of the vertical signal line 2 is _CL , if the absolute value of the amount of priming charge is larger than kTC _L /q, the vertical signal line 2 is reset to a substantially constant potential and does not cause the blooming phenomenon. Next, at t7, in the MOSFET in which the second transfer gate 12 is the gate, the junction 5 is the source, and the buried gate part of the second transfer gate 12 is the drain, -Q is only the surplus charge. The surplus charge varies depending on each vertical signal line 2 and also in time, and when the capacitance of the node 5 is Cc, the absolute value of the surplus charge can be larger or smaller than kTCc/q. If the device temperature is room temperature, kT/q is approximately 0.027 volts. For this reason, the reset potential of the junction 5 varies depending on the amount of surplus charge, and the amount of signal charge transferred next has a correspondingly different effect, causing the blooming phenomenon. As described above, conventional solid-state imaging devices have the disadvantage that the blooming phenomenon cannot be sufficiently suppressed. Although the description has been made regarding an n-channel type solid-state imaging device, the same applies to a p-channel type solid-state imaging device.

The purpose of this invention is to eliminate the above-mentioned drawbacks,
An object of the present invention is to provide a solid-state imaging device and a driving method thereof that can provide a good reproduction screen.

According to the present invention, a large number of vertical signal lines for vertically transferring signal charges from each arrayed photodiode, a connection point provided corresponding to the vertical signal line, and the vertical signal line a first transfer gate controlled by a first control line provided between the connection point and the connection point; a control capacitor provided between the connection point and the second control line; a horizontal CCD (charge-coupled device) register provided correspondingly; a second transfer gate controlled by a third control line provided between the horizontal CCD register and the connection point; A charge absorption mechanism including a sink control gate and a sink drain provided adjacent to a charge transfer channel after the transfer gate, a diffusion layer provided corresponding to the connection point and connected to a power source, and this diffusion layer. and a control gate provided between the connecting point and the connecting point.

Further, according to the present invention, in the device, at least when transfer of surplus charge from the vertical signal line to the junction is completed, the control gate is turned on, and the potential of the junction is set to the potential of the power supply. , there is obtained a method for driving a solid-state imaging device, characterized in that part of the charge is transferred from the junction to the charge absorption mechanism.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 6 is a schematic plan view of a solid-state imaging device according to an embodiment of the present invention. The same symbols in FIG. 1 and FIG. 6 indicate the same components. In this device, a diffusion layer 24 connected to a power source 23 is provided corresponding to the connection point 5, and a control gate 25 is provided between the diffusion layer 24 and the connection point 5.

A method for driving a solid-state imaging device according to an embodiment of the present invention will be described. The surplus charge flowing to the vertical signal line 2 is transferred from the vertical signal line 2 to the connection point 5 by the priming transfer operation from t1 to t4. When the second control line becomes on level, the control gate 25 is turned on level, and the potential of the connection point 5 is changed to the potential of the power supply 23.
Set to V _A bolt. The control gate 25 is operated in the linear region of the inversion region. When the transfer of surplus charge and priming charge from the vertical signal line 2 to the connection point 5 is completed and the first control line 6 becomes OFF level,
A little later than that, the control gate 25 becomes off level. It is necessary that the first control gate 25 is turned on at least when the transfer of surplus charge and priming charge from the vertical signal line 2 to the connection point 5 is completed. When there is a large amount of surplus charge flowing out to the vertical signal line 2, the charge moves from the junction 5 to the power supply 23, and conversely, when there is little surplus charge, the charge moves from the connection point 5 to the power supply 23.
The charge moves to the connection point 5. After the first transfer gate 7 and control gate 25 are turned off, the second control line 8 is turned off. The potential of this easy-to-connect contact 5 decreases by V _B volts, (V _A −V _B )
Suppose you become a bolt. The potential of the node 5 reset by the operation of the weak inversion region of the second transfer gate 12 at the timing t7 is equal to or greater than _VRO . V _A − V _B is smaller than this V _RO ,
The potential V _A of the power supply 23 is selected so that (V _RO −V _A −V _B )×Cc is larger than kTCc/q. Then, the second transfer gate 12 at timing t7
from the junction 5 through the horizontal CCD register 10
When the charge transfer to is completed, the potential of the junction 5 has been reset to approximately _VRO . The charges transferred to the horizontal CCD register 10 are absorbed by the charge absorbing mechanism. In this way, the vertical signal line 2 and the connection point 5 are each reset to a constant potential, so that
The next time the signal charge is transferred, it is not affected by the surplus charge, and the blooming phenomenon is suppressed.

Even within the same wafer, the threshold potential of MOSFETs varies by about 0.05 volts. As the threshold potential increases, the reset potential also increases accordingly. The potential of the power supply 23 is set for the one with the smallest threshold potential among the plurality of first transfer gates 7 .

Due to variations in the threshold potential of MOSFETs,
The reset potentials of each vertical signal line 2 and each connection point 5 vary. However, one vertical signal line 2 or 1
Focusing on each connection point 5, since it is always reset to a constant potential, variations in the reset potential do not affect the output signal.

Even if the charge absorbing mechanism consisting of the sink control gate 14 and the sink drain 15 is provided adjacent to at least the buried gate portion of the second transfer gate 12, the same effect of the present invention can be obtained. In this case, the charge transferred to the sink drain 15 is horizontal
2nd transfer gate 1 without passing through CCD register 10
The signal is transferred from the buried gate portion of No. 2 to the sink drain 15 via the sink control gate 14.

The signal charge may be transferred from the photodiode 1 to the vertical signal line 2 at any time after the vertical signal line 2 is reset.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a conventional solid-state imaging device.
Figure 2 shows horizontal CCD register 1 from vertical signal line 2.
Figure 3 is a partial cross-sectional view, potential diagram, and timing diagram to explain the transfer of charge to 0.
A circuit for examining the characteristics when the MOSFET is operating in the saturation region or weak inversion region of the strong inversion region, Figure 4 is a current characteristic diagram of the MOSFET, and Figure 5 is a reset due to the function of the weak inversion region of the MOSFET. FIG. 6, a diagram showing characteristics, is a schematic plan view of a solid-state imaging device according to an embodiment of the present invention. 1...Photodiode, 2...Vertical signal line,
5... Connection point, 6... First control line, 7... First transfer gate, 8... Second control line, 9... Control capacity,
10...Horizontal CCD register, 11...Third control line, 12...Second transfer gate, 14...Sink control gate, 15...Sink drain, 2
3...Power supply, 24...Diffusion layer, 25...Control gate.

Claims (1)

[Claims] 1. A large number of vertical signal lines for vertically transferring signal charges from each arrayed photodiode, a connection point provided corresponding to the vertical signal line, and a connection point provided corresponding to the vertical signal line. a first transfer gate controlled by a first control line provided between the signal line and the connection point; a control capacitor provided between the connection point and the second control line; and a control capacitor provided between the connection point and the second control line; a horizontal CCD (charge-coupled device) register provided corresponding to the contact point; a second transfer gate controlled by a third control line provided between the horizontal CCD register and the connection point; a charge absorption mechanism including a sink control gate and a sink drain provided adjacent to a charge transfer channel after the second transfer gate;
A solid-state imaging device comprising: a diffusion layer provided corresponding to the connection point and connected to a power source; and a control gate provided between the connection point. 2. A large number of vertical signal lines for vertically transferring signal charges from each arrayed photodiode, a connection point provided corresponding to the vertical signal line, and the vertical signal line and the connection point. a first transfer gate controlled by a first control line provided between the first transfer gate, a control capacitor provided between the connection point and the second control line, and a control capacitor provided corresponding to the connection point; a horizontal CCD (charge coupled device) register, a second transfer gate controlled by a third control line provided between the horizontal CCD register and the connection point, and a second transfer gate controlled by a third control line provided between the horizontal CCD register and the connection point; a charge absorption mechanism including a sink control gate and a sink drain provided adjacent to the charge transfer channel;
In the solid-state imaging device, the solid-state imaging device includes a diffusion layer provided corresponding to the connection point and connected to a power source, and a control gate provided between the diffusion layer and the connection point. When the transfer of the excess charge to the contact is completed, the control gate is turned on, the potential of the junction is set to the potential of the power supply, and a portion of the charge is transferred from the junction to the charge absorption mechanism. A driving method for a solid-state imaging device.