CN115799379A - Multi-grid composite dielectric grid photosensitive detector and working method - Google Patents
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Abstract
The invention discloses a multi-grid composite dielectric grid photosensitive detector and a working method. The photosensitive detector comprises a photosensitive transistor and a reading transistor which are formed on the same substrate, the photosensitive transistor and the reading transistor share a composite dielectric gate, the composite dielectric gate comprises a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate, the reading transistor is provided with a source end and a drain end, a second bottom dielectric layer and a selection gate are further sequentially arranged on the substrate of the reading transistor, and the second bottom dielectric layer, the selection gate and the composite dielectric gate are independent. The read-out mode of the photosensitive detector comprises a mode of reading current in a linear region or a mode of following a read voltage by a source. The composite dielectric gate photosensitive detector based on the multi-gate structure provides noise reduction and selection of multiple reading modes and working modes for the traditional composite dielectric gate photosensitive detector, and provides more choices and functions for the composite dielectric gate photosensitive detector in imaging application.
Description
Technical Field
The invention relates to a novel photosensitive detector structure, in particular to a multi-grid composite dielectric grid photosensitive detector and provides a plurality of working methods for the composite dielectric grid photosensitive detector.
Background
The photosensitive detector as a photoelectric signal converter can effectively convert optical signals into electric signals and further display images, and is widely applied to daily life, the field of security protection, the field of national defense and the like.
The photosensitive detector based on the composite dielectric gate has the advantages of combining two photosensitive detectors of CCD and CMOS-APS due to the structure of the photosensitive detector, and is expected to become a mainstream photosensitive detector of a new generation. However, the read transistor of a typical photosensitive detector based on a composite dielectric gate generally has only one gate, which greatly limits the operation mode of the photosensitive detector. Such detectors typically read using a sweeping ramp voltage, which presents difficulties in circuit design and functional applications.
Disclosure of Invention
In view of the defects in the prior art, the invention improves the structure of the photosensitive detector based on the composite dielectric grid, changes the structure into a multi-grid structure and can provide more working methods for the detector.
The technical scheme adopted by the invention is as follows:
a multi-gate composite dielectric gate photosensitive detector comprises a photosensitive transistor and a reading transistor which are formed on the same substrate, wherein the photosensitive transistor and the reading transistor share one composite dielectric gate, the composite dielectric gate comprises a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate, and the reading transistor is provided with a source end and a drain end.
The photosensitive transistor comprises a first composite dielectric gate, and the reading transistor comprises a second composite dielectric gate, a source end and a drain end, and is characterized in that the first composite dielectric gate and the second composite dielectric gate share a bottom dielectric layer, a charge coupling layer and a top dielectric layer, the uppermost part of the first composite dielectric gate is a control gate, the uppermost part of the second composite dielectric gate is a selection gate, and the bottom dielectric layer and the selection gate of the second composite dielectric gate form a semi-surrounding structure for the charge coupling layer and the top dielectric layer; the selection gate and the control gate are two independent parts.
The invention provides a working method of the multi-grid composite dielectric grid photosensitive detector, which comprises the following steps:
(1) Resetting: applying negative voltage to the control grid, grounding the substrate, and resetting electrons collected by a photosensitive transistor of the photosensitive detector;
(2) Exposure: applying positive voltage to the control gate, and grounding the substrate or applying negative voltage; when light is irradiated, when the energy of photoelectrons is larger than the forbidden bandwidth of the substrate, an electron hole pair is excited, the generated photoelectrons are collected by the photosensitive transistor under the action of an electric field of the depletion region, the potential of the photosensitive transistor is changed and is coupled to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, and therefore the reading transistor is controlled;
(3) Reading: in the reading stage, positive voltage is applied to the control grid, negative voltage or grounding is applied to the substrate, positive voltage is applied to the drain terminal to enable the reading transistor to work in a linear region or a saturated region, the source terminal is grounded or connected with a current source, and positive voltage is applied to the selection grid to enable the reading transistor to be started to read current of the drain terminal or voltage of the source terminal.
Further, in the readout stage in the step (3), a high voltage is applied to both the select gate and the control gate, and the voltage of the select gate and the control gate should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full-well state, so that the reading transistor is in the on state, a low voltage is applied to the drain terminal, the source terminal is grounded, and the voltage applied to the drain terminal should enable the reading transistor to work in the linear region when the photosensitive detector is in the full-well state, and at this time, photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, so that the potential of the charge coupling layer is changed, and the drain terminal current of the reading transistor is regulated and controlled, thereby further realizing the quantization of the optical signal.
Further, an imaging chip is composed of a plurality of composite dielectric grid photosensitive detectors, and the imaging chip has multiple working mode selections: (a) normal operating mode: the control grid is connected with positive high voltage, and the substrate is grounded; (b) high dynamic range mode: the control grid of the photosensitive detector is applied with positive high voltage, and the substrate is connected with negative high voltage, so that the depletion region of the photosensitive transistor is enlarged, and larger full-well capacity is obtained; (c) very high dynamic range mode: the control grid of the photosensitive detector is applied with positive high voltage, the substrate is connected with negative high voltage, and the photosensitive detectors are combined, at this time, the full-well capacity is further enlarged, and high-frame-rate reading is carried out.
Further, in the readout stage of step (3), the select gate and the control gate are both applied with high voltage, the voltage of the select gate and the control gate should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in a full-well state, so that the reading transistor is in an on state, the substrate is grounded, the drain terminal is applied with high voltage, the source terminal is connected with a current source, the voltage applied to the drain terminal should make the reading transistor work in a saturation region when the photosensitive detector is in an empty-well state, so that the reading transistor works in a source follower mode, and at this time, photoelectrons collected by the photosensitive transistor are coupled to a charge coupling layer of the composite dielectric gate, so that the potential of the charge coupling layer is changed, and the source terminal voltage of the reading transistor is regulated and controlled, thereby further realizing quantization of the optical signal.
The detector of the invention provides multiple reading mode selections for the photosensitive detector at the device level, and the multi-gate structure can increase the channel length of the reading transistor, so that the gate oxide area is increased, and 1/f noise and RTN noise are reduced. The invention uses the multi-gate structure, because the device is additionally controlled by the selection gate, when the selection gate of the device is closed and the high voltage is applied to the control gate, the reading transistor can not be started, thus providing noise reduction and a plurality of reading modes and working modes for the traditional composite dielectric gate photosensitive detector and providing more selections and functions for the photosensitive detector in imaging application.
Drawings
FIG. 1 is a schematic structural diagram of a multi-gate composite dielectric gate photosensitive detector in example 1;
FIG. 2 is a schematic structural diagram of a cross section of a multi-gate composite dielectric gate photosensitive detector AA' in FIG. 1;
FIG. 3 is a schematic structural diagram of a cross section of a multi-gate composite dielectric gate photosensitive detector BB' in FIG. 1;
FIG. 4 is a schematic structural diagram of a cross section of a multi-gate composite dielectric gate photosensitive detector CC' in FIG. 1;
FIG. 5 is a schematic energy band diagram of the read transistor DD' of FIG. 4 in different operating states at the gate-oxide interface;
FIG. 6 is a schematic diagram of one readout mode of the photosensitive detector;
FIG. 7 is a schematic diagram of another read-out mode of the photosensitive detector;
FIG. 8 is a schematic diagram of layout design of a multi-gate composite dielectric gate photosensitive detector;
FIG. 9 is a schematic structural diagram of a multi-gate composite dielectric gate photosensitive detector in example 2;
FIG. 10 is a schematic structural diagram of a cross section of a multi-grid composite dielectric grid photosensitive detector EE' shown in FIG. 9;
FIG. 11 is a schematic structural diagram of a cross section of a multi-gate composite dielectric gate photosensitive detector FF' in FIG. 9;
FIG. 12 is a schematic structural diagram of a cross section of a multi-grid composite dielectric grid photosensitive detector GG' in FIG. 9.
Detailed Description
Example 1
In this embodiment, a multi-gate composite dielectric gate photosensitive detector as shown in fig. 1 is used, and its structure is: the light-sensitive transistor-based charge coupled device comprises a light-sensitive transistor 101 and a reading transistor 102 which are formed above the same P-type semiconductor substrate, wherein the light-sensitive transistor 101 and the reading transistor 102 are separated by a shallow trench isolation 103, the light-sensitive transistor 101 and the reading transistor 102 share a composite dielectric gate, the composite dielectric gate sequentially comprises a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107 from bottom to top, and the control gate 107 on the top layer controls the reading transistor 102 and the light-sensitive transistor 101 together. In addition, the read transistor 102 is additionally controlled by a select gate 109, a second bottom dielectric layer 108 is disposed under the select gate 109, and the read transistor 102 further includes two ports, i.e., a source terminal 110 and a drain terminal 111. The light sensing transistor 101 is used for sensing light and converting an optical signal into an electric signal, the reading transistor 102 is used for reading the electric signal, and the reading transistor 102 is controlled by two gates of the selection gate 109 and the control gate 107, so that the overall channel length of the reading transistor 102 is longer than that controlled by only one gate, the noise of the reading transistor is reduced, and multiple reading modes are allowed.
For the AA' section in fig. 1, as shown in fig. 2, the structure is: the light-sensitive transistor 101 and the reading transistor 102 are formed above the same P-type semiconductor substrate, the light-sensitive transistor 101 and the reading transistor 102 are separated by a shallow trench isolation 103, the light-sensitive transistor 101 is controlled by a composite dielectric gate, the composite dielectric gate sequentially comprises a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107 from bottom to top, in addition, the reading transistor 102 is controlled by a selection gate 109, and a second bottom dielectric layer 108 is arranged below the selection gate 109. In this cross section, the reading transistor 102 is not affected by the charge coupling layer 105, and therefore, in this cross section, the optical signal collected by the light sensing transistor 101 does not affect the reading transistor 102.
For the BB' section in fig. 1, as shown in fig. 3, the structure is: the CMOS image sensor comprises a photosensitive transistor 101 and a reading transistor 102 which are formed above the same P-type semiconductor substrate, wherein the photosensitive transistor 101 and the reading transistor 102 are separated by a shallow trench isolation 103, and the photosensitive transistor 101 and the reading transistor 102 are simultaneously controlled by a composite dielectric gate, wherein the composite dielectric gate sequentially comprises a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107 from bottom to top. In this cross section, the reading transistor 102 is affected by the charge coupling layer 105, and therefore, in this cross section, the light signal collected by the light sensing transistor 101 changes the drain terminal current or the source terminal voltage of the reading transistor 102, so that photoelectric conversion is realized during readout.
For the section CC' in fig. 1, as shown in fig. 4, the structure is: the reading transistor 102 is formed above a P-type semiconductor substrate, the reading transistor 102 is simultaneously controlled by a control gate 107 and a selection gate 109, a second bottom dielectric layer 108 is arranged below the selection gate 109, and the composite dielectric gate integrally consists of a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and the control gate 107. In this cross section, the reading transistor 102 is affected by the selection gate 109 and the charge coupling layer 105, and therefore, in this cross section, the operating state of the reading transistor 102 is determined by the voltage of the selection gate 109 and the potential of the charge coupling layer 105 and the substrate voltage, wherein the potential of the charge coupling layer 105 is determined by the number of collected photoelectrons of the photo-sensing transistor 101 and the voltage of the control gate 107 and the substrate voltage.
The switching state of the read transistor 102 is influenced by the selection gate 109 and the charge coupling layer 105 together, and the energy band diagram of the channel cross section DD' is shown in fig. 5: FIG. 5 (a) shows the state when the select gate 109 is turned off, and during the process of electron flow from the source to the drain, a higher barrier is encountered under the select gate to block the electron flow, thereby turning off the read transistor 102; fig. 5 (b) shows a state where the select gate 109 is turned on, and at this time, an inversion layer is formed on the channel surface under the select gate, the barrier disappears, and electrons can flow from the source terminal to the drain terminal, thereby turning on the read transistor 102. The high voltage signal of the select gate 109 ensures that the read transistor 102 is turned on completely, and the source-drain current or source-side voltage of the read transistor is determined by the charge coupling layer 105 and satisfies the square law relationship of the MOSFET.
In this embodiment, a schematic diagram of a readout mode shown in fig. 6 may be used to perform readout of an optical signal, a voltage of 3.3V (a specific operating voltage is determined by circuit design and is generally a power supply voltage) is applied to a control gate CG, a voltage of 0V or-3V (a specific operating voltage is determined by circuit design and is generally grounded, and a negative high voltage may expand a full well capacity) is applied to a substrate Vb, a voltage of 0.2V is applied to a drain terminal Vd (a specific operating voltage is determined by circuit design and is required to operate a read transistor in a linear region), a voltage of 0V is applied to a source terminal Vs (a specific operating voltage is determined by circuit design and is generally grounded), a gate MG is selected to apply a high-voltage signal to turn on the read transistor, and a source-drain current is read on a Column readout circuit Column Bus; in this readout mode, the imaging chip can have multiple working mode options: 1. and (3) a normal working mode: the control gate CG is connected with positive high voltage (generally higher than 3V, the larger the voltage is, the larger the full well is), the substrate Vb is grounded, and at the moment, the full well of the device is smaller, the dynamic range is smaller, and the device is suitable for being used in an environment without strong light; 2. high dynamic range mode: the control grid CG of the photosensitive detector is applied with positive high voltage, and the substrate Vb is connected with negative high voltage, so that the depletion region of the photosensitive transistor is enlarged, and larger full-well capacity is obtained, the dynamic range and the peak signal-to-noise ratio of the device are improved, and the photosensitive transistor is suitable for being used in a long-exposure or highlight environment; 3. very high dynamic range mode: the control grid CG of the photosensitive detector is applied with positive high voltage, the substrate Vb is connected with negative high voltage, and a plurality of pixels are combined (the specific number of the pixels is determined by layout design, typically 4 pixels are combined into 1 pixel), at this time, the full-well capacity is further enlarged, the dynamic range and the peak signal-to-noise ratio of the device can be further improved, and the resolution of the imaging chip can be reduced due to the combination, so that high-frame-rate reading can be carried out, and the high-frame-rate reading device is suitable for being used in a long-exposure or strong-light environment.
In this embodiment, a schematic diagram of a readout manner as shown in fig. 7 may be used to perform readout of an optical signal, where a voltage of 3.3V (a specific operating voltage is determined by circuit design and is generally a power supply voltage) is applied to the control gate CG, a voltage of 0V (a specific operating voltage is determined by circuit design and is generally grounded) is applied to the substrate, a voltage of 3.3V is applied to the drain (a specific operating voltage is determined by circuit design and needs to make the read transistor operate in a saturation region), the source end is connected to a current source to form a source follower structure, the select gate MG provides a high-voltage signal to turn on the read transistor, and the source end voltage is read on the Column readout circuit Column Bus. When the photosensitive detector adopts the reading mode, the advantages are that the drain terminal is connected with positive high voltage, the substrate is generally grounded to avoid avalanche of a PN junction between the drain terminal and the substrate, so that the reverse bias voltage of the PN junction is small enough, and at the moment, the source terminal of the reading transistor is connected with a current source to form a mode of a source follower, so that the voltage of the source terminal of the reading transistor 102 of the photosensitive detector is directly read by a reading circuit, the light signal collected by the photosensitive transistor can be directly reflected, the reading speed of the whole device is improved by the reading mode, and the reading mode is suitable for being applied to a high frame rate mode.
In this embodiment, switching between different resolutions, switching between dynamic ranges, and switching between frame rates may be implemented by using a layout as shown in fig. 8 to implement a read circuit shared by multiple devices and by using timing control. If every two columns of pixels share a column of reading circuit, and every two rows of pixels are reset, exposed and read simultaneously, 2 × 2 combination can be realized; if every four rows of pixels share one row of readout circuits and every four rows are reset, exposed and read simultaneously, 4 multiplied by 4 combination can be realized; if each row is reset, exposed and read independently, full sampling can be realized, and the maximum resolution is achieved.
Example 2
For multi-gate composite dielectric gate photosensitive detector pixels with typical dimensions below 0.5um, it is difficult to fabricate two separate gates in parallel above the read transistor at a 65nm or 50nm process node due to process rule limitations for which the present embodiment may utilize a multi-gate photosensitive detector structure as shown in fig. 9. The structure is that the structure comprises a photosensitive transistor 901 and a reading transistor 902 which are formed on the same substrate, the photosensitive transistor 901 and the reading transistor 902 are separated by a shallow trench isolation 903, the photosensitive transistor 901 and the reading transistor 902 share a bottom dielectric layer 904, a charge coupling layer 905 and a top dielectric layer 906, a control gate 907 is arranged above the top dielectric layer 906 of the photosensitive transistor 901, a selection gate 908 is arranged above the bottom dielectric layer 904 of the reading transistor 902, the charge coupling layer 905, the top dielectric layer 906 and the selection gate 908 are arranged partially in sequence, the control gate 907 and the selection gate 908 are two independent parts, and in addition, the reading transistor 902 further comprises two ports of a source end 909 and a drain end 910.
For the section EE' in fig. 9, as shown in fig. 10, the structure is: the high-speed reading transistor comprises a photosensitive transistor 901 and a reading transistor 902 which are formed on the same P-type semiconductor substrate, the photosensitive transistor 901 and the reading transistor 902 are separated by a shallow trench isolation 903, the photosensitive transistor 901 and the reading transistor 902 are controlled by a composite dielectric gate, the composite dielectric gate sequentially comprises a bottom dielectric layer 904, a charge coupling layer 905, a top dielectric layer 906, a control gate 907 and a selection gate 908 from bottom to top, the control gate 907 is above the photosensitive transistor 901, and the selection gate 908 is above the reading transistor 902. In this cross section, the potential of the charge coupling layer 905 is determined by the number of photoelectrons collected by the light sensing transistor 901, the voltage of the control gate 907, the voltage of the select gate 908, and the substrate voltage.
For the section FF' in fig. 9, as shown in fig. 11, the structure is: the transistor comprises a photosensitive transistor 901 and a reading transistor 902 which are formed above the same P-type semiconductor substrate, the photosensitive transistor 901 and the reading transistor 902 are separated by a shallow trench isolation 903, and the photosensitive transistor 901 is controlled by a composite dielectric gate, wherein the composite dielectric gate sequentially comprises a bottom dielectric layer 904, a charge coupling layer 905, a top dielectric layer 906 and a control gate 907 from bottom to top, and in addition, the upper part of the reading transistor 902 is only controlled by a selection gate 908. In this cross section, the reading transistor 902 is not affected by the charge coupling layer 905, and therefore, in this cross section, the optical signal collected by the light sensing transistor 901 does not affect the reading transistor 902.
For the section GG' in fig. 9, as shown in fig. 12, the structure is: comprises a read transistor 902 formed over a P-type semiconductor substrate, wherein a select gate 908 over a bottom dielectric layer 904 forms a semi-enclosed structure for a charge coupling layer 905 and a top dielectric layer 906. The reading transistor 902 is commonly controlled by the potential of the charge coupling layer 905 and the potential of the selection gate 908, wherein the potential of the charge coupling layer 905 is determined by the number of collected photoelectrons of the photosensitive transistor 901, the voltage of the control gate 907, and the voltage of the selection gate 908 and the substrate voltage.
Claims (6)
1. A multi-gate composite dielectric gate photosensitive detector comprises a photosensitive transistor and a reading transistor which are formed on the same substrate, wherein the photosensitive transistor and the reading transistor share one composite dielectric gate, the composite dielectric gate comprises a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate, and the reading transistor is provided with a source end and a drain end.
2. A multi-gate composite dielectric gate photosensitive detector comprises a photosensitive transistor and a reading transistor which are formed on the same substrate, wherein the photosensitive transistor comprises a first composite dielectric gate, and the reading transistor comprises a second composite dielectric gate, a source end and a drain end; the selection gate and the control gate are two independent parts.
3. A method of operating a multi-gate composite dielectric gate photosensitive detector as claimed in claim 1 or 2, wherein the method comprises the steps of:
(1) Resetting: applying negative voltage to the control grid, grounding the substrate, and resetting electrons collected by a photosensitive transistor of the photosensitive detector;
(2) Exposure: applying positive voltage to the control gate, and grounding the substrate or applying negative voltage; when light is irradiated, when the energy of photoelectrons is larger than the forbidden bandwidth of the substrate, an electron hole pair is excited, the generated photoelectrons are collected by the photosensitive transistor under the action of an electric field of the depletion region, the potential of the photosensitive transistor is changed and is coupled to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, and therefore the reading transistor is controlled;
(3) Reading: in the reading stage, positive voltage is applied to the control gate, negative voltage or grounding is applied to the substrate, positive voltage is applied to the drain terminal to enable the reading transistor to work in a linear region or a saturation region, the source terminal is grounded or connected with a current source, and positive voltage is applied to the select gate to enable the reading transistor to be started to read the current of the drain terminal or the voltage of the source terminal.
4. The operating method according to claim 3, wherein in the readout stage of step (3), the select gate and the control gate are both applied with high voltage, and the voltage is higher than the threshold voltage of the read transistor when the photosensitive detector is in the full-well state, so that the read transistor is in the on state, the drain terminal is applied with low voltage, the source terminal is grounded, and the drain terminal is applied with voltage, so that the read transistor operates in the linear region when the photosensitive detector is in the full-well state, and at this time, photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, change the potential thereof, and regulate and control the drain terminal current of the read transistor, thereby further realizing quantization of optical signals.
5. The working method of claim 4, wherein an imaging chip is composed of a plurality of composite dielectric gate photosensitive detectors, and the imaging chip has a plurality of working mode selections: (a) normal operating mode: the control grid is connected with positive high voltage, and the substrate is grounded; (b) high dynamic range mode: the control grid of the photosensitive detector is applied with positive high voltage, and the substrate is connected with negative high voltage, so that the depletion region of the photosensitive transistor is enlarged, and larger full-well capacity is obtained; (c) very high dynamic range mode: the control grid of the photosensitive detector is applied with positive high voltage, the substrate is connected with negative high voltage, and the photosensitive detectors are combined, at this time, the full-well capacity is further enlarged, and high-frame-rate reading is carried out.
6. The method according to claim 3, wherein in the readout stage of step (3), the select gate and the control gate are both applied with high voltages, and the voltages are higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full-well state, so that the reading transistor is in the on state, the substrate is grounded, the drain terminal is applied with high voltages, the source terminal is connected with the current source, and the drain terminal is applied with voltages, so that the reading transistor operates in the saturation region when the photosensitive detector is in the empty-well state, so that the reading transistor operates in the source follower mode, and at this time, the photoelectrons collected by the photosensitive transistor couple to the charge coupling layer of the composite dielectric gate, change the potential thereof, and regulate and control the source terminal voltage of the reading transistor, thereby further realizing quantization of the optical signals.
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