JPH038152B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for driving a solid-state imaging device.

FIG. 1 is a diagram for explaining a conventional method of driving a solid-state imaging device, and is a schematic plan view of the solid-state imaging device. Although the following description will be made only regarding the n-channel type device, the same applies to the p-channel type device. In the figure, a large number of n-type photodiodes 1 are arranged on the main surface on the light-receiving side of a p-type semiconductor substrate, and are connected to the substrate in a pn junction. A vertical signal line 2 is provided adjacent to one side of the column of photodiodes 1, and this vertical signal line 2 is made of an n-type diffusion layer and aluminum wiring. A scanning line selection gate 3 is provided between the photodiode and the vertical signal line 2, and this scanning line selection gate 3 is controlled by a vertical shift register 4. An n-type diffused region 5 is provided corresponding to one end of each vertical signal line 2 . A first transfer gate 7 controlled by a first control line 6 is provided between this region 5 and the vertical signal line 2 . A control capacitor 9 is provided between the region 5 and the second control line 8 . An embedded horizontal CCD (charge-coupled device) register 10 is provided corresponding to the region 5 . Between this horizontal CCD register 10 and area 5, a third
Second transfer gate 1 controlled by control line 11
2 is provided. A part of the second transfer gate 12 adjacent to the horizontal CCD register 10 is a buried gate in which a buried layer exists;
The remaining portion adjacent to is a surface type gate. horizontal
An output section 13 is provided at the end of the CCD register 10 in the transfer direction. Horizontal CCD register 10
On the other hand, a charge absorbing section including a sink control gate 14 and a sink drain 15 is provided adjacent to the second transfer gate 12 on the opposite side.

In Figure 2, from the vertical signal line 2 to the horizontal CCD
FIG. 2 is a diagram for explaining how charges are transferred to the register 10, in which a is a partial cross-sectional view, b is a potential diagram, and c is a timing diagram. The transferred charges will be referred to as transferred charges. In the figure, 16 is a p-type semiconductor substrate, 17 is an n-type buried layer, and V ₁ , V ₂ , and V ₃ are the first control line 6, the second control line 8, and the third control line, respectively. 11 potential. t ₁ is the horizontal CCD register 10 from the vertical signal line 2
This is before the transfer charges are transferred to the area 5, and the potential of the region 5 is larger than the potential of the vertical signal line 2. We are currently considering an n-channel device, and the charge is electrons. For this reason, a potential is defined as a potential with the opposite sign, and in the case of a p-channel device, the charge is a hole, and the potential is defined as a potential. The first control line 6 is turned on, and part of the charge is transferred from the region 5 to the vertical signal line 2. In the case of an n-channel type, the on level refers to a high potential level. This partial charge will be called a priming charge. t ₂ shows this situation. When the priming charge is transferred from the region 5 to the vertical signal line 2, the second control line 8 becomes on level, and the potential of the region 5 becomes smaller. _t3 shows this situation. Then, the priming charge and the transfer charge are transferred from the vertical signal line 2 to the region 5. t ₄ shows this situation. The first control line 6 becomes off level. _t5 shows this situation.
The second control line 8 becomes off level, and the potential of the region 5 increases. This situation is shown in _t6
It is. The third control line 11 is turned on, and only the transferred charges are transferred to the horizontal CCD register 10. At this time, the area adjacent to the second transfer gate 12
The gate of CCD register 10 is on level.
T ₇ shows this situation. Third control line 11
becomes off level, and the horizontal signal line is lower than the vertical signal line 2.
The transfer of the transfer charges to the CCD register 10 ends.
_t8 shows this situation. This series of charge transfer is called priming transfer.

When the amount of incident light is large and an amount of charge larger than the maximum amount of accumulated charge in the accumulation region is generated, excess charge flows out from the accumulation region to the vertical signal line, and this outflow charge is mixed with signal charges in other accumulation regions. It appears as a white line on the playback screen and deteriorates the image quality. This phenomenon is called blooming phenomenon. This two-dimensional solid-state imaging device performs an imaging operation as described below in order to suppress the blooming phenomenon. During the horizontal retrace period, the surplus charge flowing into the vertical signal line 2 is transferred to the horizontal CCD register 10 by the above-mentioned priming transfer, and further transferred to the sink drain 15 via the sink control gate 14 which is at the on level. It is absorbed by the sink drain 15. The voltages applied to the respective gates and drains are determined so that the potential decreases stepwise from the second transfer gate 12 to the horizontal CCD register 10, sink control gate 14, and sink drain 15. Next, a pulse for sequentially selecting a scanning line from the vertical shift register 4 is applied to the scanning line selection gate 3, and each signal charge is transferred from the photodiode 1 to the vertical signal line 2. When the pulse from the vertical shift register 4 becomes off level, the next accumulation of signal charges begins. The signal charge is transferred to the horizontal CCD register 10 by the above-mentioned priming transfer, and further transferred to the output section 13 by the function of the horizontal CCD register 10, and is taken out as an output signal. After transferring the surplus charge leaked to the vertical signal line 2 to the sink drain 15,
In order to read out signal charges, the signal charges were not mixed with surplus charges, and the blooming phenomenon was supposed to be suppressed.

However, as described below, such a conventional driving method for a solid-state imaging device has the disadvantage that sufficient characteristics cannot be obtained in the above-mentioned priming water transfer and the blooming phenomenon cannot be suppressed. The priming water transfer will be discussed below using a diagram. Second
In the figure, at t ₄ , the first transfer gate 7 is gated,
Vertical signal line 2 is used as a source, and region 5 is used as a drain.
MOS field effect transistors (MOSFETs) operate in the saturation region or weak inversion region. Also t ₇
The MOSFET in which the second transfer gate 12 is the gate, the region 5 is the source, and the buried gate part of the second transfer gate 12 is the drain operates in the saturation region or weak inversion region. Figure 3 is the above
This is a circuit with only the essential parts extracted to explain the operation of MOSFET. Consisting of one MOSFET, the gate 18 is connected to a pulse source, a source capacitor 21 with a capacitance of Cs farad is provided between the source 19 and the substrate, and the drain 20 is connected to a drain power source 22. Set the potential of the board to 0V
The potentials of the gate 18, source 19, and drain 20 are V _G volts, V _S volts, and V _D volts, respectively. FIG. 4 shows the current characteristics of the MOSFET shown in FIG. 3. The horizontal axis is the source potential,
When the current flowing through the MOSFET is defined as ampere, the vertical axis is log ₁₀ I. At this time, the gate potential was set to 5 volts, which is an on level, and the drain power supply 22 was set to 8 volts, which is sufficiently higher than that. Let the threshold voltage be V _T volts. However, the threshold voltage depends on the source voltage. When V _S is smaller than V _G −V _T , the MOSFET operates in the saturation region of the strong inversion region, and when V _S is larger than V _G − V _T , the MOSFET operates in the weak inversion region. As V _S increases, current I decreases. Especially in the weak inversion region, it decreases logarithmically. If the elementary charge is q coulombs, the Boltzmann constant is k coulomb volts/degree, the absolute temperature of the device is T degrees, and Io is a constant, the current characteristic formula in the weak inversion region is I=Io exp(-qVs/kT)... …(1). The size of Io is determined by the gate voltage V _G and MOSFET
It depends on the size etc. Now, in the circuit shown in FIG. 3, the time variation of the source potential V _S when V _G is on level will be examined in the case of weak inversion. Since the discharge from the source capacitance is the MOSFET current, V _S follows the following equation.

CsdVs/dt=I=Io exp(-qVs/kT)...(2) Equation (2) can be integrated, and if the source potential V _S at t=0 seconds is V _O , then Vs(t:Vo )=kT/qln{exp(qVo/kT) +kTCSt/qIo}...(3). Assume that the gate 18 is periodically turned on for an on-time of Ton seconds and that −Q coulombs of electrons are externally injected into the source capacitance each time the gate 18 is at the off level. In this case, if the source potential when the gate 18 changes from on level to off level is V _R , then
In steady state, Vs (Ton; V _R -Q/CS) = V _R ...(4) holds true. When solving for V _R , V _R =kT/qlnkTCSTon/qIo -kT/qln{l-exp(-qQ/kTCS)}...(5). It shows the reset potential V _R of the source capacitor after transfer when the amount of charge transferred is -Q.
Let the first term be _VRO . Equation (5) is illustrated in Figure 5. When −Q is sufficiently large compared to kTCS/q, V _R V _RO becomes a constant value, whereas −
When Q becomes smaller than kTCS/q, V _R suddenly becomes
It can be seen that it is larger than V _RO . The above discussion was limited to the case of weak inversion, but the case where the gate 18 operates in the saturation region for a part of the time Ton that it is on level and operates in the weak inversion region for the remaining time. However, the above conclusion can be applied if there is a certain amount of time to operate in the weak inversion region. Furthermore, although we have discussed the case where the amount of charge injected into the source capacitance 21 -Q is constant, the case where -Q varies also.
Show similar properties.

Apply the above conclusion to priming water transfer. First t ₄
In a MOSFET with the first transfer gate 7 as the gate, the vertical signal line 2 as the source, and the region 5 as the drain, -
Q is the surplus charge and the priming charge. When the capacitance of vertical signal line 2 is C _L , if the absolute value of the amount of priming charge is larger than kTC _L /q, vertical signal line 2
is reset to a nearly constant potential and does not cause blooming phenomena. Next, at t ₇ , the second transfer gate 1
2 as gate, region 5 as source, second transfer gate 1
The buried gate part of 2 was used as the drain.
In MOSFET, -Q is only surplus charge. The surplus charge varies depending on each vertical signal line 2 and also in time, and when the capacitance of the region 5 is Cc,
The absolute value of the surplus charge can be larger or smaller than kTCc/q. If the device temperature is room temperature,
kT/q is about 0.027 volt. For this reason, the reset potential of region 5 varies depending on the amount of surplus charge, and the amount of signal charge transferred next has a correspondingly different effect, causing the blooming phenomenon. As described above, the conventional driving method for the conventional solid-state imaging device has the disadvantage that the blooming phenomenon cannot be sufficiently suppressed.

The purpose of this invention is to eliminate the above-mentioned drawbacks,
An object of the present invention is to provide a method for driving a solid-state imaging device that can obtain good reproduced images.

According to the present invention, a large number of vertical signal lines for vertically transferring signal charges from each arrayed photodiode, a connection point provided corresponding to the vertical signal line, and the vertical signal line a first transfer gate provided between the connection point and the first control line, a control capacitor provided between the connection point and the second control line, and a control capacitor corresponding to the connection point; a horizontal CCD (charge-coupled device) register provided as a gate, and a second
a transfer gate, a diffusion layer provided corresponding to the vertical signal line and connected to a power supply, a control gate provided between the diffusion layer and the vertical signal line, and adjacent to the channel of the horizontal CCD register. In a solid-state imaging device having a charge absorption mechanism consisting of a sink control gate and a sink drain, the potential is set to a potential when the signal charge is a hole, and a potential with the opposite sign when the signal charge is an electron. In this case, the potential of the vertical signal line reset by the first transfer gate is increased, and the potential of the vertical signal line is increased by turning on the control gate during the horizontal retrace period. is set to the potential of the power supply, and further, a portion of the charge is transferred from the vertical signal line to the horizontal CCD register by priming transfer, and as a result, the potential of the vertical signal line is set to the channel potential of the first transfer gate. Further, a portion of the charge transferred to the horizontal CCD register is absorbed into the charge absorption mechanism, further, a signal charge is transferred from the photodiode to the vertical signal line, and further, this signal charge is transferred to the vertical signal line. A method for driving a solid-state imaging device is obtained, which is characterized in that priming is transferred from a line to the horizontal CCD register.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 6 is a diagram for explaining a method of driving a solid-state imaging device according to an embodiment of the present invention, and is a schematic plan view of the solid-state imaging device. In FIG. 1 and FIG. 6, the same symbols indicate the same components. In this device, a diffusion layer 24 connected to a power source 23 corresponds to the end of the vertical signal line 2, and a control gate 25 is provided between the diffusion layer 24 and the vertical signal line 2.

A method for driving a solid-state imaging device according to an embodiment of the present invention will be described. As described above, the operation of the weak inversion region of the first transfer gate 7 at _t4 of the priming transfer resets the vertical signal line 2 to a potential of _VRO volts or greater. The power supply 23 is held at a potential V _A volts smaller than this V _RO . Before transferring the signal charge to the vertical signal line 2, the control gate 25
is set to on level, and the potential of vertical signal line 2 is set to power supply 2.
Set to potential 3. Control gate 25 is operated in a linear region. At this time, if there is a large amount of surplus charge flowing out to the vertical signal line 2, the charge moves from the vertical signal line 2 to the power supply 23, and conversely, if there is little surplus charge flowing out to the vertical signal line 2, the charge moves from the vertical signal line 2 to the power supply 23. Charges move more toward the vertical signal line 2. control gate 25
After turning off level, perform priming transfer.
Assuming that the absolute value of the priming charge is sufficiently larger than kTC _L /q, the potential of the vertical signal line 2 at time _t4 is
Reset to V _RO . In other words, the absolute value is (V _RO
This means that charges of -V _A )×C _L have been transferred from the vertical signal line 2 to the region 5 . _CL is about 5pF, and Cc is
Since it is about 0.2pF, it is assumed that V _A is even slightly smaller than V _RO . For example, if it is at least 0.002 volts smaller, (V _RO − V _A ) × C _L is kTCc/
q, and at time _t7 , region 5 is reset to a constant potential, and this charge is transferred to sink drain 1.
Transferred to 5. In this way, since both the vertical signal line 2 and the region 5 are reset to a constant potential,
The next time the signal charge is transferred, it will not be affected by the surplus charge, and the blooming phenomenon will be suppressed.

Even within the same wafer, the threshold potential of MOSFETs varies by about 0.05 volts, and as the threshold potential increases, the reset potential also increases accordingly. The potential of the power supply 23 is set for one of the plurality of transfer gates 7 that has a smaller threshold potential. Or V _A is 0.05 below the average V _RO
It may be made as small as a bolt.

Due to variations in the threshold potentials of the MOSFETs, the reset potentials of each vertical signal line 2 and each region 5 vary. However, when focusing on one vertical signal line 2 or one region 5, it is always reset to a constant potential, so variations in the reset potential do not affect the output signal.

The control gate 25 may be turned on at any time except when the first transfer gate 7 is on or when signal charges are present on the vertical signal line 2.

The signal charge may be transferred from the photodiode 1 to the vertical signal line 2 at any time after the vertical signal line 2 is reset.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional method of driving a solid-state imaging device, and is a schematic plan view of the solid-state imaging device;
Figure 2 shows horizontal CCD register 1 from vertical signal line 2.
Figure 3 is a partial cross-sectional view, potential diagram, and timing diagram to explain the transfer of charge to 0.
A circuit for examining the characteristics when the MOSFET is operating in the saturation region or weak inversion region of the strong inversion region. Figure 4 is a current characteristic diagram of the MOSFET, and Figure 5 is a reset due to the function of the weak inversion region of the MOSFET. FIG. 6, which is a diagram showing characteristics, is a diagram for explaining a method of driving a solid-state imaging device according to an embodiment of the present invention, and is a schematic plan view of the solid-state imaging device. 1...Photodiode, 2...Vertical signal line,
5... Area, 6... First control line, 7... First transfer gate, 8... Second control line, 9... Control capacity, 1
0...Horizontal CCD register, 11...Third control line,
12...Second transfer gate, 14...Sink control gate, 15...Sink drain, 23...
...power supply, 24...diffusion layer, 25...control gate.

Claims (1)

[Claims] 1. A large number of vertical signal lines for vertically transferring signal charges from each arrayed photodiode, a region provided corresponding to the vertical signal line, and a connection between the vertical signal line and the region. a first transfer gate provided therebetween and controlled by a first control line; a control capacitor provided between the area and the second control line; and a horizontal area provided corresponding to the area.
CCD (charge coupled device) resistor and this horizontal CCD
a second transfer gate provided between the register and the region and controlled by a third control line; a diffusion layer provided corresponding to the vertical signal line and connected to the power supply; A method for driving a solid-state imaging device including a control gate provided between a vertical signal line and a charge absorption mechanism including a sink control gate and a sink drain provided adjacent to a channel of the horizontal CCD register,
When the potential is set to a potential when the signal charge is a hole, and when the signal charge is an electron, the potential is set to have the opposite sign to the potential, and from the potential of the vertical signal line reset by the first transfer gate. In addition, the potential of the power supply is increased, the control gate is turned on during the horizontal retrace period, the potential of the vertical signal line is set to the potential of the power supply, and a part of the charge is removed from the vertical signal line. is transferred to the horizontal CCD register by priming transfer, and as a result, the vertical signal line potential is set to the channel potential of the first transfer gate, and furthermore, the horizontal signal line potential is set to the channel potential of the first transfer gate.
A portion of the charge transferred to the CCD register is absorbed into the charge absorption mechanism, further, a signal charge is transferred from the photodiode to the vertical signal line, and further, this signal charge is transferred from the vertical signal line to the horizontal CCD register. 1. A method for driving a solid-state imaging device, characterized by transmitting priming water to a solid-state imaging device.