JPS6057746B2 - solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to improving the performance of a solid-state imaging device that reads out optical information accumulated in a plurality of diodes arranged two-dimensionally on a semiconductor surface.

(2) Prior Art FIG. 1 shows the basic configuration of a solid-state imaging device.

Reference numerals 1 and 2 denote horizontal and vertical scanning circuits, which typically apply 2- to 4-phase clock pulses CPx and CPy to generate an output pulse train, Vox, in which the input pulses Vsx and Vsy are shifted by a fixed timing period of the clock. (1)
, Vox(2)..., Vo■1), Voy(2
)...... are the output lines Ox(1), O of each stage of the scanning circuit.
x(2)..., 0■1), Oy(2)...
Output to...

The switching elements included in the photoelectric conversion element 3 are sequentially opened and closed by this pulse train, and signals from the individual photoelectric conversion elements arranged in a two-dimensional manner are taken out onto the video output line 4. Since the signal from the photoelectric conversion element corresponds to the optical image projected thereon, a video signal can be extracted by the above operation. In order to obtain high resolution, this type of solid-state imaging device requires a photoelectric conversion element, a switching element, and a scanning unit circuit of approximately 500 x 500@l.

Therefore, it is usually relatively easy to achieve high integration, and the photoelectric conversion element and switching element can be integrated into an integrated structure.
Manufactured using S-LSI technology. FIG. 2 shows the structure of a photoelectric conversion element that occupies most of the area of the solid-state image sensor 1C. 5 and 6 are MOS switches for selecting horizontal and vertical positions, and are made of diffusion layers 7 and 27 forming drains and sources, and gate electrodes 9 and 29 provided through an insulating oxide film 8.

10 is a photodiode using the source of a vertical MOS switch.

Output pulse V of a scanning circuit using a MOS shift register or the like. x(N), ■0y(N) is the output line 0x(N), 0
Through y(N), the video voltage 11 charges the charge that was being discharged from the diode 10 at the same time applied to the gate of the MOS switch in proportion to the amount of incident light. The charging current at that time is read out as a video signal through the load resistor 12. However, in such conventional elements, fixed pattern noise (FixedP
NOISE) has occurred, which has become a fatal defect.

Figure 3a is a simpler depiction of the structure in Figure 2,
30 is, for example, a p-type silicon substrate, and 10 is one photodiode made of an n+ diffusion layer.

Further, 27 corresponds to the vertical signal line shown in FIG. 1, A7 in FIG. 3 corresponds to the common horizontal output line 4 in FIG.
7 are each made of a metal such as aluminum or a conductive material such as an n+ diffusion layer. 3. b to e in FIG. 3 show channel potentials corresponding to a.

Since we are currently considering an n-channel device, the potential is set in the positive direction. In FIG. 3b, a signal charge 31 is accumulated in the photodiode 10, and 0V is applied to the gate 29 of the vertical transistor (hereinafter abbreviated as Tr) 32 and the gate 9 of the horizontal transistor (hereinafter abbreviated as HTr) 33. Both transistors are set to 0ff.

In Figure 3c, VTr32 is 0n and the signal charge is ■Tr32.
It shows a state in which the signal line is spread under the gate 29 and to the vertical signal line 27.

FIG. 3d shows a potential in the process of being output, with the HTr 33 also turned ON and the signal charge spreading to the horizontal output line 7. FIG. 3(e) shows a stage where the signal charge has been read out and the signal of the next picture element is being read. That is, the signal charge 31 is first accumulated in the vertical signal line 27 via the VTr 32, and then accumulated in the horizontal output line 7 via the HTr 33, and the signal charge 31 is read out from the video signal by the signal readout device provided at the output end. It is read as . Generally, the horizontal pulse is 2! Since it is driven at S-4Hz to 10MHz, the third
From stage c to stage e in the figure, it takes 500r1S to 100ns.
The operation must be completed in a short period of time. The read time constant of the output signal is mainly determined by the resistance of the horizontal transistor HTr33 and the capacitance Cv of the vertical signal line. As mentioned above, in solid-state imaging devices, many transistors are integrated at high density, so it is difficult to obtain transistors with sufficiently low resistance. Therefore, about 10% to 1% of the signal is left unread as the residual charge 34. This residual charge 34 causes extreme deterioration of the vertical resolution of the two-dimensional solid-state imaging device.

(3) Purpose of the Invention The purpose of the present invention is to improve the vertical resolution of a two-dimensional solid-state imaging device.

(4) Examples Hereinafter, the present invention will be explained in detail with reference to examples.

FIG. 4 shows an embodiment of the present invention.

In FIG. 4, 41 is a reset transistor for resetting each vertical signal line, 42 is a reset pulse gate, and 43 is a reset drain. FIG. 5 shows a timing chart of each pulse, and the reset pulse is set to 0n at a certain time.

The horizontal blanking time is about 11 μS, but if the reset pulse is generated within that period, the width TR of the reset pulse can be reduced to 11 μS in principle, and 10 ps in practice.
It can be taken up to about s.

Therefore, the time can be 10 to 10 times longer than the time to read one signal with a horizontal pulse, so the reset transistor 41 can be replaced with a transistor with a slightly higher resistance.
Even if it is used for this purpose, each vertical signal output line can be cleared to the reset voltage VO with sufficient S/N ratio. Therefore, by applying the present invention, it is possible to significantly improve the resolution in the vertical direction.

Note that the value of the reset voltage 43 is equal to the output bias voltage 44.
V. It goes without saying that it is desirable to choose the same value. Another effect of the present invention is suppression of blooming.

For example, in FIG. 4, consider that strong light is irradiated on the m-th column from the top, causing blooming. If the present invention is not applied, a strong signal will be mixed into the signal of the next (m+1)th column, and a blooming phenomenon will appear in the vertical stripes. When the present invention is applied, the vertical output line is cleared during the horizontal blanking time between the mth column and the (m+1)th column, so
Blooming charges accumulated during that time are also cleared.
FIG. 6 shows an example of the configuration of the vertical shift register.

I is an inverter. Also, a timing chart of each pulse at that time is shown below. Vertical synchronization pulse φy
The vertical shift register is operated with two pulses, φY1 and φY2, which are slightly delayed from the pulse φY2, and the vertical pulse ■ is generated as shown in FIG.

Taking out y(n) and VOy(n+1) yields V. y(n)
,■. y(n+1) changes its state in synchronization with φY2. Therefore, the reset pulse φ1 in this case is φy1
The fifth point is that there is no problem with the principle of the present invention even if the
It can be seen from the figure and Fig. 6. In other words, the reset pulse φR shown in FIG. 5 can be used together with one of the vertical synchronizing pulses, and the number of pulses will not increase by applying the present invention.

(5) Summary As explained above, by applying the present invention to a two-dimensional solid-state imaging device, the resolution in the vertical direction can be significantly improved.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams for explaining a conventional example, and FIG. 3 is a diagram for explaining problems in the conventional example.

Claims (1)

[Claims] 1. A plurality of photodiodes two-dimensionally provided on a semiconductor substrate, horizontal and vertical MOS switches that transfer the signal charges accumulated in the photodiodes to the output end, and the signal charges generated by the horizontal and vertical MOS switches. A signal line that temporarily accumulates the signal charge during transfer, a horizontal and vertical shift register that controls opening and closing of the horizontal and vertical MOS switches, and a signal line that continues the signal charge transferred to the output terminal. What is claimed is: 1. A solid-state imaging device comprising a signal readout device, further comprising means for clearing the signal line in which the signal charge from the photodiode is first accumulated within a horizontal blanking period.