JPH05207376A - Solid-state image pickup device and its control method - Google Patents

Abstract

PURPOSE:To provide the solid-state image pickup device which is operated to avoid the saturation in a controllable integration time range in the case of a bright object and realizes the operation in a short integration time in the case of a dark object. CONSTITUTION:The solid-state image pickup device is provided which has an amplification type solid-state image pickup element as a unit picture element, and this amplification type solid-state image pickup element consists of a photo diode part 1, a capacitive element 3 where photoelectric charge is stored, an n-type MOS transistor TR 2 which outputs a signal corresponding to the photoelectric charge stored in the capacitive element 3, and an n-type MOS TR 4 for reset which refreshes the photoelectric charge stored in the capacitive element 3. A polysilicon gate 1e is formed on a photo diode part 1, and this part 1 is divided into two areas 1-1 and 1-2, and the effective light reception area is switched by a switching element formed by the polysilicon gate 1e.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid-state image pickup device used as a light receiving element of an automatic focus control device (AF = Auto Focus) of a camera.

[0002]

2. Description of the Related Art Conventionally, in addition to CCD, SIT, AMI, BAS are used as solid-state image pickup devices used for AF of cameras.
An amplification type solid-state imaging device such as IS is known. The amplification type solid-state image pickup device has advantages such as nondestructive readout as compared with the CCD, but the amplification type solid-state image pickup device is configured in a device having a relatively large pixel size such as used for an AF line sensor. Since there is a problem that the sensitivity cannot be increased due to the parasitic capacitance of the photodiode itself, a signal reading method is required in which the sensitivity does not depend on the photodiode capacitance.

Next, this point will be described based on the AMI shown in FIG. FIG. 9 is a circuit configuration diagram showing the configuration of one pixel of a normal AMI, 101 is a photodiode, Q
Reference numeral 1 is an amplifying transistor, Q2 and Q3 are biasing transistors, Q4 is a resetting transistor, 102 is a bias circuit, and 103 is a switching transistor driven by an output pulse from a shift register. In the AMI configured as described above, the signal output voltage ΔV _OUT by photoelectric conversion is given by the following expression (1). ΔV _OUT = I _P · t / C _d (1)

Where I _P is the photocurrent, t is the integration time, and C
_d is the junction capacitance of the photodiode 101. As can be seen from the equation (1), in order to increase the signal output voltage ΔV _OUT under a constant integration time, I _P should be increased or C should be increased.
_d must be small. However, in order to increase I _P , the pixel area must be increased, and as the pixel area increases, C _d also increases. Further, in order to reduce C _d , the pixel area must be reduced, and when the pixel area is reduced, I _P becomes smaller. Therefore, the conventional A
The sensitivity cannot be improved with the MI configuration.

In order to solve this problem, the configuration as shown in FIG. 10 is "A New MOS Imager Using Photodiode as
Current Source "(IEEE JOURNAL OF SOLID-STATE-CI
RCUITS, VOL. 26, NO. 8, Aug., 1991). This configuration has a transfer gate transistor Q.
5, Q6 is added, and a storage capacitor C _t is connected between the photodiode 101 and the amplifying transistor Q1. In the solid-state image pickup device configured as described above, the transistor Q5 is turned on by the Data signal so as to operate in the saturation region during the integration period, and the voltage applied to the photodiode 101 changes from the gate voltage of the transistor Q5 to the gate voltage. By fixing the voltage lower than the source-to-source voltage V _{GS, the} photocharge generated in the photodiode 101 is stored in the storage capacitor C _t connected to the gate of the amplifying transistor Q1 via the transistor Q5. It Therefore, the influence of the junction capacitance C _d of the photodiode 101 is cut off, and the signal output voltage ΔV _OUT by photoelectric conversion is cut off.
Is determined by the following equation (2). ΔV _OUT = I _P · t / C _t (2)

As can be seen from the equation (2), the signal output voltage ΔV _OUT can be increased by reducing the storage capacitance C _t . That is, the sensitivity can be determined without depending on the junction capacitance C _{d of the} photodiode.

Similarly, a pixel configuration shown in FIG. 11 is considered as a pixel configuration in which the sensitivity can be set without being affected by the photodiode capacitance and the sensitivity can be increased. In the figure, 201 is a photodiode and 202 is an n-type MO.
The source is grounded by the S transistor, and the depletion type n-type MOS transistor 205 that operates as a load is connected to the drain to form a source-grounded amplifier circuit. The photodiode 201 is connected to the input terminal of the source-grounded amplifier circuit, that is, the gate of the n-type MOS transistor 202, and the output terminal of the source-grounded amplifier circuit, that is, the drain of the n-type MOS transistor 202 to the input terminal (n-type A resetting n-type MOS transistor 204 for connecting a capacitive element 203 to the gate of the MOS transistor 202 to provide feedback and setting an initial potential of the gate of the n-type MOS transistor 202
Is connected in parallel with the capacitive element 203. This structure is used as a basic cell (pixel), and when the basic cell is arranged one-dimensionally or two-dimensionally, the reading pixel is selected.
Switching element 20 driven by shift register pulse
6 is provided and when the switching element 206 is turned on,
The drain voltage of the n-type MOS transistor 202 appears on the signal output line 207.

Next, the operation of the solid-state image pickup device configured as described above will be described. First, before the start of integration, a reset pulse φ _R turns on the n-type MOS transistor 204 to perform a reset operation, and integration is started from the time when the n-type MOS transistor 204 is turned off. After that, when a certain integration time has elapsed, the switching element 206 is turned on and the signal output V _OUT given by the following equation (3) is obtained from the signal output line 207. V _OUT = V _GS + I _P · t / {(1 + 1 / G) C _t + 1 / G · C _d } (3)

Here, V _GS is the gate-source voltage of the n-type MOS transistor 202 at the time of reset, and this is also the drain voltage at the time of reset. G is the gain of the source-grounded amplifier circuit, C _t is the capacitance value of the capacitive element 203, C _d is the junction capacitance value of the photodiode 1, and I _P and t are the photocurrent and the integration time, respectively, as in the previous case. ..

As can be seen from the above equation (3), the increase in the output signal due to the photoelectric conversion can be suppressed by the junction capacitance C _d of the photodiode 201 by increasing the gain G of the source-grounded amplifier circuit. it can. As a result, by decreasing the capacitance value C _t of the feedback capacitance element 203, the output voltage V _OUT can be increased, that is, the sensitivity can be increased.

[0011]

[Problems to be Solved by the Invention] FIG. 10 or FIG.
In the conventional solid-state imaging device shown in FIG. 1 or the conventionally considered solid-state imaging device, the sensitivity can be increased by reducing the storage capacitance or the feedback capacitance C _t . However, the following points must be taken into consideration in this sensitivity setting. That is, the range of the brightness of the subject for which the automatic focus control is performed must cover a dynamic range of about EV0 to EV18 and 2.6 × 10 ⁵ (= 2 ¹⁸ ) in terms of EV value.

In the AF control of a subject having a wide range of brightness, it is general to use the integration time control and the gain control amplifier together in order to obtain an optimum output. For example, when using a 10 times gain control amplifier, a dynamic range of 2.6 × 10 ⁵ can be covered by controlling the integration time in the range of 10 μsec to 260 msec. Therefore, the value of C _t is EV0
The subject may be set to have a predetermined output with an integration time of 260 msec and a gain of 10 times.

By the way, when it is desired to shorten the integration time for the object of EV0, that is, C is further than C _t described above.
If you want to reduce the value of _t and increase the sensitivity, the following problems occur. To increase sensitivity and shorten integration time,
For example, when the integration time is set to 1/3 described above, the minimum integration time must be 3.3 μsec. For that purpose, not only the pulse width of the pulse for controlling must be made very small, but also the response speed of the control system must be increased, but in reality, such short integration time control causes problems such as power consumption. There is, and it is difficult.

As another method of increasing the sensitivity, C _t
Assuming that the value of is the same as above, a method of increasing the amplifier gain by 30 times is conceivable. However, this method also amplifies noise, so the S / N cannot be improved even if the output reaches a predetermined level. Is included.

The present invention has been made to solve the above problems in the conventional solid-state image pickup device or the conventionally considered solid-state image pickup device, and the capacitance C _t that determines the sensitivity.
A solid-state imaging device that can operate so as not to saturate within a controllable integration time range for a bright object and can operate in a short integration time for a dark object even when the sensitivity is increased by decreasing The purpose is to provide.

[0016]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a pn matching type photodiode section and a photodiode for accumulating photoelectric charges generated by light incident on the photodiode section. A capacitor other than the capacitor, an amplifier that outputs a signal corresponding to the charge without destroying the charge accumulated in the capacitor, and a switching element for refreshing the charge accumulated in the capacitor. In a solid-state imaging device using the constructed amplification-type solid-state imaging device as a unit pixel, the region of the photodiode section is divided into a plurality of regions, and the photoelectric charge accumulated in the capacitive element of the unit pixel by a switching element provided in the region. It is configured so that the sensitivity of the pixel portion can be switched by changing the light receiving area that gives the light.

In the solid-state image pickup device configured as described above, since the sensitivity of the pixel portion is switched by turning on / off the switching element, even if the capacitance value of the capacitive element that determines the sensitivity is decreased to increase the sensitivity, For a bright subject, the light-receiving area can be reduced to lower the sensitivity to prevent saturation within the controllable integration time range, and for a dark subject, the light-receiving area can be increased to increase the sensitivity and shorten the integration time. Can be realized, and a wide dynamic range can be secured.

[0018]

EXAMPLES Next, examples will be described. The present invention is shown in FIG.
FIG. 1 shows an embodiment applied to a line sensor using the amplification type solid-state imaging device shown in FIG. FIG. 1A shows a circuit configuration diagram of a line sensor in which pixels are arranged in a line.
1B shows a sectional view of the photodiode section taken along the line AA ', and FIG. 1C shows a sectional view taken along the line BB' of the photodiode section. FIG. 2 shows a circuit configuration per pixel rewritten into an equivalent circuit.

In FIG. 1, reference numeral 2 is an n-type MOS transistor, and a source is grounded and a drain is connected to a depletion-type n-type MOS transistor 5 which operates as a load, thereby forming a grounded source type amplifier circuit. There is. The photodiode unit 1 is connected to the input terminal of the source-grounded amplifier circuit, that is, the gate of the n-type MOS transistor 2, and the output terminal of the source-grounded amplifier circuit,
That is, the capacitance element 3 is connected from the drain of the n-type MOS transistor 2 to the input terminal (gate of the n-type MOS transistor 2) to provide feedback, and for resetting to set the initial potential of the gate of the n-type MOS transistor 2. The n-type MOS transistor 4 is connected in parallel with the capacitive element 3 to form a basic cell. And in this basic cell,
A switching element 6 for sampling and holding the output voltage and a capacitive element 7 are provided, and an n-type MOS transistor 9 that operates as a read switching element is sequentially turned on by scanning a shift register 8 for the charge accumulated in the capacitive element 7. While being operated, the signal output line 10 is configured to read out as the signal output S _OUT via the buffer 11.
Also, every time the signal output is read out for each pixel, the signal output line
A signal line reset transistor 12 is provided on the signal output line 10 in order to remove charges remaining in the signal line 10.

The photodiode section 1 is shown in FIG.
As shown in the sectional view of (C), after the p well 1b is formed on the n substrate 1a, the photodiode portion 1 for each pixel is separated by the LOCOS oxide film 1c. After the formation, an n ⁺ diffusion layer 1d is formed by doping an n type impurity to form a pn junction type photodiode portion. In the present embodiment, in the photodiode portion of one pixel, the region is further divided into two regions. Therefore, the polysilicon gate 1e is formed on the photodiode portion before doping the n-type impurity. 1 is divided into two regions, a first photodiode region 1-1 and a second photodiode region 1-2, with the polysilicon gate 1e as a boundary.

In the line sensor thus constructed, the polysilicon gate 1 of the photodiode section 1 is
When the pulse applied to e is φ _GC , an inversion layer is formed immediately below the polysilicon gate 1e when φ _GC is “H”, and the two photodiode regions 1-1 and 1-2 are in a conductive state. become. Therefore, when the integration operation is performed in this state, the charge accumulated in the capacitive element 3 is the charge generated by the light incident on both the photodiode regions 1-1 and 1-2 of the photodiode unit 1, and the sensitivity is high. Will be higher.

On the other hand, when φ _{GC is set} to "L",
First photodiode region 1 of the photodiode section 1
-1 and the second photodiode region 1-2 become non-conductive. As a result, when the integration operation is performed, the charges accumulated in the capacitive element 3 are stored in the first region 1 of the photodiode section 1.
Φ _GC =
Compared with the case of "H", the sensitivity is reduced by the amount that the charges generated in the second photodiode region 1-2 are not accumulated.

Therefore, it is possible to increase the sensitivity ratio by increasing the area ratio between the first region 1-1 and the second region 1-2 of the photodiode section 1, thereby increasing the dynamic range. Can respond. In FIG. 2, 1e 'indicates a MOS switching element formed by the polysilicon gate 1e, and 1-1' and 1-2 'indicate the first divided photodiode and the second divided photodiode by the first region. The 2nd division | segmentation photodiode by the area | region is shown.

In this embodiment, the photodiode section 1 is divided into two and the sensitivity is switched in two steps. However, the number of divisions should be increased to three or four in order to perform finer sensitivity switching. Also has 2 and 3 polysilicon gates
It can be realized by adding more books.

In the above-mentioned embodiment, the photodiode portion is divided by the MOS switching element having the polysilicon gate. Next, one photodiode portion is divided by LOCOS separation. 3 shows. FIG. 3A is a plan view of the photodiode portion,
FIG. 3B is a sectional view taken along the line CC ′ of FIG. 3A, and the read circuit portion is not shown in FIG.
It is exactly the same as the embodiment shown in FIG.

In this embodiment, the photodiode section 21
Is formed by separating one photodiode region with a LOCOS oxide film 21c and dividing it into two regions 21-1 and 21-2. Then, the divided photodiode regions 21-1, 21
-2 is used as a switching element for connecting the gates of the n-type MOS transistor 2 to the polysilicon gates 22-1, 22-2 and the divided photodiode regions 21-1, 21-2.
To form an n-type MOS transistor. In FIG. 3B, 21a is an n substrate and 21b is a substrate.
Is a p-well and 21d is an n ⁺ diffusion layer.

The equivalent circuit configuration in this embodiment is shown in FIG. As can be seen from this Figure 4, the polysilicon gate
N-type MOS transistor 22- formed by 22-1 and 22-2
With the pulses φ _GC1 and φ _GC2 applied to 1 ′ and 22-2 ′,
It is possible to switch the divided photodiodes 21-1 'and 21-2' of the photodiode section 21 stored in the capacitive element 3.

As described above, the photodiode portion can be divided by using LOCOS isolation for one photodiode region. Further, by using the LOCOS isolation and the isolation by the polysilicon gate shown in the embodiment of FIG. 1, the photodiode region can be divided vertically and horizontally. Further, in each of the above-mentioned embodiments, the photodiode in which the p well is formed on the n substrate and the n ⁺ diffusion layer is formed thereon is described, but the same applies to the photodiode manufactured by the MOS process. Can be applied to.

Next, a control method for controlling the pulse applied to the polysilicon gate in the divided photodiode section to switch the sensitivity of the photodiode section will be described. Information on the brightness of the subject is required to switch the sensitivity. Automatic exposure control (AE =
Since a photometric device for Auto Exposure) is installed,
It is possible to switch the sensitivity based on the information. It is also possible to dispose a photometric photodiode on the same chip as the sensitivity switching sensor and switch the sensitivity based on that information. However, since the direction and range of photometry do not exactly match those of the sensors that switch the sensitivity, accurate photometry cannot be performed. Therefore, in the embodiment described below, a method of performing the switching control by detecting the signal level of the sensor itself that performs the sensitivity switching is shown.

FIG. 5 shows an embodiment in which the peak value of the output voltage of each pixel is detected and the sensitivity is switched based on the detected value. In this embodiment, an n-type MOS transistor 31 for detecting the output voltage of each pixel is added to each pixel in the configuration of the embodiment shown in FIG. And a depletion type n-type M connected to the source line 32 as a load.
The OS transistor 33 is connected. As a result, a voltage corresponding to the peak output of the entire pixel appears in the monitor voltage V _M of the source line 32. This is compared with the reference voltage V _ref using the comparator 34, and the output C _{OUT of the} comparator 34 is output.
Is configured to control the control system 35 to output a control pulse φ _GC for switching the sensitivity.

Next, an example of the operation of the sensitivity switching control device thus configured will be described with reference to the timing chart shown in FIG. FIG. 6 shows a reset pulse φ
_R, represents a sample-hold pulse phi _SH, monitor voltage V _M at the time when the dark subject of bright subject, the comparator output C _OUT, the sensitivity switching control pulse phi _GC. The period T ₀ is a period in which the reset operation is performed. During this period, φ _{R is set} to “H” and φ _{GC is set} to “H”, so that all regions 1-1 and 1-2 of the photodiode section 1 are set.
Are set in a conductive state, and each pixel is reset.

Next, in the period T ₁ , φ _R is changed from “H” to “L” and at the same time φ _{GC is set} to “L”, and the integration operation is performed with a low sensitivity setting. After performing the integration operation for a certain period,
The brightness of the subject is determined by the comparator output C _{OUT at} time t ₁ . When the subject is bright, the comparator output C _OUT is "H", and when it is dark, it is "L". Therefore, at time t ₁ , C
_{When OUT} = "H", φ _GC continues to be "L" in a low-sensitivity state, while when C _OUT = "L", φ _{GC
Switch the GC} from "L" to "H" for high sensitivity,
The integration is continued (period T ₂ ). At this time, when φ _GC is switched from “L” to “H”, the second diode formed in the photodiode region 1-2 on the side insulated by the switching element 1e ′ formed of the polysilicon gate until then.
The photocharges accumulated in the divided photodiode 1-2 'of No. 2 flow in, and the output of each pixel rises sharply. Therefore, if the sensitivity ratio between the low sensitivity state and the high sensitivity state is m, the reference voltage V
It is necessary to set _ref so that it is 1 / m or less of the saturated output. The time t ₁ may be set within the range of 1 / m of the shortest integration time to the longest integration time.

As described above, by monitoring the output of the amplifying n-type MOS transistor, it is possible to accurately set the sensitivity suitable for the subject. When the photodiode section is divided into three or four, the method of judging the brightness by adding two or three reference voltages to be compared, and the integration time to be compared are two or three points. Therefore, a method of judging the brightness based on the comparator output at each time can be considered.

Next, an embodiment in which the present invention is applied to a solid-state image pickup device using the amplification type solid-state image pickup device shown in FIG. 10 will be described. FIG. 7 shows a circuit configuration diagram of this embodiment, and the same or corresponding members as those of the embodiment shown in FIG. 5 and the image pickup device shown in FIG. 10 are designated by the same reference numerals. In the amplification type solid-state image pickup device in this embodiment, the output voltage becomes smaller as the accumulated charge becomes larger. Therefore, the monitoring device for detecting the output voltage of each pixel is changed to the p-type MOS transistor 31 '. .. Along with this, the load on the source line 32 is made active by the p-type MOS transistor 33 '.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG. In this image pickup device, so that charges generated in the photodiode portion 1 is accumulated in the storage capacitor element C _t through the transistor Q5, "H" level of the drive signal DATA, the transistor Q5 operates in the saturation region As described above, the reset voltage is set to V _R or less. As a result, the charges themselves generated in the photodiode portion become the bias current of Q5. Therefore, the switching element 1e ′ by the sensitivity switching control pulse φ _GC
When the bias current changes due to the ON / OFF switching of, the gate-source voltage V _GS of the transistor Q5 changes accordingly, and the voltage applied to the photodiode section 1 also changes.

Therefore, every time the sensitivity is switched,
Reset operation is required. Therefore, as shown in the timing chart, when the first integration operation is performed, φ _GC is set to “H” in the period T ₀ and the reset operation is performed at a high sensitivity setting, and then, in the period T ₁ , φ _GC = "H"
The integration is started as it is. After the elapse of a certain integration time, if the comparator output C _OUT is “L” at time t ₁ , the integration operation is continued as it is, and if the comparator output C _OUT is “H”, φ _{GC is set} to “L” and the sensitivity is low. After setting, the reset is performed again and integration is performed (period T ₂ ).

In this way, when the subject is bright, it is necessary to perform the integration operation twice, but when the subject is bright, the operation is completed in a short integration time. Therefore, the time required for the entire operation is the longest integration time. It can be set not to reach. For that purpose, it is better to set a short integration time until the time t ₁ for judging the brightness. In addition, the reference voltage V at this time
Regarding _ref , there is no restriction as in the embodiment shown in FIG. 5, and any value may be used as long as it is below the saturation level.

[0038]

As described above on the basis of the embodiments,
According to the present invention, since the sensitivity of the photodiode can be switched according to a bright subject and a dark subject, the sensitivity is lowered for a bright subject to allow a sufficient integration time to facilitate control, and for a dark subject. Can enhance sensitivity and realize operation in a short integration time, and can easily secure a wide dynamic range.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention, and a sectional view of a photodiode portion thereof.

FIG. 2 is a diagram showing an equivalent circuit of a pixel portion of the embodiment shown in FIG.

FIG. 3 is a plan view and a sectional view showing a photodiode portion of a second embodiment.

FIG. 4 is a diagram showing an equivalent circuit configuration of a pixel portion of a second embodiment.

FIG. 5 is a circuit configuration diagram showing a third embodiment including a sensitivity switching controller.

FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 7 is a circuit configuration diagram showing a fourth embodiment similarly including a sensitivity switching control section.

FIG. 8 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 9 is a circuit configuration diagram showing a configuration example of a conventional amplification type solid-state imaging device.

FIG. 10 is a circuit configuration diagram showing another configuration example of a conventional amplification type solid-state imaging device.

FIG. 11 is a circuit configuration diagram showing an amplification type solid-state imaging device which has been conventionally considered.

[Explanation of symbols]

1,21 Photodiode part 1-1 First photodiode region 1-2 Second photodiode region 1-1 'First divided photodiode 1-2' Second divided photodiode 1a, 21a n Substrate 1b , 21b p well 1c, 21c LOCOS oxide film 1d, 21dn ⁺ diffusion layer 1e, 22-1, 22-2 polysilicon gate 2 n-type MOS transistor 3 feedback capacitance element 4 reset n-type MOS transistor 5 depletion type n-type MOS transistor 6 Switching element 7 Capacitance element 8 Shift register 9 Read n-type MOS transistor 10 Signal output line 11 Buffer 12 Signal line reset transistor 31 Detection n-type MOS transistor 32 Source line 33 Load n-type MOS transistor 34 Comparator 35 Control system

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 31/10

Claims (4)

[Claims] 1. A pn matching type photodiode section, a capacitive element other than the photodiode section for accumulating photocharges generated by light incident on the photodiode section, and a charge accumulated in the capacitive element are destroyed. In the solid-state imaging device using an amplification-type solid-state imaging device as a unit pixel, which is configured by an amplification unit that outputs a signal corresponding to the electric charge and a switching element for refreshing the electric charge accumulated in the capacitive element, The region of the photodiode portion is divided into a plurality of regions, and the sensitivity of the pixel portion can be switched by changing the light-receiving area for applying the photocharge accumulated in the capacitive element of the unit pixel by the switching element provided in the region. A solid-state imaging device characterized by the above. 2. The monitor means for detecting the signal output level of the amplification section of the unit pixel and the control means for controlling the sensitivity switching switching element based on the monitor signal of the monitor means and a reference signal are the same. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided on a chip. 3. The method of controlling a solid-state image pickup device according to claim 2, wherein when a capacitive element of the unit pixel is reset, a sensitivity switching switching element is turned on to perform a refresh operation at a high sensitivity setting and start integration. After that, turn off the switching element for sensitivity switching to set low sensitivity,
When integrated for a certain period of time, the monitor signal level of the monitor means is compared with the reference signal level, and when the monitor signal level is higher than the reference signal level, the integration is continued as it is, and when the monitor signal level is low, the sensitivity switching switching element is turned on. A method for controlling a solid-state imaging device, comprising: switching to a state, setting a high sensitivity, and continuing an integration operation without performing a refresh operation. 4. The solid-state image pickup device according to claim 2, wherein during initial reset operation and subsequent integration, a sensitivity switching switching element is turned on to operate at a high sensitivity setting, and a monitor signal is output after a certain integration time has elapsed. If the monitor signal level is lower than the reference signal level, the integration is continued as it is, and if the monitor signal level is higher, the second reset operation is performed to set the low sensitivity, and then the integration is performed again. A method for controlling a solid-state imaging device, comprising performing an operation.