JPH05129502A - Package structure of lsi - Google Patents

Package structure of lsi

Info

Publication number
JPH05129502A
JPH05129502A JP31365491A JP31365491A JPH05129502A JP H05129502 A JPH05129502 A JP H05129502A JP 31365491 A JP31365491 A JP 31365491A JP 31365491 A JP31365491 A JP 31365491A JP H05129502 A JPH05129502 A JP H05129502A
Authority
JP
Japan
Prior art keywords
input
output pins
pads
lsi
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31365491A
Other languages
Japanese (ja)
Inventor
Katsuhiro Uchida
勝広 内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP31365491A priority Critical patent/JPH05129502A/en
Publication of JPH05129502A publication Critical patent/JPH05129502A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To achieve a high-density mounting operation by a method wherein, at a multilayer interconnection board, its surface, is provided with pads used to bond a plurality of input/output pins and its rear surface is provided with a plurality of input/output pins whose interval size is different from that of the input/output pins. CONSTITUTION:Pads 3 whose mounting interval is the same as that of input/ output pins 1 are provided on a face bonded to the input/output pins 1 on a multilayer interconnection board 2; the individual pads 3 are boned to the respectively corresponding input/output pins 1 by a soldering operation. In addition, input/output pins 12 whose interval (b) is the same as that of through holes and pads on the side of a printed wiring board 13 are arranged on a face opposite to the face on which the pads 3 have been formed. Thereby, the number of input/output pins for an LSI per unit area can be increased, the physical size of the LSI can be made small, and a high-density mounting operation can be achieved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、電子機器内に使用され
るプリント配線基板に実装されるＬＳＩパッケージ構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI package structure mounted on a printed wiring board used in electronic equipment.

【０００２】[0002]

【従来の技術】従来のＬＳＩパッケージ構造は、図２
（Ａ），（Ｂ）に示すように、基板４の半導体部品５が
実装される面側に、入出力ピン１２，１２…が１／１０
ｉｎｃｈ以上の間隔ｂで配置されている。尚、基板４に
は、キャップ７が設けられる位置に、入出力ピン１２，
１２…が設けられていない。2. Description of the Related Art A conventional LSI package structure is shown in FIG.
As shown in (A) and (B), the input / output pins 12, 12, ... Are 1/10 on the surface of the substrate 4 on which the semiconductor component 5 is mounted.
It is arranged at a distance b which is equal to or larger than the inch. At the position where the cap 7 is provided on the substrate 4, the input / output pins 12,
12 ... is not provided.

【０００３】また、図３に示すＬＳＩパッケージ構造の
ものでは、半導体部品５実装面の反対側に１／１０ｉｎ
ｃｈ以上の間隔ｂで入出力ピン１２が全面に配置されて
いた。また、図中、６はリード、８はシール材、９は凹
部、１０はヒートシンクである。In the case of the LSI package structure shown in FIG. 3, 1/10 inch is provided on the side opposite to the mounting surface of the semiconductor component 5.
The input / output pins 12 were arranged on the entire surface at an interval b of ch or more. In the figure, 6 is a lead, 8 is a sealing material, 9 is a recess, and 10 is a heat sink.

【０００４】[0004]

【発明が解決しようとする課題】従来のＬＳＩパッケー
ジ構造では、図２（Ｂ）のようにキャップ部分には、入
出力ピンを立てられないため、必要とする入出力ピン数
を得るためには、基板の外形を大きくして入出力ピン実
装エリアを広げたりしなければならず、部品実装の高密
度化や、プリント配線基板の小型化に対応することが困
難となっている。In the conventional LSI package structure, the input / output pins cannot be set up in the cap portion as shown in FIG. 2B, and therefore, in order to obtain the required number of input / output pins. However, it is necessary to enlarge the outer shape of the board to expand the input / output pin mounting area, which makes it difficult to cope with high density mounting of components and miniaturization of the printed wiring board.

【０００５】又、図３のように半導体部品実装面の反対
側に入出力ピンを配置すれば、ピン実装面全てにピンを
配置することができるが、この場合は半導体部品から発
生した熱が基板を通りヒートシンクへ伝わるまでの熱伝
導距離が長くなり、且つ基板からヒートシンクへの熱伝
達面積が小さくなり、熱伝達効率が悪くなるという問題
があった。Further, if the input / output pins are arranged on the opposite side of the semiconductor component mounting surface as shown in FIG. 3, the pins can be arranged on the entire pin mounting surface, but in this case, heat generated from the semiconductor component is generated. There is a problem that the heat conduction distance until it is transmitted to the heat sink through the substrate becomes long, and the heat transfer area from the substrate to the heat sink becomes small, resulting in poor heat transfer efficiency.

【０００６】本発明の目的は、単位面積当りのＬＳＩの
入出力ピン数を容易に増やすことができるＬＳＩのパッ
ケージ構造を提供することにある。An object of the present invention is to provide an LSI package structure capable of easily increasing the number of input / output pins of the LSI per unit area.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係るＬＳＩのパッケージ構造においては、
半導体部品が実装された基板と、多層配線基板とを有す
るＬＳＩのパッケージ構造であって、前記半導体部品実
装用基板は、複数の入出力ピンを有するものであり、前
記多層配線基板は、前記入出力ピンを接合させるパッド
を上面に有し、前記入出力ピンと間隙寸法が異なる入出
力ピンを下面に有するするものである。In order to achieve the above object, in the package structure of the LSI according to the present invention,
A package structure of an LSI having a substrate on which semiconductor components are mounted and a multilayer wiring substrate, wherein the semiconductor component mounting substrate has a plurality of input / output pins, and the multilayer wiring substrate is A pad for joining the output pins is provided on the upper surface, and an input / output pin having a gap size different from the input / output pin is provided on the lower surface.

【０００８】[0008]

【作用】多層配線基板を利用することにより、単位面積
当りの入出力ピン数を増加させる。By using the multilayer wiring board, the number of input / output pins per unit area is increased.

【０００９】[0009]

【実施例】次に本発明について図面を参照して説明す
る。図１（Ｃ）は、本発明の一実施例に係るＬＳＩパッ
ケージを示す断面図であり、図１（Ａ）と図１（Ｂ）と
のものを組み立ててプリント配線基板１３に実装したも
のである。The present invention will be described below with reference to the drawings. FIG. 1C is a sectional view showing an LSI package according to an embodiment of the present invention, in which the ones shown in FIGS. 1A and 1B are assembled and mounted on a printed wiring board 13. is there.

【００１０】すなわち、図１（Ａ）に示す基板４の凹部
９に半導体部品５が実装され、凹部９のある面に入出力
ピン１，１…が配置されている。６はリード、７はキャ
ップ、８はシール材である。この基板４では、入出力ピ
ン１の実装間隔ａが一般のプリント配線基板１３などに
使用される１／１０ｉｎｃｈ間隔や１／２０ｉｎｃｈ間
隔より小さいものであり、単位面積当りの入出力ピン１
の実装本数は、従来のＬＳＩパッケージよりも遥かに多
くすることができる。That is, the semiconductor component 5 is mounted in the recess 9 of the substrate 4 shown in FIG. 1A, and the input / output pins 1, 1 ... Are arranged on the surface of the recess 9. 6 is a lead, 7 is a cap, and 8 is a sealing material. In this board 4, the mounting interval a of the input / output pin 1 is smaller than the 1/10 inch interval or 1/20 inch interval used for the general printed wiring board 13 or the like, and the input / output pin 1 per unit area is
The number of mounted devices can be much larger than that of the conventional LSI package.

【００１１】図１（Ｂ）に示す基板は、基板４の下面に
小さな間隔で配置された入出力ピン１をプリント配線基
板１３側のピン実装間隔へ変換するための多層配線基板
２である。多層配線基板２の入出力ピン１と接合する面
には、入出力ピン１と同じ実装間隔でパッド３があり、
各パッド３は各々対応する入出力ピン１とハンダ付けに
より結合される。The board shown in FIG. 1B is a multi-layer wiring board 2 for converting the input / output pins 1 arranged on the lower surface of the board 4 at a small interval into a pin mounting interval on the printed wiring board 13 side. Pads 3 are provided on the surface of the multilayer wiring board 2 that is joined to the input / output pins 1 at the same mounting intervals as the input / output pins 1.
Each pad 3 is connected to the corresponding input / output pin 1 by soldering.

【００１２】又パッド３のある面とは逆の面には、プリ
ント配線基板１３側のスルーホールやパッドと同間隔ｂ
で入出力ピン１２が配置されている。多層配線基板２の
内部でパッド３と入出力ピン１２は電気的に接続され、
これによりプリント配線基板１３側との信号のやりとり
を行うものである。On the surface opposite to the surface on which the pads 3 are provided, the same spacing b as the through holes and pads on the printed wiring board 13 side is provided.
The input / output pin 12 is arranged at. The pad 3 and the input / output pin 12 are electrically connected inside the multilayer wiring board 2,
As a result, signals are exchanged with the printed wiring board 13 side.

【００１３】[0013]

【発明の効果】以上説明したように本発明は、近年のＬ
ＳＩの入出力ピン数の増加に対応すべく単位面積当りの
ＬＳＩの入出力ピン数を容易に増やすことができる。
又、ＬＳＩの入出力のピン数が従来のＬＳＩと同一本数
という条件で比較した場合には、ＬＳＩの物理的大きさ
をより小さくすることが可能となり、プリント配線基板
上の高密度実装化に寄与することができる。As described above, according to the present invention, the L
It is possible to easily increase the number of input / output pins of the LSI per unit area to cope with the increase of the number of input / output pins of the SI.
Further, when comparing the number of input and output pins of the LSI with the same number of pins as the conventional LSI, it becomes possible to further reduce the physical size of the LSI, which leads to high-density mounting on the printed wiring board. Can contribute.

【図面の簡単な説明】[Brief description of drawings]

【図１】（Ａ），（Ｂ）は、本発明の一実施例に係るＩ
Ｃのパッケージ構造の組立前の状態を示す断面図、
（Ｃ）は、組立後の状態を示す断面図である。1A and 1B are views showing an I according to an embodiment of the present invention.
Sectional drawing which shows the state before the assembly of the C package structure,
(C) is a sectional view showing a state after assembly.

【図２】（Ａ）は、従来のＬＳＩパッケージを示す断面
図、（Ｂ）は同斜視図である。2A is a cross-sectional view showing a conventional LSI package, and FIG. 2B is a perspective view of the same.

【図３】従来のＬＳＩパッケージを示す断面図である。FIG. 3 is a sectional view showing a conventional LSI package.

【符号の説明】 １ 入出力ピン ２ 多層配線基板 ３ パッド ４ 基板 ５ 半導体部品 ６ リード ７ キャップ ８ シール材 ９ 凹部 １０ ヒートシンク １１ カバー １２ 入出力ピン １３ プリント配線基板[Explanation of reference numerals] 1 input / output pin 2 multilayer wiring board 3 pad 4 substrate 5 semiconductor component 6 lead 7 cap 8 sealing material 9 recess 10 heat sink 11 cover 12 input / output pin 13 printed wiring board

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/50 Ｐ 9272−4Ｍ 7352−4Ｍ Ｈ０１Ｌ 23/12 Ｊ Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 23/50 P 9272-4M 7352-4M H01L 23/12 J

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体部品が実装された基板と、多層配
線基板とを有するＬＳＩのパッケージ構造であって、 前記半導体部品実装用基板は、複数の入出力ピンを有す
るものであり、 前記多層配線基板は、前記入出力ピンを接合させるパッ
ドを上面に有し、前記入出力ピンと間隙寸法が異なる入
出力ピンを下面に有するものであることを特徴とするＬ
ＳＩのパッケージ構造。1. A package structure of an LSI having a substrate on which a semiconductor component is mounted and a multilayer wiring substrate, wherein the semiconductor component mounting substrate has a plurality of input / output pins. The substrate has a pad for bonding the input / output pins on the upper surface, and an input / output pin having a gap size different from that of the input / output pins on the lower surface.
SI package structure.
JP31365491A 1991-10-31 1991-10-31 Package structure of lsi Pending JPH05129502A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31365491A JPH05129502A (en) 1991-10-31 1991-10-31 Package structure of lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31365491A JPH05129502A (en) 1991-10-31 1991-10-31 Package structure of lsi

Publications (1)

Publication Number Publication Date
JPH05129502A true JPH05129502A (en) 1993-05-25

Family

ID=18043914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31365491A Pending JPH05129502A (en) 1991-10-31 1991-10-31 Package structure of lsi

Country Status (1)

Country Link
JP (1) JPH05129502A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235172A (en) * 1988-03-15 1989-09-20 Fujitsu Ltd Connection of ceramic substrate and input/output pin
JPH01264249A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Pin for board, board equipped with pin and printed-circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235172A (en) * 1988-03-15 1989-09-20 Fujitsu Ltd Connection of ceramic substrate and input/output pin
JPH01264249A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Pin for board, board equipped with pin and printed-circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same

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