JPH05129390A - Pattern for checking electrical characteristics of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain accurate contact resistance which excludes other resistant components by measuring the resistance of two patterns. CONSTITUTION:There are installed two patterns which connect a plurality of diffusion layer regions 2 having specified dimensions in series by way of a contact hole 1 and a metal wiring layer 6. The dimensions of the diffusion layer regions 2 are variable in each pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device electrical characteristic check pattern, and more particularly to a contact resistance check pattern.

[0002]

2. Description of the Related Art As shown in FIG. 2, a contact resistance check pattern in a conventional semiconductor device has one conductive type semiconductor region 2 or gate region of a certain size through a contact hole 1 and a metal wiring layer 6. , And had only one pattern connected in series.

[0003]

With the recent miniaturization of elements, the size of the contact hole 1 is also miniaturized, and the influence of this contact resistance on the electrical characteristics of the semiconductor device is becoming more and more significant.

However, the conventional check pattern has a problem that an accurate contact resistance value cannot be obtained because the resistance measurement value includes the resistance component of the one-conductivity type semiconductor region 2 or the gate region.

An object of the present invention is to solve the above-mentioned problems and to provide an electrical characteristic check pattern of a semiconductor device capable of accurately measuring a contact resistance.

[0006]

According to the check pattern of the present invention, a plurality of patterns of one conductivity type semiconductor region or gate region having a predetermined size are connected in series through a contact hole and a metal wiring layer. It is characterized in that the dimensions of one conductivity type semiconductor region or gate region of each pattern are made different.

[0007]

1 is a plan view showing an electric characteristic check pattern of a semiconductor device according to an embodiment of the present invention.

In one embodiment of the present invention, the N-type semiconductor region 2, the contact hole 1 and the metal wiring layer 6 are interposed between the electrode pads 3 and 4, and the N-type semiconductor region 2'is provided between the electrode pads 4 and 5. , The contact hole 1 and the metal wiring layer 6 are interposed.

In FIG. 1, the contact resistance check pattern of the embodiment of the present invention has the same size of the contact holes 1 and the same size of the N-type semiconductor regions 2 and 2 '.

The N-type semiconductor regions 2 and 2'have a width W and lengths L ₁ and L ₂ , respectively. The resistance R ₁ between the electrode pad 3 and the electrode pad 4 and the resistance R ₂ between the electrode pad 4 and the electrode pad 5 are expressed by the following equations (1) and (2), respectively.

R ₁ = 10R _c + 5ρ _s L ₁ / W (1) R ₂ = 10R _c + 5ρ _s L ₂ / W (2) where R _c ; contact resistance, ρ _s ; of N-type semiconductor region Resistance per unit area, W; width of N-type semiconductor region,
L ₁ ; the length of the N-type semiconductor region 2, L ₂ ; the length of the N-type semiconductor region 2 ′ Note that the contact resistances R _c are all considered to be the same, and the resistance of the metal wiring layer is much smaller than the other resistance components. Ignore it because it is too small.

From the above equations (1) and (2), the following equation is obtained.

R _c = (R ₁ L ₂ −R ₂ L ₁ ) / 10 (L ₂ −L ₁ ) Thus, an accurate contact resistance R _c can be obtained. The following equation is obtained from the equations (1) and (2).

The layer resistance of ρ _s = (R ₁ −R ₂ ) W / 5 (L ₁ −L ₂ ) N type semiconductor regions 2 and 2 ′ can also be obtained.

Instead of the N-type semiconductor regions 2 and 2 ',
Similar results are obtained using a P-type semiconductor region or gate region.

[0016]

As described above, according to the present invention, a plurality of patterns in which a plurality of one-conductivity type semiconductor regions or gate regions of a predetermined size are connected in series via contact hole metal wiring are provided.
By providing different sizes of the one conductivity type semiconductor region or the gate region for each pattern, it is possible to obtain an accurate contact resistance excluding other resistance components. The resistance per unit area of the region or the gate region can be obtained at the same time.

[Brief description of drawings]

FIG. 1 is a plan view showing an electrical characteristic check pattern of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing an electrical characteristic check pattern of a conventional semiconductor device.

[Explanation of symbols]

1 Contact Hole (Resistance R _c ) 2,2 ′ N-type Semiconductor Region 3,4,5 Electrode Pad 6 Metal Wiring Layer

Claims (1)

[Claims] 1. A one-conductivity-type semiconductor region or gate region having a predetermined size is provided through a contact hole and a metal wiring layer,
Two types of patterns connected in series are provided, the two types are provided, and the size of the one conductivity type semiconductor region or the gate region is different for each of the two types of patterns, and electrical characteristics of the semiconductor device. Check pattern.