JPS61248460A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61248460A JPS61248460A JP60088583A JP8858385A JPS61248460A JP S61248460 A JPS61248460 A JP S61248460A JP 60088583 A JP60088583 A JP 60088583A JP 8858385 A JP8858385 A JP 8858385A JP S61248460 A JPS61248460 A JP S61248460A
- Authority
- JP
- Japan
- Prior art keywords
- well
- type
- resistance
- type well
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000001747 exhibiting effect Effects 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特に、抵抗を集積化した相
補型絶縁ゲートトランジスタ装置（０ＭＯ８）Ｋ関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a complementary insulated gate transistor device (0MO8)K with integrated resistors.
従来の半導体装置上に集積された抵抗（以下モノリシッ
ク抵抗）は、例えばアナログ信号処理が主体のバイポー
ラＩＣではベース拡散層抵抗（以下ＢＲ低抵抗が多用さ
れている。しかしながら、デジタル信号処理が主体の０
ＭＯ８−ＩＣではモノリシック抵抗はあまり用いられな
かった。バイポーラＩＣのＢＲ低抵抗ついて＆瓜例えば
「集積回路工学（１）」柳井、永田著 コロナ社に、Ｃ
ＭＯ８ＩＣに関しては、例えば、日経エレクトロニクス
１９８０年１０月２７日号 Ｐ１７５などに述べられ
ている。Conventional resistors integrated on semiconductor devices (hereinafter referred to as monolithic resistors) are, for example, base diffusion layer resistors (hereinafter referred to as BR low resistance) often used in bipolar ICs mainly used for analog signal processing. 0
Monolithic resistors were rarely used in MO8-ICs. For example, "Integrated Circuit Engineering (1)" by Yanai and Nagata, Corona Publishing, C.
MO8IC is described in, for example, Nikkei Electronics October 27, 1980 issue, P175.
従来、０ＭＯ８−ＩＣにおいてモノリシック抵抗を用い
る場合、例えばＮ型基板、Ｐウェル構造の０ＭＯ８の場
合、ＰＭＯ８のソース及びドレインと同時に形成される
Ｐを拡散抵抗が用いららている。Ｐ散拡散層抵抗は、面
積抵抗率（正方形あたりの抵抗値、以下シート抵抗）が
１０Ω〜５０Ω程度と小さいため、ＢＲ低抵抗同等レベ
ルの、絶対精度、相対精度、温度係数。Conventionally, when a monolithic resistor is used in an 0MO8-IC, for example, in the case of an 0MO8 with an N-type substrate and a P well structure, a P diffused resistor is used, which is formed simultaneously with the source and drain of the PMO8. Since the P diffused layer resistance has a small area resistivity (resistance value per square, hereinafter referred to as sheet resistance) of about 10Ω to 50Ω, it has absolute accuracy, relative accuracy, and temperature coefficient at the same level as BR low resistance.
逆バイアス電圧依存性などを期待出来る。しかしながら
、シート抵抗が小さいため高抵抗を必要とする場合には
、レイアウト面積および寄生容量の増加を覚悟しなけれ
ばならない。より高抵抗を得る手段としてＰウェル抵抗
を用いることは従来から知られていたが、不純物濃度が
低いために本質的に電圧係数、逆バイアス電圧係数が著
しく悪いために、抵抗値精度の不要な場所、たとえばプ
ルアップ抵抗などに用いられておりＰウェル抵抗を精度
よ（作ろうとする試みはなされていなかった。We can expect reverse bias voltage dependence. However, if a high resistance is required because the sheet resistance is small, one must be prepared for an increase in layout area and parasitic capacitance. It has long been known to use a P-well resistor as a means of obtaining higher resistance, but because the impurity concentration is low, the voltage coefficient and reverse bias voltage coefficient are inherently extremely poor, making resistance value accuracy unnecessary. No attempt has been made to make P-well resistors accurate, such as in pull-up resistors.
本発明の目的は、０ＭＯ８−ＩＣにおいて、ウェルを用
いたモノリシック抵抗を相対精度良く形成する手段を提
供することにある。An object of the present invention is to provide a means for forming a monolithic resistor using wells with relatively high accuracy in an 0MO8-IC.
例えばＮ型基板、Ｐ−ウェル（ＷＩＬＬ）構成の０ＭＯ
８の場合には、Ｐ−ウェル（ＷＥＬＬ）を抵抗として用
いる場合には、アルミ配線と直接コンタクトを取ること
が出来ないために、Ｐ散拡散層を介して電気的に接続す
る。本発明は、このＰ散拡散層を積極的忙活用すること
により、Ｐ−ウェル抵抗の端子部の形状効果を少なくし
、比精度（相対精度）を向上させるものである。For example, N-type substrate, P-well (WILL) configuration 0MO
In the case of No. 8, when a P-well (WELL) is used as a resistor, it is not possible to make direct contact with the aluminum wiring, so it is electrically connected via a P diffusion layer. The present invention makes active use of this P diffusion layer to reduce the shape effect of the terminal portion of the P-well resistor and improve the relative accuracy.
矛１図に本発明の一実施例であるウェル抵抗のパターン
を示す図を、矛２図に矛１図のＷＥＬＬ抵抗の断面図を
示す。才１図および、１？２図において、１はＰ型のク
エ／Ｉ／、２および３はＰ減拡散層、４および５はアル
ミ配線パターン。Figure 1 shows a pattern of a well resistor according to an embodiment of the present invention, and Figure 2 shows a sectional view of the WELL resistor shown in Figure 1. In Figures 1 and 1 to 2, 1 is a P-type Que/I/, 2 and 3 are P-reduced diffusion layers, and 4 and 5 are aluminum wiring patterns.
６および７はＰ散拡散層とアルミ配線とのコンタクト、
８．９および１０はＳｉＯ，による絶縁層、１１はＮ型
基板、１６は絶縁保護膜である。6 and 7 are contacts between the P diffusion layer and the aluminum wiring;
8.9 and 10 are insulating layers made of SiO, 11 is an N-type substrate, and 16 is an insulating protective film.
矛１図からも判る様にＰ−ウェル１とアルミ配線４およ
び５を電気的に接続するには、Ｐ型拡散層２および３を
使用する。この時、Ｐ−ウェルのシート抵抗値は、５に
Ω〜１０にΩ１０程度であるのに対して、Ｐ散拡散層の
シート抵抗は１０〜５０Ω１０と大幅く小さいため１．
ｔＦｊ図に見られる様釦、Ｐ型拡散層２および３の＠（
Ｗｓ ）をＰ−ウェル１の＠（凧）より大きくか１長さ
方向（Ｌ）Ｋ対して垂直に取ることＫより、ＢＲ，抵抗
に見られる様な端子部分のパターンによる形状効果の影
響を受けることなく、抵抗値をほぼＬ／Ｗ、によって決
定することが可能となり、複数個のＷＥＬＬ抵抗間抵抗
比精度がとりやす（なる。As can be seen from Figure 1, P-type diffusion layers 2 and 3 are used to electrically connect the P-well 1 and the aluminum wirings 4 and 5. At this time, the sheet resistance value of the P-well is about 5Ω to 10Ω10, whereas the sheet resistance of the P-diffusion layer is much smaller at 10 to 50Ω10.
As seen in the tFj diagram, the P-type diffusion layers 2 and 3 @(
Ws ) is larger than the @(kite) of P-well 1 or perpendicular to the length direction (L)K, so that the influence of the shape effect due to the pattern of the terminal part as seen in BR and resistor can be reduced. It becomes possible to determine the resistance value approximately by L/W without being affected by the resistance, and the resistance ratio accuracy between the plurality of WELL resistors can be easily achieved.
Ｐ−ウェルの不純物濃度の低さに起因して、温度係数や
逆バイアス電圧係数が大きいため、抵抗値の絶対精度が
要求される用途あるいは、振幅の大きな交流信号が乗る
様な用途には向かないが、例えば、才１図に示す抵抗を
複数個直列接続して分圧電圧を得るために用いることな
どは逆バイアス電圧像数分をあらかじめ加味しておいて
設計を行なうことにより十分可能である。Due to the low impurity concentration of the P-well, the temperature coefficient and reverse bias voltage coefficient are large, so it is not suitable for applications that require absolute accuracy of resistance values or applications that carry AC signals with large amplitudes. However, for example, it is possible to connect multiple resistors shown in Figure 1 in series and use them to obtain a divided voltage by taking into account the number of reverse bias voltage images in advance. be.
矛５図に本発明の別の実施例であるＰ−ウェル抵抗のパ
ターンを示す。また才４図に、才３図に対応する断面図
を示す。才３図および才４図において、１はＰ−ウェル
、２．３および１２はＰ散拡散層、４．５および１３は
アルミ配線、６．７および１４はＰ散拡散層とアルミ配
線とのコンタクト、８，９．１０および１５はＳｉｎ、
による絶縁層、１１はＮ型基板、１６は絶縁層保護膜で
ある。Figure 5 shows a pattern of a P-well resistor according to another embodiment of the present invention. In addition, Fig. 4 shows a sectional view corresponding to Fig. 3. In Figures 3 and 4, 1 is a P-well, 2.3 and 12 are P-diffusion layers, 4.5 and 13 are aluminum wiring, and 6.7 and 14 are connections between the P-diffusion layer and aluminum wiring. Contact, 8, 9.10 and 15 are Sin,
11 is an N-type substrate, and 16 is an insulating layer protective film.
矛３図は、２つのウェル抵抗を直列に接続した例であり
、逆バイアス電圧の影響を除けば、ウェル抵抗部の長さ
の比であるり、：Ｌ、の抵抗比を示すと考えられる。Figure 3 shows an example in which two well resistors are connected in series, and excluding the influence of reverse bias voltage, it can be thought that it shows the ratio of the length of the well resistor part, or the resistance ratio of :L. .
ウェル抵抗を用いる場合には、使用バイアス条件による
逆バイアス電圧係数の影響を加味した設計を行なう必要
がある。逆バイアス電圧係数をほぼ決定するパラメータ
であるところの基板およびシェルの不純物濃度は、ＭＯ
Ｓトランジスタのｖｔｈなとの特性を決定する重要なパ
ラメータなので、（ウェルを抵抗として用いる、用いな
い釦関らず）グミセス工程において厳密に管理されてい
る。このため、逆バイアス電圧係数はあまりバラつくこ
とはない。代表的な値としては、２〜ａｓ／Ｖ程度であ
る。したがって、直流的な使い方（抵抗端子の電圧が変
動しない様な使い方）は十分可能である。When using a well resistor, it is necessary to perform a design that takes into account the influence of the reverse bias voltage coefficient depending on the bias conditions used. The impurity concentration of the substrate and shell, which is a parameter that approximately determines the reverse bias voltage coefficient, is
Since it is an important parameter that determines the characteristics such as vth of the S transistor, it is strictly controlled in the gummy process process (regardless of whether the well is used as a resistor or not). Therefore, the reverse bias voltage coefficient does not vary much. A typical value is about 2 to as/V. Therefore, direct current use (use where the voltage at the resistor terminal does not fluctuate) is fully possible.
本発明によれば、ウェルを用いたモノリシック抵抗にお
いて、抵抗端子部の形状効果をほぼ無視することが可能
であり、比精度（相対精度）の高い抵抗を作ることが出
来る。According to the present invention, in a monolithic resistor using a well, the shape effect of the resistor terminal portion can be almost ignored, and a resistor with high specific accuracy (relative accuracy) can be manufactured.
、ｔＦ１図は本発明の半導体装置の実施例を示す平面２
才２図は矛１図の断面図２才３図は本発明の別の実施例
を示す平面図、才４図は才５図の断面図である。
１・・・Ｐ−ウェル、２，３および１２・・・Ｐ型拡散
鳳＋ １−Ｎ型基板。
第１図
才２図, tF1 is a plane 2 showing an embodiment of the semiconductor device of the present invention.
Figure 2 is a sectional view of Figure 1, Figure 2 is a plan view showing another embodiment of the present invention, and Figure 4 is a sectional view of Figure 5. 1...P-well, 2, 3 and 12...P type diffusion hole + 1-N type substrate. Figure 1 Figure 2
Claims (1)
半導体基板と、前記半導体基板上に形成され半導体基板
と異なる導電性を示すウェル領域とを有する、相補型絶
縁ゲートトランジスタ装置において、 ウェル領域と同時に形成される高抵抗領域と、前記高抵
抗領域の両端に位置し、かつ、上記高抵抗領域より幅が
広い前記半導体基板上に形成される絶縁ゲートトランジ
スタのソースおよびドレイン領域と同時に形成される低
抵抗領域とを有することを特徴とする半導体装置。[Scope of Claims] A complementary insulated gate comprising a semiconductor substrate exhibiting conductivity of either P-type or N-type, and a well region formed on the semiconductor substrate and exhibiting conductivity different from that of the semiconductor substrate. In the transistor device, a high resistance region is formed at the same time as a well region, and a source and an insulated gate transistor are formed on the semiconductor substrate, which are located at both ends of the high resistance region and have a width wider than the high resistance region. A semiconductor device characterized by having a low resistance region formed at the same time as a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60088583A JPS61248460A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60088583A JPS61248460A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61248460A true JPS61248460A (en) | 1986-11-05 |
Family
ID=13946863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60088583A Pending JPS61248460A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248460A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5891500A (en) * | 1995-10-12 | 1999-04-06 | E. I. Du Pont De Nemours And Company | Packaging films capable of being heat-sealed closed and thereafter peeled open |
-
1985
- 1985-04-26 JP JP60088583A patent/JPS61248460A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5891500A (en) * | 1995-10-12 | 1999-04-06 | E. I. Du Pont De Nemours And Company | Packaging films capable of being heat-sealed closed and thereafter peeled open |
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