JPH05128236A - Printed circuit board pattern inspecting device - Google Patents

Abstract

PURPOSE:To remove and inspect a pseudo fault generated at the time of inspecting a printed circuit board pattern appearance. CONSTITUTION:An objective pattern is scanned by a photoelectric conversion scanner 1, the binary picture of the pattern is obtained by a binary circuit 2, and exclusive mask for removing the pseudo fault, especially a clearance pseudo fault, is generated, and a design rule inspection is operated by operating the mask. At the time of generating the exclusive mask, first of all, the binary picture is line-thinned by a line thinning part 3, a land connecting point is extracted by a characteristic point extracting mask by a land characteristic point extracting part 4, and a window for designating a land area is generated by a land area window generating part 5 by using the land connecting point as a center. On the other hand, an inverted thin line picture pattern is obtained by line-thinning the pattern obtained by inverting the binary picture by an inverting and line-thinning part 6. Then, only the pattern of the window is segmented from the inverted thin line picture pattern by the land area window, and it is enlarged in order to obtain the clearance pseudo fault removing mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board pattern inspection device, and more particularly to a printed circuit board pattern inspection device for detecting a pattern defect portion by referring to design rules such as pattern thinness, thickness and space (clearance).

[0002]

2. Description of the Related Art A conventional printed circuit board pattern inspection apparatus is, for example, "automatic visual inspection of printed circuit board".
Mechanical Design Vol, 29, No, 2Pp 87-91, 19
As shown at 85, there is a printed circuit board pattern inspection device using a dedicated length measuring sensor.

FIG. 9 shows the above-described length measuring sensor, and the length measuring sensor is composed of four length measuring pixel rows 103 extending on the radiation with respect to the inspection center 102. Each length measurement sensor 101
Form a symmetrical pair with respect to the inspection center, and
The number of pixels corresponding to the target inspection pattern in 3 is measured, and when the preset pixel row condition for each defect type is satisfied, the inspection center 102 performs the design rule inspection using the means that is the defective portion. Is.

[0004]

The above-mentioned conventional printed circuit board pattern inspection device detects a defect by using a dedicated length measuring sensor, but it is not actually a defect for clearance defect detection. There is a drawback that the land area with sub-brand is mistakenly recognized as a defective clearance, that is, a clearance pseudo defect is detected.

[0005]

A printed circuit board pattern inspection apparatus according to the present invention comprises a binarization circuit for converting an input image obtained by scanning an inspected printed circuit board pattern with a photoelectric conversion scanner into a binarized image. A thinning portion for thinning the binary image output by the binarizing circuit to output a thin line image, and a land connection point is extracted by extracting feature points of a pattern on the thin line image output from the thinning portion. A land connection point extraction unit, a land region window generation unit that generates a window designating a land region of a preset size centered on the land connection point, and a binary image output from the binarization circuit. An inversion thinning unit that thins out a region other than the pattern part of and outputs an inversion thin line image,
A clearance pseudo defect removal mask generation unit for generating a mask window in which the data of the inverted thinned image in the cut out land area window is expanded a predetermined number of times, and on the binary image output from the binarization circuit. And a design rule inspection unit for outputting a defect of the pattern by applying a mask window generated from the clearance pseudo defect removal mask generation unit to the pattern to inspect the design rule to see if the design rule is satisfied. Composed.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The operation of this embodiment will be described below with reference to the signal flow shown in FIG.

The pattern on the printed circuit board to be inspected is scanned by the photoelectric conversion scanner 1, and the binarization circuit 2 binarizes the pattern part to "1" and the other parts to "0". A binarized image f is obtained.

FIG. 2 is a view showing an example of the binarized image f, and FIG. 2 includes a land portion 9 with a subland 10 and a normal wiring pattern portion 11. In the example of FIG. 2, points a and b indicate portions that can be erroneously recognized as defective clearances in the conventional printed circuit board pattern inspection apparatus. Although the points a and b are not actually defects, the distance between the sub-brand 10 and the wiring pattern portion 11 thereunder is
Since they are smaller than the clearance standard of ordinary wiring patterns, they are detected as pseudo defects only by the conventional design rule inspection. In this embodiment, in order to avoid the detection of the pseudo defects that occur near the land, the pseudo defects can be removed by the following operation.

First, the thinning section 3 inputs the binarized image f and thins the pattern section. The thinning here is performed by setting the thin line parameters so that the processing is stopped in the state where the land pattern is stored in the land portion 9 with the width of the normal wiring pattern portion 11 being one pixel. FIG. 3 is an example of the thin line image. Here, the binary image f shown in FIG.
The thin line image g is shown in FIG. As shown in FIG. 3, the normal wiring pattern portion 11 has a fine line pattern 12 having a width of 1 pixel, and the land portion 9 has a wiring pattern 13 having a shape having a width of 2 pixels or more.

Next, the land connection point extraction unit 4 extracts the land connection points by extracting the feature points of the pattern using the thin line image g which is the processing result of the thin line lower portion 3. The processing here will be described in more detail with reference to FIG. 4A and 4B are operation explanatory diagrams of the land connection point extraction unit. FIG. 4A is a land connection point, and FIG. 4B is a 3 × 3 used for land connection point extraction.
Shows a mask window. In order to extract the feature points, the 3 × 3 mask window 14 shown in FIG. 4B is used to scan the thin line images that are successively input to scan the “0” and “1” data in the mask window 14. Get the placement. This data is compared with the data arrangement in the 3 × 3 mask window that may occur at the land connection points registered in advance in the table 14 ', and if there is a match, that point is extracted as the land connection point R. The extraction result h is sent to the next land area window generation unit 5. The land area window generation unit 5 uses the extraction result h of the land connection point extraction unit 4 to generate a window 0 of a preset size centered on the obtained land connection point R. As shown in FIG. 5, the land area window 15 generated around the land connection point R is generated.

This mask window 15 has a land connection point R.
However, if the size includes the points a and b, which may be clearance pseudo defects, the mask can be used as a mask for removing the clearance pseudo defects, but the clearance is not a problem. It occurs up to all lands. Therefore, in order to specify more clearly, the following operations are performed.

In addition to the above operation, the inversion thinning unit 6 inputs the binary image f output from the binarization circuit 2 and inverts the binary data to "0" for the pattern part, and "1" for the other parts. After that, the inverted thin line image P is obtained by thinning the data of the value “1”. The thinning here is to perform thinning processing for the clearance reference value defined by the design rule. FIG. 6 is a diagram showing an example of the thinning result by the inversion thinning unit 6, and here shows the case where the inversion thinning is applied to the binary image f in FIG. As shown in FIG. 2, the inverted thin line image data 16 has a width of 1 pixel at the points a and b, which may cause a clearance defect due to the inversion thinning, and has a width of 2 pixels or more at other portions.

Next, the clearance fine defect removal mask generator 7 inputs the inverted thin line image P, and the inverted thin line image data 16 is multiplied by the window 15 generated by the land area window generator 5 to obtain the data in the window 15. Only to extract. FIG. 7 is an example in which the land area window is applied to the inverted thin line image, and here, the land area window 15 of FIG. 5 is applied to the inverted thin line image data 16 of FIG. After cutting out only the inverted thin line image data 17 and 18 in the land area window 15, the data is expanded. FIG. 8 is a diagram showing an example of the clearance pseudo defect removal mask. Expansion is performed a predetermined number of times around the inverted thin line image data 17 and 18 in the land area 15 shown in FIG. In FIG. 8, the area generated by expansion is the clearance pseudo defect removal mask 19. In FIG. 8, M1 and M2 are the clearance pseudo defect removal mask 19 for the inverted thin line data 17 and 18 in the land area window, respectively.
It shows that it becomes. The above is the operation until the clearance pseudo defect removal mask is generated. Then, the design rule inspection unit 8 applies the mask g generated by the clearance pseudo defect removal mask generation unit 7 to the binary image f, and outputs only the defects other than the defects in this mask as the defect portion r.

[0015]

The printed circuit board pattern inspecting apparatus of the present invention has a problem that many pseudo defects are generated only by the conventional design rule inspection, whereas the clearance pseudo defects particularly in the land portion are removed. Since the design rule inspection is performed while the mask is generated, there is an effect that the false defect detection can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an example.

FIG. 2 is a diagram showing an example of a binary image obtained by a binarizing circuit 2 in FIG.

FIG. 3 is a diagram showing an example of a thin line image obtained by a thinning unit 3 shown in FIG.

4A and 4B are diagrams for explaining the operation of a land connection point extraction unit 4 in FIG. 1, where FIG. 4A is an example of land connection points, and FIG. 4B is a diagram of a 3 × 3 mask window used for land connection point extraction. Is.

5 is a diagram of a land area window generated by a land area window generation unit 5 in FIG.

FIG. 6 is a diagram of an inversion thin line image by an inversion thinning unit 6 in FIG.

FIG. 7 is a diagram in which a land area window is applied to an inverted thin line image in the clearance pseudo defect removal mask generation unit 7 in FIG.

8 is a diagram of a clearance pseudo defect removal mask by a clearance pseudo defect removal mask generation unit 7 in FIG.

FIG. 9 is a diagram of a length measuring sensor used in a conventional printed circuit board pattern inspection device.

[Explanation of symbols]

 1 Photoelectric conversion scanner 2 Binarization circuit 3 Thinning section 4 Land connection point extraction section 5 Land area window generation section 6 Inversion thinning section 7 Clearance pseudo defect removal mask generation section 8 Design rule inspection section 9 Land section 10 Subbrand section 11 wiring pattern portion 12 wiring pattern portion thin line image data 13 land portion thin line image data 14 feature extraction 3 × 3 mask window 14 ′ 3 × 3 mask window data arrangement table 15 land area window 16 inverted thin line image data 17 land area window Reverse fine line image data of 18 Reverse fine line image data in land area window 19 Clearance pseudo defect removal mask 101 Length measuring sensor 102 Inspection center 103 Length measuring pixel column

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical indication H05K 3/00 Q 6921-4E

Claims (1)

[Claims] 1. A binarization circuit for converting an input image obtained by scanning a printed circuit board pattern to be inspected by a photoelectric conversion scanner into a binarized image, and a thin line in the binary image output by the binarized circuit. The thinning part that outputs the thinned line image and the land connection point extraction part that extracts the land connection point by extracting the feature points of the pattern on the thin line image output from this thinning part, and the land connection point A land area window generating section for generating a window for designating a land area of a preset size, and an area other than the pattern area on the binary image output from the binarizing circuit is thinned and inverted. An inversion thinning unit that outputs a thin line image, and a mask window that expands the data of the inversion thinned image in the clipped land area window a predetermined number of times to generate a mask window. The Alanse pseudo defect removal mask generator and the pattern on the binary image output from the binarization circuit are multiplied by the mask window generated by the clearance pseudo defect removal mask generator to satisfy the design rule. A printed circuit board pattern inspecting device, comprising: a design rule inspecting unit that inspects whether or not the pattern is present and outputs a pattern defect.