JPH11101752A - Pattern inspection apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the detection accuracy of a flaw by masking the line width increase inferiority generated for a pad for QFP(quad flat package) of a fine pitch. SOLUTION: A line width increase detection circuit 3 for detecting line width increase inferiority from binary image data obtained by binarizing image data obtained by scanning a pattern by a pad for QFP by a binarization circuit is equipped while a mask data forming circuit 7 detecting the end point of the pad from thinning image data obtained by thinning processing of the pattern of the pad part until the pattern becomes one pixel by the end point detecting mask of an end point detection circuit 5 and subsequently collating the same with the mask data of a plurality of registered QFP pad sizes and taking cut false flaw mask data from preliminarily registered data on the basis of the position and size of QFP detected by a QFP detection circuit 6 is provided. A mask circuit 8 removes the line width increase inferiority from the false flaw mask data to output genuine line width increase flaw data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern inspection apparatus for detecting a defective portion of a pattern by performing image processing on a printed pattern on a printed circuit board and inspecting a processing result according to a predetermined rule. Qu
The present invention relates to a pattern inspection apparatus capable of improving the accuracy of detecting a defect generated in a pad for mounting an ad flat package.

[0002]

2. Description of the Related Art Conventionally, in this type of pattern inspection apparatus,
For example, there is a technique described in JP-A-7-20061.

In this apparatus, as shown in FIG. 5, a video signal obtained by scanning a wiring pattern to be inspected by a photoelectric conversion scanner 101 is converted into a binarizing circuit 102.
However, the analog-to-digital conversion is performed, and the noise is removed by smoothing.
Binary image data is obtained by binarizing the other parts into numerical values “0”.

The binary image data is subjected to thinning of the wiring pattern by the thinning circuit 103 to become thin line image data. The land connection point extraction unit 104 extracts land connection points by extracting the features of the pattern using the thin line image data obtained as a result of the processing by the thinning circuit 103. Then
The land area window generation unit 105 generates a window of a preset size around the land connection point of the extraction result obtained from the land connection point extraction unit 104.

On the other hand, the binary image data is input to an inversion thinning circuit 106 and is inverted by the inversion thinning circuit 106, and the portion of the wiring pattern is a numerical value "0" and the other portions are a numerical value "1". Are converted into inverted thin line image data binarized into the image data.

[0006] Clearance pseudo defect removal mask generator 1
In step 07, only the inverted fine line image data obtained from the inverted thinning circuit 106 is cut out from the image data in the land area window obtained from the land area window generating unit 105, and the cut out data is expanded (enlarged). . The area generated by this expansion becomes a clearance pseudo defect removal mask.

Next, the design rule inspection unit 108 applies the clearance pseudo defect removal mask of the binary image data, and detects and outputs only a defect other than the clearance pseudo defect removal mask as a true defect.

[0008]

In the above-described conventional pattern inspection apparatus, since the pattern is inspected by applying the inverted fine line image data in the through-hole land area, the pattern inspection is performed based on the clearance defect generated near the through-hole land. Although a pseudo defect can be masked, there is a problem that it is not possible to mask a defect caused by a line width increase occurring in a fine pitch QFP pad.

An object of the present invention is to solve the above problems and to provide a pattern inspection apparatus capable of improving the defect detection accuracy by masking a line width defect occurring in a fine pitch QFP pad. .

[0010]

SUMMARY OF THE INVENTION A pattern inspection apparatus according to the present invention is a pattern inspection apparatus which performs image processing on a printed pattern on a printed circuit board and inspects a processing result according to a predetermined rule to detect a defective portion of the pattern. , Fine pitch QFP (Quad Flat Package)
A binarizing circuit for binarizing image data obtained by scanning the pattern with a pad for mounting the pattern to obtain binary image data, and a line for detecting a line-thickness defect on one side from the binary image data A widening detection circuit, and performs thinning processing from the binary image data until the pattern of the pad portion becomes one pixel, and detects an end point of the pad from the thinned image data as a predetermined end point. And a QFP for detecting the position and size of the QFP by comparing the detected end point with mask data of a plurality of QFP pad sizes registered in advance.
A detection circuit for extracting pseudo defect mask data from data registered in advance based on the position and size of the QFP, and removing the line width defect detected by the line width detection circuit from the pseudo defect mask data; A defect data output circuit for outputting true line width defect data.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

In the pattern inspection apparatus shown in FIG. 1, a photoelectric conversion scanner 1, a binarization circuit 2, a line width detection circuit 3, a thinning circuit 4, an end point detection circuit 5, a QFP detection circuit 6, a mask data generation A circuit 7, a mask circuit 8, and a measurement circuit 9 are provided.

The photoelectric conversion scanner 1 scans the pattern to be inspected and sends the read image data to the binarization circuit 2. The binarizing circuit 2 converts the received image data into binary image data having a pattern portion of a numerical value "1" and the other portions of the pattern portion having a numerical value "0", and the line width thickening detecting circuit 3 and the thinning. It shall be sent to the circuit 4.

When the line width thickening detecting circuit 3 detects a pattern having a line width larger than a predetermined width from the received binary image data, the masking circuit 8 generates the line width thickening defect data.
Shall be sent to

On the other hand, the thinning circuit 4 repeats the thinning process on the received binary image data, and sends the thinned image data in which the QFP pad portion becomes one pixel to the end point detecting circuit 5. The endpoint detection circuit 5 compares the received thinned image data with a pattern at a predefined and held endpoint, and when detecting a match, sends the detected endpoint data to the QFP detection circuit 6. .

The QFP detection circuit 6 converts the received end point data into a QFP detection signal indicating the center of the QFP and a mask size selection signal indicating the size of the QFP when the predetermined condition is satisfied. It shall be output. The mask data generation circuit 7 generates pseudo defect mask data from data defined and held in advance, based on the QFP detection signal received from the QFP detection circuit 6 and the mask size selection signal, and outputs the data to the mask circuit 8. Shall be.

The mask circuit 8 converts the line width failure data received from the line width detection circuit 3 into a mask data generation circuit 7.
And removes the true line width defect data from the pseudo defect mask data received from the measuring circuit 9.
The measuring circuit 9 detects a true defect occurrence position from the received true line width defect data.

Next, referring to FIG. 1 and FIGS. 2 to 4, specific operation functions in detail will be described.

FIG. 2A is an explanatory diagram showing an example of pad data processed by the thinning circuit 4. Thinning circuit 4
Is obtained by sequentially erasing the pattern portion of the binary image data 20 from the periphery and repeating the thinning process until the pad portion becomes a line of one pixel, so that the center line of the wiring pattern is shifted from the end point 21 which is the center of the QFP pad. The thinned image data 22 is generated by a one-pixel pattern formed over the entire area.

In FIG. 2B, a line of one pixel based on the thinned image data 22 is not arranged on a straight line due to the thinning processing, and some pixels are shifted by one to an adjacent pixel position. Is shown. The end point detection mask 23 for detecting the end point 21 is composed of 3 × 3 pixels as shown.

FIG. 3 is an explanatory diagram showing mask data used by the endpoint detection mask 23 to detect an endpoint. As shown in the figure, only one pixel is included in the thinned image data 22 at eight peripheral pixel positions with respect to the pixel at the center end point 21, and the thinned image data 22 does not appear at other pixel positions. .

The end point detecting circuit 5 scans the sequentially input thinned image data 22 using the mask data shown in FIG. Is detected as the end point 21.

Next, referring to FIG. 4 and FIG.
Will be described.

As shown in the figure, QFP detecting masks M1 to M4 are arranged on four sides corresponding to the pad shape of the QFP, and the QFP detecting mask M1 has end points E1-1 to E1-n,
Similarly, the QFP detection mask M4 has the end points E4-1 to E4-1.
E4-n are included. The QFP detection signal P is shown at the center of the QFP.

The QFP detection circuit 6 shown in FIG. 1 includes end points E1-1 to E1-existing in the QFP detection masks M1 to M4, respectively.
The numbers n, ..., E4-1 to E4-n are registered in advance as QFP detection counts. QFP detection circuit 6
Is the mask M for QFP detection detected by the end point detection circuit 5.
From 1 to M4, the end points E1-1 to E1-n, ..., E4-1 to E4-n
Each is scanned and detected, and the QFP detection mask M
The numbers in each of 1 to M4 are compared with the above-mentioned numbers registered in advance, and if the numbers are within a specified value range, the QFP detection signal P
And QFP detection masks M1 to M4 when the conditions match.
And a mask size selection signal, which is the size of the mask data, is output to the mask data generation circuit 7.

As described above, the mask data generation circuit 7
Generates pseudo-defect mask data from the QFP detection signal P and the mask size selection signal, and the mask circuit 8 receives the pseudo-defect mask data and compares it with the separately received line width defect data to remove the pseudo defect. .

In the above description, the functional blocks have been illustrated and described.
The present invention is free as long as the above functions are satisfied, and the above description does not limit the present invention.

[0029]

As described above, according to the present invention, image data obtained by scanning a pattern is binarized to obtain binary image data. On the other hand, thinning processing is performed until the pattern of the pad portion becomes one pixel, and an end point on the pad is detected by a predetermined end point detection mask from the thinned image data resulting from the processing, and the detected end point is detected. The position and size of the QFP are detected by comparing with mask data of a plurality of QFP pad sizes registered in advance, and the pseudo defect mask data is extracted from the data registered in advance based on the position and size of the QFP. A pattern inspection apparatus is provided which removes the line width defect detected by the line width detection circuit from the pseudo defect mask data and outputs true line width defect data. With this configuration, the fine pitch Q
The effect of improving the defect detection accuracy can be obtained by masking the line width defect occurring in the FP pad.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of binary image data and an end point detection mask in FIG. 1;

FIG. 3 is an explanatory diagram of mask data exemplifying an end point detection mask in FIG. 2;

FIG. 4 is an explanatory diagram of QFP detection in which QFP detection masks are arranged on four sides corresponding to the QFP pad shape in the present invention.

FIG. 5 is a functional block diagram showing an example of the related art.

[Explanation of symbols]

 Reference Signs List 1 photoelectric conversion scanner 2 binarization circuit 3 line width thickening detection circuit 4 thinning circuit 5 endpoint detection circuit 6 QFP detection circuit 7 mask data generation circuit 8 mask circuit 9 measurement circuit 20 binary image data 21 endpoint 22 thinning image data 23 Endpoint detection mask

Claims (3)

[Claims] 1. A pattern inspection apparatus that performs image processing on a printed pattern on a printed circuit board and inspects a processing result according to a predetermined rule to detect a defective portion of the pattern.
e) binarizing image data obtained by scanning the pattern with a pad for mounting (2) to obtain binary image data;
A binarizing circuit, a line-thickness detecting circuit for detecting a line-thickness defect on the one hand from the binary image data, and a thinning process from the binary image data until the pattern of the pad portion becomes one pixel And an end point detection circuit for detecting an end point of the pad from the thinned image data resulting from the processing using a predetermined end point detection mask, and comparing the detected end point with mask data of a plurality of QFP pad sizes registered in advance. Q to detect the position and size of the QFP
Pseudo defect mask data is extracted from data registered in advance based on the position and size of the FP detection circuit and the QFP, and a line width defect detected by the line width detection circuit is removed from the pseudo defect mask data. A defect data output circuit that outputs true line width defect data. 2. The mask according to claim 1, wherein the end point detection mask is composed of 3 × 3 pixels having a center pixel as an end point, and the end point detection circuit detects a single pixel around the center pixel. A pattern inspection apparatus for detecting the end points based on data. 3. The QFP detection circuit according to claim 1,
A mask for QFP detection corresponding to a plurality of shapes of the QFP pad, the number of the end points present in each of the masks, and a QFP center point serving as a QFP detection signal in advance, with respect to the end point detected by the end point detection circuit; Scan sequentially and compare the number of the endpoints present in each of the QFP detection masks with a pre-registered numerical value, and if the number is within a specified value range, the corresponding QFP detection signal and the size of the QFP detection mask And a pattern inspection device for outputting a pattern.