JP2500758B2 - Printed circuit board pattern inspection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board pattern inspection device, and more particularly, to a printed circuit board pattern inspection for detecting a defective portion of a pattern by referring to a design rule for a clearance (clearance) such as a thin pattern width or a thick pattern width. Regarding the device.

[0002]

2. Description of the Related Art A conventional printed circuit board pattern inspection technique is, for example, "Printed circuit board inspection using radial matching", Journal of Precision Engineering, Vol. 56, No. 8,
There is a pattern inspection device using a dedicated length measuring sensor and a pattern code as shown in pp30 to 33, 1990.

The conventional technique will be described below with reference to the drawings.

FIG. 10 is an explanatory diagram for explaining an inspection method of a pattern inspection apparatus using the above-described length measuring sensor. FIG. 10A shows 16 length measuring sensors 102 each including a group of pixels radially extending with respect to the inspection center 101. Each length measurement sensor 102 forms a symmetrical pair with respect to the pixel of the inspection center 101, and codes the length and symmetry of the pattern measured by each length measurement sensor 102 as elements. Then, the coded data is compared with a previously created coding dictionary to determine whether the code of the target pattern is a point of a normal pattern or a point of a defective pattern.

FIGS. 10 (b), 10 (c) and 10 (d) are schematic diagrams showing examples of coding determination by the length measuring sensor 102 for various patterns. In these figures, (b) shows a normal pattern, and (c) shows a line thinning defect. In the case of the normal pattern of (b), all four directions of the pattern measured by the length measuring sensor 102 show symmetry, and the vertical direction (90 ° direction) is longer than the length measuring sensor. In the case of the line-thinning defect of (c), the pair of length measurement sensors in the vertical direction of the pattern
03 is the same as the normal pattern, but in the left-right direction (0 ° direction)
Although the symmetry in the length measurement sensor pair 104 is preserved, the length becomes short, and the length measurement sensor pair 105 in the oblique direction (45 °) becomes asymmetric. On the other hand, (d) shows a case of a line thick defect, which is equal to the normal pattern in the vertical direction and the diagonal direction, but is asymmetric in the horizontal direction. Such measurement results are coded to determine whether the pattern is normal or defective.

[0006]

In the above-mentioned conventional pattern inspection, the pattern state of the inspection central portion is coded by using a lengthwise extending sensor and the defect is detected by comparing with a dictionary code created in advance. However, there is a drawback in that a portion in which the through hole land is close to the wiring pattern is detected as a defect like a normal pattern interval defect (clearance defect) portion. For example, as will be described later, points a and b shown in FIG. 2 are detected as defects.

[0007]

[Means for Solving the Problems ] To solve the above problems
Therefore, the printed circuit board pattern inspection apparatus of the present invention is a photoelectric conversion scanner that optically scans a target wiring pattern and outputs a video signal corresponding to the reflected light, and a video signal from this photoelectric conversion scanner as a wiring pattern section. A binarization circuit for converting other parts to binarized image data, and up to the number of steps in which the line width of the wiring pattern portion is 1 pixel width with respect to the binary image data obtained by this binarization circuit. A thinning circuit that outputs thinning image data of a thinning pattern, and a thinning line image data obtained by this thinning circuit has a width of 2 pixels or more.
Land connection point and 1 pixel , which is the point to connect with the pattern
There is a feature point extraction unit that extracts a branch point, which is a point connecting with a width pattern, with a 3 × 3 mask, and this land connecting point .
There is a land connection region window generator for generating a window showing the lands connection area size set in advance around a branch point, in a region other than the pattern portion on the binary image output from the binarizing circuit An inversion thinning circuit that thins the line and outputs an inversion thin line image, and a clearance pseudo defect removal mask that expands the inversion thin line image in the window of the land connection region window generation part by a preset amount A pseudo defect removal mask generating section, and an inspection section that removes a portion of the clearance pseudo defect removal mask from the pattern on the binary image output from the binarization circuit to detect a defective section. To be done.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Hereinafter, the operation will be described along the signal flow shown in FIG.

The video signal e obtained by scanning the wiring pattern to be inspected by the photoelectric conversion scanner 1 is A / D converted by the binarizing circuit 3 and further noise is removed by smoothing to make the pattern portion "1". The binary image data f is obtained by binary lending the "," and other parts to the value of "0".

FIG. 2 is a diagram showing an example of the binary image f, and shows a pattern including a land portion 9 with a subland 10 and a normal wiring pattern portion 11. According to the conventional printed circuit board pattern inspection in the example of FIG.
The point b is a portion that can be erroneously detected as a defective clearance. The points a and b are not actually defects, but the distance between the sub-brand 10 and the wiring pattern portion 11 thereunder is
Since they are smaller than the standard of the distance between the usual wiring patterns, these are detected as pseudo defects together with actual defects only by the conventional design rule inspection.

The thinning circuit 3 shown in FIG. 1 inputs the binary image f and thins the pattern. In the thinning here, the normal wiring pattern portion 11 is thinned until the width becomes 1 pixel. As a result, the land portion 9 stops processing while the shape is preserved. FIGS. 3A and 3B are examples of thin line images, each showing a thin line image g obtained by thinning the binary image f shown in FIG. 2 by the thinning circuit 3. As shown in FIGS. 3A and 3B, the normal wiring pattern portion 11 has a fine line pattern 12 having a width of 1 pixel, and the land portion 9 has a fine line pattern 13 having a shape having a width of 2 pixels or more. . In particular, at the connection portion (point R) in the thin line image of the land and the wiring pattern, depending on the diameter and position of the through-hole formed on the land, as shown in FIG.
When connecting with a pattern having a width of 2 pixels or more as described above (such a case is referred to as a land connection point) and when connecting as a branch point with a pattern having a width of 1 pixel as shown in FIG. There is something called a branch point).

Next, the land connection point extraction unit 4 extracts the land connection and the branch point by the feature extraction of the pattern using the thin line image g obtained by the processing of the thinning circuit 3. 4A and 4B are diagrams for explaining the operation of the land connection point extraction unit. FIG. 4A shows land connection points, and FIG. 4B shows a 3 × 3 mask used for land connection point and branch point extraction. In order to extract these feature points, the 3 × 3 mask 14 shown in FIG. 4B is used to scan the thin line images that are successively input to scan “0” and “1” in the 3 × 3 mask 14. "Get the placement of the data. When this data is compared with the data arrangement in the 3 × 3 mask shown in FIG. 5 which may occur at a land connection point or a branch point registered in advance in a table (not shown) and there is a match, 3 × of that point 3 The center of the mask 14 is extracted as a land connection point or a branch point R. Here, the data arrangement in the 3 × 3 mask registered in the table in advance is a data arrangement that can occur at a point (land connection point) where a pattern having a width of 2 pixels or more and a pattern having a width of 1 pixel are connected on the thin line image ( 5 (a)) and data arrangement (FIG. 5 (b)) that can occur at a branch point (branch point) of a pattern of one pixel width. The extraction result is sent to the next land area window generation unit 5.

Although only the land connection point R is shown in FIG. 4 as a point to be extracted by the land connection point extraction unit 4, a point S where the wiring branches is actually extracted. However, the subsequent processing is performed on the point S in exactly the same manner as in the case of the point R, and the final result is exactly the same as the case where the subsequent processing is performed only on the point R, and therefore the description of the point S will be omitted.

The land area window generation unit 5 uses the extraction result h of the land connection point extraction unit 4 to generate a window of a preset size centered on the obtained land connection point and branch point R. FIG. 6 shows a land area window 15 generated around the land connection point R. This window 15 is generated with a size including the points a and b which can be clearance pseudo defects centering on the land connection point and the branch point R, but first in all the land portions where the clearance is not particularly problematic. It will be included in the window 15. Therefore, the following operation is performed in order to clearly specify the problem area.

In addition to the above operation, the inversion thinning circuit 6
The binary image f output from the binarization circuit 2 is input, the binary data is inverted, the pattern part is changed to "0", and the other is changed to "1". An inverted thin line image p is obtained by thinning the data.
The thinning here is to thin the clearance reference amount defined by the design rule. FIG. 7 is a diagram showing an example of the thinning result by the inversion thinning circuit 6, and here shows the case where the inversion thinning is applied to the binary image f in FIG. As shown in FIG. 7, the inverted thin line image 16 has a width of 1 pixel at the points a and b where the clearance may be defective due to the thinning of the inverted line, and the other portions have a width of 2 pixels or more.

Next, the clearance pseudo defect removal mask generator 7 inputs the inverted thin line image p obtained by the inverted thin line thinning circuit 6, applies the land area window 15 to the inverted thin line image 16, and the image in the window 15 is applied. Only to extract. FIG. 8 shows a case where the land area window 15 of FIG. 6 is applied to the inverted thin line image 16 of FIG. After cutting out only the reverse image data 17 and 18 in the land area window 15, expansion of this data (image data 17 and 18)
For each of them, the maximum value is expanded by a constant value and the minimum value is expanded by a constant value in both the x-coordinate (horizontal direction) and the y-coordinate (vertical direction). Give. The area refined by this expansion is the clearance pseudo defect removal mask 19 shown in FIG.
Becomes The above is the operation until the clearance pseudo defect removal mask is generated.

Then, the design rule inspection unit 8 applies the pseudo defect mask 19 to the binary image f in response to the processing result g of the clearance pseudo defect removal mask generation unit 7, and only the defects generated at positions other than the mask are received. Is output as a true defect portion r.

[0019]

As described above, in the printed circuit board pattern inspection apparatus of the present invention, a pseudo defect such as a clearance defect occurs in a portion where the distance between the wiring patterns connected to the through hole lands is short in the conventional design rule inspection. However, since the design rule inspection is performed while generating the pseudo defect mask in the through hole land part and the wiring pattern connection part, the detection of the pseudo defect (misinformation)
Is effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a binary image obtained by a binarizing circuit 2 in FIG.

3 is a diagram showing an example of a thin line image of the binarized image of FIG. 2 obtained by a thin line thinning circuit 3 in FIG.

4A and 4B are diagrams for explaining the operation of a land connection point extraction unit 4 in FIG. 1, where FIG. 4A is an example of a land connection point, and FIG. 4B is a 3 × 3 mask window used for land connection point extraction. FIG.

FIG. 5: Pre-registered 3 used in the land connection point extraction unit 4
It is a figure which shows the data in a * 3 mask.

6 is a diagram showing a land area window by a land area window generation unit 5 in FIG.

7 is a diagram of an inversion thin line image by the inversion thinning circuit 6 in FIG.

FIG. 8 is a diagram in which a land area window is applied to an inverted thin line image in the clearance pseudo defect removal mask generation unit 7 in FIG.

9 is a diagram of a clearance pseudo defect removal mask by a clearance pseudo defect removal mask generation unit 7 in FIG.

FIG. 10 is an explanatory diagram for explaining an inspection method of a pattern inspection apparatus using a conventional length measurement sensor. (A) is
FIG. 7 shows a length measurement sensor, and FIGS. 6B, 6C, and 6D are schematic views of an example of coding determination by the length measurement sensor.

[Explanation of symbols]

 1 Photoelectric conversion scanner 2 Binarization circuit 3 Thinning circuit 4 Land connection point extraction unit 5 Land area window generation unit 6 Inversion thinning circuit 7 Clearance pseudo-defect removal mask generation unit 8 Design rule inspection unit 9 Land unit 10 Subbrand unit Reference Signs List 11 wiring pattern 12 thin line pattern of wiring pattern 13 thin line pattern of land 14 3 × 3 mask window 15 land area window 16 inverted thin line image 17,18 inverted thin line image in land area window 19 clearance pseudo defect removal mask 101 inspection center 102 Length measurement sensor 103 Vertical (90 °) direction Length measurement sensor pair 104 Left and right (0 °) direction Length measurement sensor pair 105 Diagonal (45 °) direction Length measurement sensor pair

Claims (2)

(57) [Claims] 1. A photoelectric conversion scanner which optically scans a target wiring pattern and outputs a video signal corresponding to the reflected light, and a binary signal which distinguishes a video signal from the photoelectric conversion scanner between a wiring pattern portion and other portions. A binarization circuit for converting the image data into digitized image data, and for the binary image data obtained by the binarization circuit, the line width of the wiring pattern portion is reduced to one pixel width 2 pixel width from the thinning circuit to output and the thin line image data obtained by this thinning circuit
Land connection points that connect to the above patterns and 1
A feature point extraction unit that extracts a branch point, which is a point connecting with a pixel width pattern, using a 3 × 3 mask, and a window indicating a land connection area of a preset size centered on this land connection point or branch point A land connection area window generation unit, an inversion thinning circuit that thins an area other than the pattern portion on the binary image output from the binarization circuit and outputs an inversion thin line image, and the land connection A pseudo defect removal mask generation unit that generates a clearance pseudo defect removal mask by expanding the inverted thin line image in the window of the region window generation unit by a preset amount, and a binary image output from the binarization circuit. An inspection unit for detecting a defect portion by removing a portion of the clearance pseudo defect removal mask with respect to the upper pattern. Substrate pattern inspection apparatus. 2. The pseudo defect removal mask generation unit further enlarges a maximum value by a constant value and a minimum value for each of the horizontal coordinate and the vertical coordinate of each continuous portion of the inverted thin line image in the window. The pseudo printed circuit board pattern inspection apparatus according to claim 1, wherein the pseudo dummy defect removal mask is generated by enlarging the width of a rectangular area sandwiched by a value reduced by a certain value.