JPH05122642A - Liquid crystal panel driving circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration and residual image of the picture element of a color liquid crystal panel by constructing the device so that voltage having a same polarity cannot be applied to the RGB picture elements on the color liquid crystal panel for a period of 2H. CONSTITUTION:An input video signal in a PAL broadcasting system is led to a video demodulation circuit 1. The input video signal is demodulated by the demodulation circuit 1 to generate the R, G and B signals, and these signals are processed to a state corresponding to a color liquid crystal panel 7 by built-in clamping circuit, white balance circuit and gamma correction circuit, and outputted to an inversion circuit 2. The inversion circuit 2 inverts the polarity of the R, G, and B signals to generate R', G' and B' signals and outputs them to an RGB alternate circuit 3 along with the R, G and B signals. At this time, since a CLY signal providing the timing of alternatively switching between the R, G and B signals and the R', G' and B' signals to be led to the alternate circuit 3 is forcedly inverted, the voltage having the same polarity can be prevented from being applied to the rGB picture elements on a panel 7 for a period of 2H.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a circuit equipped in a television / video device or the like, which is capable of displaying an image on a color liquid crystal panel for the NTSC broadcasting system even though the input video signal is the PAL broadcasting system. Liquid crystal panel drive circuit.

[0002]

2. Description of the Related Art A liquid crystal panel drive circuit of this type has a normal C
The major difference from the RT drive circuit is that in order to prevent deterioration of the liquid crystal due to electrochemical reaction, it is necessary to apply an AC voltage to the pixel instead of a DC voltage, and the horizontal of the field of the input video signal, which is the PAL broadcasting system. The point is that the number of horizontal lines must be regularly thinned to match the number of vertical lines of the color liquid crystal panel for the NTSC broadcasting system.

A conventional liquid crystal panel drive circuit will be described with reference to FIGS. In addition, from the viewpoint of preventing flicker on the screen, the circuit examples given here reverse the polarity of the voltage applied to the pixels of the color liquid crystal panel field by field and line by line, and further reduce the number of lines that are thinned out in odd and even fields. Different. Specifically, the 6th line of every 9th line in the odd field and the 3rd line of every 9th line in the even field are thinned out (hereinafter, this will be referred to as a thinning line for convenience of description).

FIG. 6 is a block diagram of a liquid crystal panel drive circuit. An input video signal of the PAL broadcasting system is introduced into the video demodulation circuit 1. The video demodulation circuit 1 demodulates the input video signal to generate R, G, B signals (see FIG. 8) and outputs the signals to the inverting circuit 2. The inverting circuit 2 inverts the polarities of the R, G, B signals to generate R ', G', B'signals (see FIG. 8),
It is output to the RGB alternating circuit 3 together with the R, G and B signals.

The RGB alternating circuit 3 is composed of three analog switches, and has R, G, B signals and R ', G'.
The B'signal and the B'signal are alternately switched at the timing indicated by the CLY signal (1) described later, and output to the RGB rotation circuit 4 as R / R'.G / G'.B / B 'signals.

The RGB rotation circuit 4 is also composed of analog switches and the like, and R / R'.G /
The order of the G ′ · B / B ′ signals is switched at the timing indicated by the D _X signal, which will be described later, and the signals are output to the X driver circuit 5 as VID1, 2 and 3 signals.

The X driver circuit 5 and the Y driver circuit 6 are connected to the color liquid crystal panel 7. FIG. 7 is a circuit diagram of a peripheral circuit of the color liquid crystal panel, and the color liquid crystal panel 7 will be described with reference to this figure.

The color liquid crystal panel 7 is of a TFT active matrix type, which has a horizontal direction (X direction).
And a plurality of RGB pixels are arranged in the vertical direction (Y direction). The first line in the horizontal direction is RGB in order of 2
-The third line is arranged in the order of GBR and BRG, and the subsequent lines are the above-described repetition to form a matrix-shaped pixel arrangement.

Each of the X driver circuits 5 is composed of an X shift register 51 and a sample holder 52 having the same number of circuits as the number of pixels in the horizontal direction (X direction) of the color liquid crystal panel 7. The X shift register 51 has a D _x signal which is a shift start pulse and a CL which is a shift transfer clock.
Sample holder 52 while X1-4 signals are introduced
Has a set of 3 circuits corresponding to the RGB pixels,
ID1, 2 and 3 signals are introduced respectively.

The Y-triver circuit 6 is composed of a Y-shift register 61 and a buffer 62 each having the same number of circuits as the number of pixels in the vertical direction of the color liquid crystal panel 7. To the Y shift register 61, a D _Y signal which is a shift start pulse and a CLY signal which is a shift transfer clock are introduced.

On the other hand, the input video signal is also input to the synchronizing signal generating circuit 8 in addition to the video demodulating circuit 1 as shown in FIG. The sync signal generation circuit 8 outputs H from the input video signal.
The SYNK signal (horizontal synchronizing signal) and the V SYNK signal (vertical synchronizing signal) are taken out and output to the reference pulse generating circuit 90.

The reference pulse generation circuit 90 uses the H SYNK signal and V
A reference pulse for operating the X / Y driver circuits 5 and 6 based on the SYNK signal, that is, the above-mentioned D _x signal, C
LX1~4 signal, D _Y signal, CLY signal, a digital circuit for generating CLY (1) signal and the like.

FIG. 8 is a timing chart of main signals in the liquid crystal panel drive circuit, in which the signal generated by the reference pulse generation circuit 90 is also included. D _x signal, as shown in the figure is a pulse that is substantially synchronized with the H SYNK signal has a signal pulse has been erased in the thinning lines. The CLY signal is basically a clock inverted at the timing indicated by the H SYNK signal, but is a signal delayed by 1H (H: horizontal scanning period) in the thinning line. The D _Y signal is a signal that outputs a pulse every time the field changes. Although not shown in FIG. 8, the CLY (1) signal is a signal obtained by inverting the CLY signal every time the field changes.

Next, the operation of the liquid crystal panel drive circuit configured as described above will be described. First, when the H SYNK signal becomes active in the first line of the odd field on the input video signal, the CLY signal and CLY signal (1)
And the _Dx signal changes. At this time, CLY signal and CL
Since the Y signal (1) is L, the RGB alternating circuit 3 outputs R, G, B signals. Further, R, G, B signals will appear in the VID1, 2, 3, signals output from the RGB rotation circuit 4.

The R, G and B signals are once taken into the sample holder 52 and then operated according to the CLX1 to CLX signals.
The shift register 51 sequentially reads the sample holder 52 from the left to the right in the figure, and applies the voltages of the R, G, B signals to the R, G, B pixels of the first line on the color liquid crystal panel 7, respectively. To be done.

Then, for the second line of the odd field on the input video signal, when the H SYNK signal becomes active again, the CLY signal changes to H, so that the RGB alternating circuit 3 outputs R '.・ It becomes G '・ B' signal. At the same time, the D _x signal becomes active, so RG
As a result of the change in the contact point of the B rotation circuit 4, the VID1, 2 and 3 signals to be output are G ′, B ′ and R ′.
A signal appears. The voltage of this signal is the color liquid crystal panel 7
The process of applying the second upper line is similar to the above. However, although the pixel arrangement of the second line is different from that of the first line, since the order of the signals is switched by the RGB rotation circuit 4, the GBR of the second line is changed.
Voltages of G ′, B ′, and R ′ signals corresponding to the pixels are applied to the pixels.

Since the same applies to the third and subsequent lines of the odd field on the input video signal, the sixth line which is the thinning line will be described. 6 line is different from other lines, CLY signal and D _x signal does not change. Therefore, from the 5th line to the 6th line, the Y shift register 6 is not shifted and is held in the previous state, while the R, G, B signals latched by the sample holder 52 are read again. It is written again on the fifth line on the color liquid crystal panel 7. In this way, the sixth line of the odd field of the input video signal is thinned out.

On the other hand, the even field is similar to the odd field, except that the thinning line is different and the CLY signal (1) is inverted every time the field changes. By comparison, the polarities of the voltages applied to the RGB pixels of the color liquid crystal panel 7 are reversed.

[0019]

However, in the case of the above-mentioned conventional example, although the polarity of the voltage applied to each pixel of the color liquid crystal panel 7 is inverted for each field and each line, the voltage shown in FIG. As shown in the figure, there is a drawback that a positive voltage may be applied to the RGB pixels of the color liquid crystal panel 7 for a 2H period in the thinning line on the input video signal and the line immediately before the thinning line. Therefore, if a still image is continuously displayed for a long time, not only the RGB pixels of the color liquid crystal panel 7 are deteriorated but also an afterimage is generated for a long time, which affects the image quality.

The present invention was created in view of the above background, and an object thereof is to provide a liquid crystal panel drive circuit which does not cause the above-mentioned drawbacks.

[0021]

A liquid crystal panel drive circuit according to claim 1 of the present invention uses an NTSC broadcast system by regularly thinning out the nth line of a field even though the input video signal is a PAL broadcast system. A liquid crystal panel display circuit for displaying an image on a color liquid crystal panel for display and for inverting the polarity of the voltage applied to the pixels of the color liquid crystal panel for each field and for each line. A sync signal generation circuit for separating the vertical sync signal and outputting the signal, an XY driver circuit having an XY shift register connected to the color liquid crystal panel, and the X / X driver based on the horizontal / vertical sync signals.・ Y
A circuit for generating a pulse signal for operating a shift register or the like, wherein when the input video signal is the nth line of the field, the X shift register start pulse is stopped and this is used as the D _X signal, while the Y shift register The Y shift register transfer clock to be introduced into is delayed by one horizontal scanning period to be a CLY signal, and when the input video signal advances from the (n-1) th line to the nth line of the field, the CLY signal becomes Reference pulse generation circuit that generates a signal that is inverted before and after this and that is output every time the field changes and outputs as a CLY (2) signal, and video demodulation that demodulates the input video signal to generate R, G, B signals A circuit, an inverting circuit that inverts the polarities of the R, G, B signals to generate R ', G', B'signals, and an R, G
・ B signal and R '・ G' ・ B 'signal are alternately switched at the timing indicated by CLY (2) signal, and the switched signal is R
RGB output as / R ', G / G', B / B 'signals
In order to give signals corresponding to the RGB pixels arranged differently for each line in the alternating circuit and the color liquid crystal panel, R
The order of the / R ', G / G', B / B 'signals is changed at the timing indicated by the D _X signal, and the changed signals are changed to VID1.
It is characterized by including an RGB rotation circuit for outputting to the RGB pixels of the color liquid crystal panel via the X driver circuit as a few signals.

A liquid crystal panel drive circuit according to a second aspect of the present invention is a color liquid crystal panel for an NTSC broadcast system by regularly thinning out the nth line of a field while the input video signal is of the PAL broadcast system. On the other hand, a liquid crystal panel display circuit for displaying an image and inverting the polarity of the voltage applied to the pixel of the color liquid crystal panel for each field and for each line, and separating the horizontal and vertical sync signals from the input video signal. And a sync signal generating circuit for outputting the signal concerned, and an X connected to the color liquid crystal panel.
An X / Y driver circuit having a Y shift register and a circuit for generating a pulse signal for operating the X / Y shift register or the like based on a horizontal / vertical synchronizing signal, wherein the input video signal is the nth line of the field. , Then X
The shift register start pulse is stopped and this is used as the D _X signal, while the Y shift register transfer clock introduced to the Y shift register is delayed by one horizontal scanning period and this is used as the CLY signal. An MK signal which is active when the n-th line of the field is generated, and C is generated every time the field changes.
A reference pulse generation circuit that generates a signal in which the LY signal is inverted and outputs it as a CLY (2) signal, a video demodulation circuit that demodulates the input video signal and generates R, G, and B signals, and R.
An inversion circuit that inverts the polarities of the G and B signals to generate R ', G', and B'signals, and the R, G, B, and R ', G',
The B'signal and the CLY (1) signal are switched alternately at the timing indicated by the CLY (1) signal, and the switched signal is R / R'.G / G'.B /
RGB alternating circuit that outputs as B'signal and R / R '.
A mute circuit for forcibly clamping the voltage of the G / G '/ B / B' signals to the common voltage at the timing indicated by the MK signal, and a signal corresponding to RGB pixels arranged differently for each line on the color liquid crystal panel R / R '.
The order of the G / G 'and B / B' signals is changed at the timing indicated by the D _X signal, and the changed signals are output as VID 1, 2 and 3 signals to the RGB pixels of the color liquid crystal panel via the X driver circuit. And an RGB rotation circuit for controlling the liquid crystal panel.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a liquid crystal panel drive circuit according to the present invention will be described below with reference to the drawings. Since the circuit of the embodiment described here is basically the same as the conventional circuit, some of the description will be repeated, but the same circuit configuration will be described in detail below by showing the same numbers.

The circuit of the embodiment reverses the polarity of the voltage applied to the pixels of the color liquid crystal panel for each field and for each line from the viewpoint of preventing flicker on the screen, and the sixth line for every nine lines in the odd field. The same applies to the conventional circuit in that the third line of every nine lines in the even field is thinned out (hereinafter, this will be referred to as a thinned line for convenience of explanation).

FIG. 1 is a block diagram of a liquid crystal panel drive circuit. An input video signal of the PAL broadcasting system is introduced into the video demodulation circuit 1. The video demodulation circuit 1 demodulates the input video signal to generate R, G, and B signals, and the signal is applied to the characteristics of the color liquid crystal panel 7 by a built-in clamp circuit, white balance circuit, and gamma correction circuit. It is designed to be processed according to the above, and then output to the inverting circuit 2.

The inverting circuit 2 inverts the polarities of the R, G, B signals to generate R ', G', B'signals, and outputs the R, G, B signals.
-It outputs to the RGB alternating circuit 3 with B signal. In addition,
If V _cc is the power supply voltage, in the case of normally white, 1
/ 2V _cc ~V voltage between _c is negative, the voltage between the 0 to 1 / 2V _cc a positive electrode, the positive polarity signal and a negative polarity signal 1
It is symmetrical about the voltage of / 2V _cc . On the other hand, in the case of normally black, the opposite is true.

FIG. 2 is a circuit diagram showing a peripheral circuit of the RGB alternating circuit. As shown in this figure, the RGB alternating circuit 3 is
A circuit having three circuits of two-input one-output analog switches, wherein R, G, B signals and R ', G', B'signals are alternately switched at the timing indicated by a CLY signal (2) described later. The signals are output to the RGB rotation circuit 4 as R / R ′ · G / G ′ · B / B ′ signals. As shown in FIG. 2, when the CLY signal (2) is at the H level, the R ', G', and B'signals are output, and when it is at the L level, the R, G, and B signals are output. It is designed to output.

As shown in FIG. 2, the RGB rotation circuit 4 is composed of three-input one-output analog switches 41, 42 and 43 and a flip-flop 44, and as shown in FIG. 1, R / R'.G. The order of the / G 'and B / B' signals is changed at the timing indicated by the D _x signal described later, and
It is adapted to be output to the X driver circuit 5 as D1, 2, and 3 signals.

The RGB rotation circuit 4 will be described in detail with reference to FIG. When D _x signal becomes active, the signal is flip-flop 44 holds, whenever the D _x signal becomes active, the analog switches 41, 42 and 43
Each of the contact points toggles in the order of a, b, and c. When the analog switches 41, 42 and 43 are a contacts,
R / R ', G / G', B / B 'signals are VID 1, 2, 3
In the same way, VID 3.1.
2 signals, and when it is the c contact, it becomes VID2.3.1 signal. By the RGB rotation circuit 4, the R, G, B signals corresponding to the R, G, B pixels arranged on the color liquid crystal panel 7 are applied.

The X driver circuit 5 and the Y driver circuit 6 are connected to the color liquid crystal panel 7. The X driver circuit 5 and the Y driver circuit 6 have an X shift register and a Y shift register. The color liquid crystal panel 7 is for the NTSC broadcasting system, and the R, G, and B pixels are in the vertical direction (X Direction) and the horizontal direction (Y direction) to form a mosaic structure. Since the X driver circuit 5, the Y driver circuit 6, and the color liquid crystal panel 7 are the same as the conventional circuit described with reference to FIG. 7, detailed description thereof will be omitted.

Now, as shown in FIG. 1, the input video signal is inputted not only to the video demodulating circuit 1 but also to the synchronizing signal generating circuit 8. The sync signal generation circuit 8 is a sync separation circuit, and the input video signal is converted from the input video signal to the H SYNK signal (
The horizontal synchronizing signal) and the V SYNK signal (vertical synchronizing signal) are separated and output to the reference pulse generating circuit 9.

The reference pulse generating circuit 9 includes an H-PLA 91,
A digital circuit including a V-PLA 92, a clock signal generation circuit 93, and a thinning-out controller 94.
XY driver circuit 5 based on the signal and V SYNK signal,
A reference pulse for operating the X / Y shift register 51, 61, etc. of No. 6 is generated.

More specifically, the H SYNK signal and the V SYNK signal are led to the clock signal generation circuit 93 via the H-PLA 91 and V-PLA 92. The clock signal generation circuit 93
While recognizing the current field and scan line based on the H SYNK signal and V SYNK signal, D _x signal, CLX1-4
Signal, D _Y signal, CLY signal, etc. are generated. On the other hand, the thinning-out controller 94 stores the thinning-out line data in advance, and generates the CLY (2) signal based on the signal derived from the clock signal generating circuit 93.

FIG. 3 is a timing chart of main signals in the embodiment circuit. There is no difference from the conventional circuit except for the CLY signal (2) signal, but the reference pulse generating circuit 9 will be described with reference to this figure. It should be noted that the uppermost row of FIG. 3 shows the numbers of horizontal lines of fields on the input video signal.

The D _x signal is a pulse that is substantially synchronized with the H SYNK signal (not shown), and is a signal obtained by deleting the pulse to be output on the thinning line. The signal is guided to the RGB rotation circuit 4. However, the X shift register 51
For the shift start input (see Fig. 7), H SYNK (not shown)
A pulse synchronized with the signal is introduced.

The CLY signal is a clock inverted at the timing indicated by the H SYNK signal, and is a signal delayed by 1H (H: horizontal scanning period) in the thinning line, and the signal is the Y shift register 61. Is led to the shift transfer clock input of. The CLX1 to 4 signals and the D _Y signal generated by the reference pulse generation circuit 90 are the same as the conventional ones, and thus the description thereof will be omitted.

On the other hand, the CLY (2) signal is basically CLY (2).
Although the signal is synchronized with the signal, the signal is changed in the thinning line. That is, the signal is forcibly changed between the fifth and sixth lines of the odd field and between the second and third lines of the even field, and the signal is inverted every time the field changes. I am letting you.

The characteristic operation of the embodiment circuit configured as described above will be described. In the sixth line of the odd field on the input video signal, like the conventional circuit,
Since CLY signal and D _x signal does not change, Y shift register 6 well into the sixth line is held in the state immediately before is not shifted, as a result, the lines are thinned out. This point is the same as the conventional circuit. However, the difference from the conventional circuit is that when the fifth to sixth lines of the odd field are advanced, the contact point of the RGB alternating circuit 3 changes with the change of the CLY (2) signal at this point, and the sixth line Is that the R ', G', and B'signals are rewritten to the fifth line on the color liquid crystal panel 7 via the sample holder 52. That is, for the fifth line and the sixth line of the odd field on the input video signal, the signal voltage is applied to the RGB pixels of the fifth line on the color liquid crystal panel 7 in an overlapping manner, but the former is While the R, G, and B signals have a positive polarity, the latter has a R ', G', and B'signals that have a negative polarity. Therefore, unlike the conventional circuit, a voltage of the same polarity is applied to each pixel of the color liquid crystal panel 7. It is no longer applied during the 2H period.

It should be noted that in FIG. 3, the VID 1 and 2 signals on the 5th and 6th lines on the input video signal appear to have the same polarity, but a color liquid crystal panel to which a voltage is applied is applied. There is no problem because the line on 7 is different. The above description applies to other thinning lines of odd fields and thinning lines of even fields.

Next, a modified example of the embodiment circuit will be described with reference to FIGS. FIG. 4 is RGB as in FIG.
FIG. 5 is a circuit diagram showing a peripheral circuit of the alternating circuit, and FIG. 5 is a timing chart of main signals of the liquid crystal drive panel as in FIG.

The circuit of this modification is different from the circuit of the above embodiment in that the RGB alternating circuit 3 is switched by the CLY (1) signal used in the conventional circuit instead of the CLY (2) signal. Then, the reference pulse generating circuit 9 newly generates an MK signal which becomes active in the thinning line instead of the CLY (2) signal, and R / R'.G / G'.B at the timing indicated by the MK signal. The point is that a mute circuit 10 for clamping the voltage of the / B 'signal to the common voltage is newly added. Here, the common voltage is the center voltage between the positive electrode and the negative electrode, and is specifically 1/2 V _CC .

That is, since the RGB alternating circuit 3 is switched at the timing indicated by the CLY (1) signal, it is output from the RGB alternating circuit 3 on the fifth and sixth lines of the odd field on the input video signal. The signals become R, G, B signals, but when the sixth line, which is a thinning line, operates the mute circuit 10, the voltage applied to the RGB pixels on the fifth line on the color liquid crystal panel 7 is substantially the same. It becomes zero. Since the same applies to the other thinning lines, it is possible to obtain the same merit as that of the embodiment circuit.

The liquid crystal panel drive circuit according to the present invention is not limited to the above embodiment, but can be applied to any type of liquid crystal panel.

[0044]

As described above, in the liquid crystal panel drive circuit according to the first and second aspects of the present invention, the RG on the color liquid crystal panel is used in the thinning line on the input video signal and the line immediately before the thinning line.
Since the same polarity voltage is not applied to the B pixel for 2H, unlike the conventional circuit, even if a still image is continuously displayed for a long time, the pixel on the color liquid crystal panel may deteriorate. Moreover, since there is no afterimage and the image quality is good, it is possible to improve the performance of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing peripheral circuits of an RGB alternating circuit as well.

FIG. 3 is a timing chart of main signals in the circuit of the embodiment.

FIG. 4 is a diagram corresponding to FIG. 2 for explaining a modified example of the embodiment circuit.

FIG. 5 is a diagram corresponding to FIG.

FIG. 6 is a block diagram of a conventional liquid crystal panel drive circuit.

FIG. 7 is a circuit diagram of a peripheral circuit of the same color liquid crystal panel.

FIG. 8 is a diagram corresponding to FIG.

[Explanation of symbols]

 1 ... Video demodulation circuit 2 ... Inversion circuit 3 ... RGB alternating circuit 4 ... RGB rotation circuit 5, 6 ... X, Y driver circuit 7 ... Color liquid crystal panel 8 ... Synchronization signal generation circuit 9 ... Reference pulse generation circuit

Claims (2)

[Claims] 1. An image is displayed on a color liquid crystal panel for the NTSC broadcast system by regularly thinning out the nth line of the field while the input video signal is of the PAL broadcast system, and the liquid crystal panel for the color is concerned. A liquid crystal panel display circuit for inverting the polarity of the voltage applied to the pixel for each field and line, and a sync signal generation circuit for separating horizontal and vertical sync signals from the input video signal and outputting the signals, An X / Y driver circuit having an X / Y shift register connected to a color liquid crystal panel, and a circuit for generating a pulse signal for operating the X / Y shift register or the like based on a horizontal / vertical synchronization signal, when the input video signal is a n-th line of the field, whereas it stops the X shift register start pulse and D _X signal, The Y shift register transfer clock to be introduced into the Y shift register is delayed by one horizontal scanning period to be a CLY signal, and in addition to the signal, the input video signal advances from the (n-1) line to the nth line of the field. Occasionally, the CLY signal is inverted before and after this, and an inverted signal is generated each time the field changes.
(2) A reference pulse generating circuit for outputting as a signal, a video demodulating circuit for demodulating an input video signal to generate an R, G, B signal, and R '.
The inverting circuit that generates the G '/ B' signal and the R / G / B signal and the R '/ G' / B 'signal are alternately switched at the timing indicated by the CLY (2) signal, and the switched signal is R / R '
In order to provide signals corresponding to RGB alternating circuits that output G / G '/ B / B' signals and RGB pixels arranged differently for each line on the color liquid crystal panel, R / R '.
The order of the G / G 'and B / B' signals is changed at the timing indicated by the D _X signal, and the changed signals are output as VID 1, 2 and 3 signals to the RGB pixels of the color liquid crystal panel via the X driver circuit. And an RGB rotation circuit for controlling the liquid crystal panel. 2. An image is displayed on a color liquid crystal panel for the NTSC broadcasting system by regularly thinning out the nth line of the field while the input video signal is of the PAL broadcasting system, and the liquid crystal panel for the color is concerned. A liquid crystal panel display circuit for inverting the polarity of the voltage applied to the pixel for each field and line, and a sync signal generation circuit for separating horizontal and vertical sync signals from the input video signal and outputting the signals, An X / Y driver circuit having an X / Y shift register connected to a color liquid crystal panel, and a circuit for generating a pulse signal for operating the X / Y shift register or the like based on a horizontal / vertical synchronization signal, when the input video signal is a n-th line of the field, whereas it stops the X shift register start pulse and D _X signal, The Y shift register transfer clock introduced into the Y shift register is delayed by one horizontal scanning period and used as a CLY signal. Separately from this, an MK signal that becomes active when the input video signal is the nth line of the field is generated. On the other hand, each time the field changes, a reference pulse generation circuit that generates a signal in which the CLY signal is inverted and outputs it as a CLY (2) signal, and video demodulation that demodulates the input video signal to generate the R, G, B signals The circuit and the polarity of R, G, B signals are reversed and R ', G',
Inversion circuit for generating B'signal, R / G / B signal and R '
・ The G'and B'signals are alternately switched at the timing indicated by the CLY (1) signal, and the switched signals are R / R '/ G /
RGB alternating circuit that outputs as G '/ B / B' signals,
A mute circuit that forcibly clamps the voltage of the R / R ', G / G', B / B 'signals to the common voltage at the timing indicated by the MK signal, and the R, G, and B RGB signals arranged differently for each line on the color liquid crystal panel. To give the signal corresponding to the pixel,
The order of the R / R ', G / G', and B / B 'signals is changed at the timing indicated by the D _X signal, and the changed signals are VID1
A liquid crystal panel drive circuit comprising: an RGB rotation circuit for outputting to each of the RGB pixels of the color liquid crystal panel as a few signals via the X driver circuit.