JPH05121413A - Electrolytic plating for bump electrode for integrated circuit device - Google Patents

Abstract

PURPOSE:To easily eliminate the irregularity of height of the projecting metal for bump electrode, which is subject to electrolytic plating growth, in an integrated circuit in which the chips buried in a wafer has not been separated yet. CONSTITUTION:A distribution film 15 of high conductive metal is provided in a grid pattern within a mutual scribe zone SZ of chip area in a wafer 10, and after each chip area of the wafer is covered with a protective film 16, the window is opened at the position to provide a bump electrode 20 projectingly. Then a metallic and thin base film 17 is adhered on the wafer surface in a manner to connect the film 15 and the distribution film 14 in the window of film 16, and a projecting metal 18 is grown on the connected position to the film 14 through an electrolytic plating while using the film 17 as a plating electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrolytic plating method for bump electrodes, which are protruding electrodes protruding from a chip for external connection of an integrated circuit device.

[0002]

2. Description of the Related Art In order to save the labor and space required for mounting an integrated circuit device in various electronic devices, it is advantageous to mount it as a chip rather than once package it. Solder for mounting this chip,
So-called flip chips, which have bump electrodes made of gold, copper or the like, are widely used.

This flip chip bump electrode needs to be projected at a height of several tens to 100 .mu.m, and it is extremely uneconomical if the metal for it is deposited on the entire surface of the chip and the unnecessary portion is removed by etching. And it takes a lot of work,
Conventionally, it is usual to selectively grow only bumps of a bump electrode for a bump electrode on an integrated circuit device, which is not yet isolated into a chip formed in a wafer, by electrolytic plating only at a necessary portion. As is well known, a conventional electrolytic plating method for bump metal for bump electrodes will be briefly described below with reference to FIG.

FIG. 3 is an enlarged cross-sectional view of the peripheral portion of the wafer 10. The junction separation layer 12 is a strong p-type on the surface of the portion of the n-type epitaxial layer 11 which is usually the peripheral portion of each chip in which an integrated circuit is formed. Are diffused, and bump electrodes 20 are projected on the thick field oxide film 13 attached to the surface thereof. Epitaxial layer 11 on field oxide 13
An aluminum wiring film 14 connected to an integrated circuit formed in a portion (not shown) is provided, and the bump electrode 20 should be connected in a window opened in a protective film 16 such as silicon nitride that covers the wiring film 14. The end of the wiring film 14 is exposed. Next, a lower base film 17a made of a very thin metal such as titanium used as a plating electrode film during electrolytic plating is deposited on the entire surface of the wafer 10 and connected to the wiring film 14 inside each window of the protective film 16. Then, the upper base film 17b made of a thin metal such as palladium or copper is formed on the upper side of the window in a desired pattern for the bump electrode 20 having a small diameter of several tens of μm or a small angle.

Then, a photoresist film 30 is spin-coated on the entire surface of the wafer 10 for electrolytic plating, and a plating window exposing only the upper base film 17b is opened by a photo process. Electrolytic plating of the protruding metal 18 is performed by using the photoresist film 30 as a plating mask and the lower base film 17a as a plating electrode film, and a metal such as solder, gold, or copper for that is placed in the window of the photoresist film 30. The exposed upper underlayer film 17b is selectively grown to a height of several tens of μm. At this time, in order to connect the lower base film 17a to the plating power source, the tip of the metal needle 31 passes through the photoresist film 30 and the upper and lower base films 17 at the peripheral portion of the wafer 10 are passed.
Connected to.

After this electrolytic plating, first, a photoresist film
After removing 30, the titanium of the lower base film 17a is completely removed by dissolution by chemical etching using dilute hydrofluoric acid or the like except the lower part of the upper base film 17b. The individual bump electrode 20 is formed by disconnecting the physical connection. After that, the wafer 10 is cut along the scribe line SL to isolate each chip 40.

[0007]

In the conventional electrolytic plating method for the bump electrode 20, the bump metal 18 for the bump electrode 20 is used as described above.
By using the photoresist film 30 as a mask for plating only selectively at desired portions in the wafer 10, and by using the lower base film 17a as a plating electrode film all over the entire surface of the wafer 10. Although it can be grown, there is a problem in that the growth height of the protruding metal 18 is difficult to be uniform in the plane of the wafer 10.

This is because the lower base film 17a also serves as a barrier metal for preventing mutual diffusion or atomic migration of the aluminum for the wiring film 14 on the lower side and the element for the protruding metal 18 on the upper side. Therefore, it is necessary to use a metal with a high specific resistance such as titanium or chrome.
Since it is necessary to reduce the thickness to about 0.5 μm, its surface resistance becomes considerably high. Therefore, the growth of the protruding metal 18 at the time of electrolytic plating is fast in the peripheral portion of the wafer 10 connected to the plating power source via the needle 31 described above. This is because there is an unavoidable tendency to slow down in the central part. This causes the protruding metal in the wafer 10.
The in-plane variation of the height of 18 can be as much as ± 20% or more, which has been the main cause of defective electroplating.

As a measure against this, in addition to the lower base film 17a, an upper base film 17b made of palladium or copper and having a low specific resistance is used.
Can also be used as a plating electrode film, but since the film thickness is only about 0.5 μm, the effect of lowering the combined surface resistance is not very high, and both base films 17a and 17b are completely removed after completion of electrolytic plating. Becomes very difficult, and conversely, defects due to etching residues tend to occur.

Further, if the connection of the wafer 10 to the plating power source is made at the central portion, or if the connection is made at a plurality of points distributed in the plane, the in-plane variation of the height of the protruding metal 18 is determined by the number of connection points. However, this method is also not practical because it takes a lot of time and effort for the electrolytic plating work and its preparation, and the mass productivity is significantly reduced.

Under such circumstances, it is an object of the present invention to provide an electrolytic plating method capable of growing a bump metal for a bump electrode at a uniform height in a wafer surface by a simple and practical means. ..

[0012]

According to the present invention, the above object is to provide a distribution film made of a highly conductive metal in a grid pattern in a scribe zone between chip regions in a wafer, Each chip area in each chip is covered with a protective film, and a window is opened above the portion where the bump electrode of the wiring film in each chip is to be projected, and a thin metal base film is formed on the entire surface of the wafer as the distribution film and the distribution film. After depositing it so as to connect it to the wiring film in the window of the protective film of the chip, selectively grow the protruding metal on the connection part with the wiring film by using the base film as the plating electrode by the electrolytic plating method. It is achieved by

The same highly conductive metal as the wiring film for the integrated circuit is used for the above-mentioned highly conductive metal for the distribution film, and the wiring film is arranged for each chip area in the wafer, and at the same time the distribution film is scribed. It is advantageous to arrange the zones in a grid pattern. The wiring film is provided on the insulating film, while the power distribution film is provided directly on the surface of the semiconductor exposed in the scribe zone, and the chip of the wafer after the electrolytic plating of the protruding metal is completed. It is advantageous to facilitate the scribing operation by removing it by the chemical etching method as in the case of the base film before isolation into the underlayer. Further, when the underlying film is a composite film composed of upper and lower two layers as in the conventional case, the protruding metal is electrolytically plated on the upper underlying film while the lower underlying film is connected to the distribution film. It may be grown selectively on the connection point with the film.

[0014]

In the present invention, attention is paid to the fact that the scribe zones between the respective chip areas in the wafer are widely distributed in the plane in a lattice pattern. By providing a distribution film made of a conductive metal in a grid pattern and connecting a base film for the plating electrode film to this, it is virtually possible to connect the plating electrode film to the plating power source at many points distributed in the wafer surface. It succeeded in growing the bump metal in the same state as above and reducing the variation in the height of the bump electrode in the wafer surface to one-third or less than the conventional one. Note that the bump electrodes are usually arranged on the peripheral edge of each chip in close proximity to the scribe zone.In this case, the bump electrodes on the wafer surface should be directly connected to the plating power source. By growing the protruding metal in almost the same state as described above, it is possible to further reduce the variation in the height of the bump electrode within the wafer surface to about 1/5 of the conventional case.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged cross-sectional view of an essential part of a wafer showing a method of electrolytic plating bump electrodes for an integrated circuit device according to the present invention in each of its main steps, and FIG. 2 is a top view of the wafer showing a state in which a distribution film is provided. Since the same reference numerals are given to the portions corresponding to FIG. 3 described above, the description of the overlapping portions will be appropriately omitted.

In the step shown in FIG. 1A, the power distribution film 15 is arranged in the scribe zone SZ of the wafer 10. Since it is advantageous in the process to use aluminum for the wiring film 14 of the integrated circuit as the highly conductive metal for the power distribution film 15, the wiring film 14 is arranged in each chip area in the wafer 10 in this embodiment. In the step, the distribution film 15 made of the same aluminum is arranged in the scribe zone SZ on the semiconductor surface in the lattice pattern shown in FIG. 2 in the illustrated example. Chip 40 shown slightly enlarged in wafer 10 of FIG.
The scribe zones SZ are set in both the vertical and horizontal directions, and the power distribution film 15 is formed in a grid pattern corresponding to the scribe zones SZ with a width of, for example, 60 μm.

FIG. 1 (b) shows a step of disposing the protective film 16. As is customary, the protective film 16 is a silicon nitride film having a film thickness of 1 to 1.5 μm, which is formed on the entire surface of the wafer 10 by a CVD method or the like, and then a window 16a is provided with a bump electrode by a dry etching method. The end of the wiring film 14 is exposed by opening at a portion to be formed, and is removed in the scribe zone SZ with a width of, for example, 70 μm to expose the power distribution film 15.

FIG. 1C shows a step of depositing the underlayer film 17. Also in this embodiment, the base film 17 has a two-layer structure, and the lower base film 17 is
Titanium has a thickness of 0.2 μm and upper base film 17b has a thickness of 0.4 μm and is formed on the upper side of the protective film 16 by sputtering or the like. Inside the window 16a, the wiring film 14 and the scribe zone are formed. In the SZ, they are respectively connected to the power distribution film 15. The metal of the lower base film 17a, which is also used for the plating electrode film and the barrier metal, is titanium, chromium,
Molybdenum-tungsten-nickel chrome alloy is used. Upper base film that connects it with protruding metal with low resistance
In addition to palladium, copper is used as the metal of 17b. It is possible to proceed to the next electrolytic plating step with this composite film as it is, but in this embodiment, the upper base film 17b uses aqua regia solution to form a small pattern for bump electrodes as shown in FIG. 1 (d). Photo-etched on.

FIG. 1D shows an electroplating process of the bump metal 18. After patterning the upper base film 17b as described above, a photoresist film is formed on the entire surface of the wafer 10 as in the conventional case.
Spin coat 30 and perform photo process on upper base film
By opening a plating window that exposes only 17b, using this photoresist film as a plating mask, and using the lower base film 17a as a plating electrode film, a protruding metal such as solder, gold, or copper 18, In the example, gold is selectively grown on the upper base film 17a. In order to connect the lower base film 17a as a plating electrode film at the time of this electroplating to the plating power source, the peripheral part of the wafer 10 shown on the right side of the drawing is compared with the base film 17 having a two-layer structure in this example. The tip of the needle 31 is contacted through, for example, the soft photoresist film 30 at three points shown in FIG. The height of the protruding metal 18 is usually several tens to 100 μm, and in the case of gold as in this embodiment, it is 30 to 100 μm.
Grown to a height of 50 μm.

FIG. 1 (e) shows a completed state of the bump electrode 20. After completion of the above-described electrolytic plating, the photoresist film 30 is first removed in the same manner as in the conventional case, and then the titanium of the lower base film 17a is dissolved and removed by a chemical etching method using a dilute hydrofluoric acid solution with the upper base film 17b as a mask. As a result, the independent bump electrode 20 is formed as shown in the figure. Further, in this embodiment, in order to facilitate the scribing work, the aluminum distribution film 15 is removed from the scribe zone SZ by etching using a mixed solution of phosphoric acid and nitric acid to complete the illustrated wafer 10. After this, the wafer 10 is moved to the scribe line SL shown in the figure.
By cutting along the lines and isolating into chips 40, flip chips of the integrated circuit device each having bump electrodes 20 are obtained.

When the protruding metal 18 of the bump electrode 20 is grown by the electrolytic plating method as in the embodiment described above,
The surface resistance of the aluminum distribution film 15 is 5 to 10 Ω / □ when the film thickness is 0.5 to 1 μm, and the surface resistance of the titanium lower base film 17a of 0.2 μm for the plating electrode film is about 100 Ω / □. As compared with the resistance, the electroplating voltage applied to the needle 31 from the plating power source is remarkably low, which is 1/10 to 1/20, so that as shown in FIG. It is transmitted over the entire surface, and further, Fig. 1 (d)
As can be seen from the distribution film 15, a very short lower base film 17a
Is transmitted to the place where the protruding metal 18 on the peripheral portion of the chip region is to be grown, via the via with almost the same voltage value. Therefore, according to the method of the present invention, all the protruding metals 18 in the wafer 10 can be grown at a substantially uniform plating voltage. The results of applying the method of the present invention to the trial production of a mass-produced flip chip show that the bump electrode 20 has a high height. It has been proved that the variation in the wafer surface is reduced to less than one-third of the conventional value, and to about one-fifth when the electrolytic plating conditions are good.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various modes. The materials, numerical values, structures, conditions, etc. described in the examples are merely examples or exemplifications, and it is possible to carry out the method of the present invention in an appropriately selected manner within the scope thereof in actual cases or as necessary. is there.

[0023]

As described above, in the method of the present invention, a distribution film made of a highly conductive metal is provided in the scribe zone between the chip regions of the wafer in a grid pattern, and each chip region in the wafer is protected by a protective film. A window is opened at the place where the bump electrode should be covered and a metal underlayer film is deposited on the entire surface of the wafer so as to connect to the wiring film in the window of the distribution film and the protective film. As a plating electrode, a protruding metal is selectively grown on the connection point with the wiring film by electrolytic plating, so that the electrolytic plating voltage applied to the peripheral edge of the wafer from the plating power supply has a surface resistance of 10 ~ It is transmitted over the entire surface of the wafer with almost no voltage drop through a distribution film that is significantly lower than 1/20, and when the plating electrode film is connected to the plating power supply at many points, the protruding metal is evenly distributed. Grow to any height It is possible to reduce the variation in the height of the bump electrode within the wafer to one third to one fifth of the conventional one.

Since the power distribution film can be formed by using the same metal as the wiring film for the integrated circuit and in the same step, the method of the present invention can be easily and easily performed without adding any new step to the conventional method. it can. INDUSTRIAL APPLICABILITY The present invention is particularly advantageous when applied to mass production of highly integrated small-sized flip chips having many external connection points, and can exert a remarkable effect of improving the manufacturing yield and reducing the damage at the time of mounting.

[Brief description of drawings]

FIG. 1 shows an embodiment of a method for electroplating bump electrodes according to the present invention in a state of each main step, wherein FIG. 1 (a) is a distribution film arranging step, and FIG. 1 (b) is a protective film forming step. The figure (c) is an enlarged cross-sectional view of the essential part of the wafer, showing the step of depositing the base film, the figure (d) is the electroplating step, and the figure (e) is the completed state of the bump electrode.

FIG. 2 is a top view of a wafer illustrating an arrangement state of a power distribution film.

FIG. 3 is an enlarged sectional view of an essential part of a wafer showing a conventional electrolytic plating method for bump electrodes.

[Explanation of symbols]

 10 Wafer 14 Wiring film for integrated circuit 15 Distribution film 16 Protective film 17 Underlayer film 17a Lower underlayer film as plating electrode film 17b Upper underlayer film 18 Protruding metal 20 Bump electrode 40 Chip of integrated circuit device SZ scribe zone SL scribe line

Claims (3)

[Claims] 1. A method for growing a bump metal for a bump electrode on an integrated circuit device before isolation into a chip formed in a wafer by electrolytic plating, comprising: A place where a distribution film made of a highly conductive metal is provided in a grid pattern in the scribe zone between each other, the area for each chip in the wafer is covered with a protective film, and the bump electrode of the wiring film in each chip is to be projected. A window is opened on the top surface of the wafer, and a thin base film made of metal is applied to the entire surface of the wafer so as to be connected to the distribution film and the wiring film in the window of the protective film of each chip.
An electrolytic plating method for bump electrodes for an integrated circuit device, characterized in that a bump metal is selectively grown by electrolytic plating on a connection portion of the chip with a wiring film using the base film as a plating electrode. 2. An electrolytic plating method for bump electrodes for an integrated circuit device according to claim 1, wherein the power distribution film is formed of the same metal as the wiring film and at the same time. 3. The electrolytic plating of bump electrodes for an integrated circuit device according to claim 1, wherein the distribution film is removed before the isolation of the wafer into chips after electrolytic plating of the protruding metal. Method.