JPH05113834A - Digital signal processing system - Google Patents
Digital signal processing systemInfo
- Publication number
- JPH05113834A JPH05113834A JP3275875A JP27587591A JPH05113834A JP H05113834 A JPH05113834 A JP H05113834A JP 3275875 A JP3275875 A JP 3275875A JP 27587591 A JP27587591 A JP 27587591A JP H05113834 A JPH05113834 A JP H05113834A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency
- signal processing
- digital signal
- processing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000001514 detection method Methods 0.000 claims abstract description 4
- 239000002699 waste material Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Power Sources (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は入力信号をディジタル的
に処理して出力信号を得るディジタル信号処理システム
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing system for digitally processing an input signal to obtain an output signal.
【０００２】[0002]
【従来の技術】信号処理システムでは、システムに課せ
られる負荷，即ち信号の処理量の大きさは、常に一定し
ているのではなく，時々刻々変化しているのが普通であ
る。従来は、信号処理をディジタル回路で実現する場合
には、信号処理量の大きさの時間的変化に対して、その
最大値を見積もり，これを処理できる様に設計する。即
ち、最大負荷に合わせてディジタル信号処理回路の動作
クロックの速度が決められていた。2. Description of the Related Art In a signal processing system, the load imposed on the system, that is, the amount of signal processing is not always constant, but is usually changing every moment. Conventionally, when the signal processing is realized by a digital circuit, the maximum value is estimated with respect to the time change of the magnitude of the signal processing amount, and it is designed so that it can be processed. That is, the speed of the operation clock of the digital signal processing circuit is determined according to the maximum load.
【０００３】[0003]
【発明が解決しようとする課題】ところが、ＣＭＯＳ等
の半導体素子で構成されるディジタル回路では、その回
路規模を同じとすれば、動作速度が高速な回路ほど単位
時間における動作回数が大きくなるので其の消費電力が
大きい。従来のディジタル信号処理システムでは、負荷
が軽くて其の処理量がシステムの最大能力を大きく下回
る場合で、実際にはもっと低速のクロックにより信号処
理回路を動作させることが可能である場合でも、高速の
クロックのままで動作させていた。従って従来のディジ
タル信号処理システムは電力を無駄に消費していたこと
になる。本発明の目的は、信号処理量の大きさが時間的
に変化する場合に消費電力が無駄にならない様なディジ
タル信号処理システムを実現することにある。However, in a digital circuit composed of semiconductor elements such as CMOS, if the circuit scale is the same, the higher the operation speed, the larger the number of operations per unit time. Power consumption is large. In a conventional digital signal processing system, when the load is light and the amount of processing is much lower than the maximum capacity of the system, even if it is possible to operate the signal processing circuit by a clock with a slower speed, I was operating with the clock. Therefore, the conventional digital signal processing system wastes power. An object of the present invention is to realize a digital signal processing system in which power consumption is not wasted when the amount of signal processing changes with time.
【０００４】[0004]
【課題を解決するための手段】この目的を達成するため
の本発明の基本構成を図１の原理図に示す。同図中、１
はディジタル信号処理システム10の信号処理量を検出す
る処理量検出手段であり、２は前記の処理量検出手段1
の検出信号により駆動されて同システム10の動作用のク
ロックを発生し其の速度を制御するクロック速度制御手
段である。The basic configuration of the present invention for achieving this object is shown in the principle diagram of FIG. 1 in the figure
Is a processing amount detecting means for detecting the signal processing amount of the digital signal processing system 10, and 2 is the processing amount detecting means 1 described above.
Is a clock speed control means that is driven by the detection signal to generate a clock for the operation of the system 10 and controls the speed thereof.
【０００５】[0005]
【作用】本発明では、処理量検出手段1 がディジタル信
号処理システム10の信号の処理量を検出して、クロック
速度制御手段2 を駆動する。そしてシステム10の信号処
理量が少ない時は、クロック速度制御手段2が発生クロ
ックの周波数を低くするように制御し、処理量が多い時
は、発生クロックの周波数を高くするように制御する。
即ち、システムの信号処理量に応じて動作クロックの速
度を変化することが可能となるので、システムは常に最
適の消費電力量に制御されることになる。従ってシステ
ムの消費電力は無駄に消費されない。In the present invention, the processing amount detecting means 1 detects the processing amount of the signal of the digital signal processing system 10 and drives the clock speed controlling means 2. Then, when the signal processing amount of the system 10 is small, the clock speed control means 2 controls so as to lower the frequency of the generated clock, and when the processing amount is large, controls so as to increase the frequency of the generated clock.
That is, the speed of the operation clock can be changed according to the signal processing amount of the system, so that the system is always controlled to the optimum power consumption amount. Therefore, the power consumption of the system is not wasted.
【０００６】[0006]
【実施例】図２に本発明の第１の実施例のディジタル信
号処理システムの構成を示す。本実施例の信号処理シス
テム10は、その内部にディジタル信号処理プロセッサ11
の他に, 入力データを一時蓄積しておくバッファ12を具
えており、該バッファ11内に蓄積されるデータ量がシス
テムの負荷の大きさを表す。処理量検出手段1 のデータ
量検出部は、バッファ11内の入力データの量を検出し
て、クロック速度制御手段2を構成する制御電圧発生器2
1を駆動し電圧制御発振器22の発振周波数を制御する制
御電圧Vcを発生する。バッファ11内のデータ量が多い時
は、電圧制御発振器22の発振周波数が高くなるように,
データ量が少ない時は、発振周波数が低くなるように制
御電圧Vcを発生する。電圧制御発振器22は、制御電圧発
生器21から此の制御電圧Vcを受けて所定の周波数で発振
し、其の発振信号をディジタル信号処理システム10に動
作用のクロックとして供給する。FIG. 2 shows the configuration of a digital signal processing system according to the first embodiment of the present invention. The signal processing system 10 of this embodiment includes a digital signal processor 11 inside.
In addition to the above, a buffer 12 for temporarily storing input data is provided, and the amount of data stored in the buffer 11 indicates the magnitude of the load on the system. The data amount detecting section of the processing amount detecting means 1 detects the amount of input data in the buffer 11 to control voltage generator 2 which constitutes clock speed controlling means 2.
A control voltage Vc that drives 1 to control the oscillation frequency of the voltage controlled oscillator 22 is generated. When the amount of data in the buffer 11 is large, the oscillation frequency of the voltage controlled oscillator 22 should be high.
When the amount of data is small, the control voltage Vc is generated so that the oscillation frequency becomes low. The voltage controlled oscillator 22 receives the control voltage Vc from the control voltage generator 21, oscillates at a predetermined frequency, and supplies the oscillation signal to the digital signal processing system 10 as a clock for operation.
【０００７】図３に本発明の第２の実施例のディジタル
信号処理システムの構成を示す。本実施例は図２の第１
の実施例の変形であり、以下に異なる部分のみを説明す
る。本実施例では、クロック速度制御手段2が、固定周
波数の信号を発振する発振器211 と其の出力を所定の周
波数比に分周する分周器212 と其の分周比を定める分周
比制御器213 とから成り、システム10の負荷の大きさに
より其の動作クロックを可変とするために、本実施例で
は、固定周波数の発振器211 からの信号を分周器212 で
分周した出力をシステム10に動作クロックとして供給す
る分周器212の分周比を,分周比制御器213 にて可変とし
ている。すなわち、クロック速度制御手段2 の分周比制
御器213 が、分周器212の分周比を, バッファ11内のデ
ータ量が多い時には分周器212 が供給するクロックの周
波数が高くなるように,データ量が少ない時はクロック
周波数が低くなるように制御する。分周比制御器213で
此の様に定められた分周比により、分周器212 が分周を
行い其の出力をディジタル信号処理システム10に対して
動作クロックとして供給する。FIG. 3 shows the configuration of a digital signal processing system according to the second embodiment of the present invention. This embodiment is the first of FIG.
This is a modification of the embodiment described above, and only different parts will be described below. In the present embodiment, the clock speed control means 2 is an oscillator 211 that oscillates a signal of a fixed frequency, a frequency divider 212 that divides its output to a predetermined frequency ratio, and frequency division ratio control that determines the frequency division ratio. In order to make the operating clock variable depending on the load of the system 10, in the present embodiment, the output from the signal from the fixed frequency oscillator 211 is divided by the frequency divider 212. The frequency division ratio of the frequency divider 212 supplied to 10 as the operation clock is made variable by the frequency division ratio controller 213. That is, the frequency division ratio controller 213 of the clock speed control means 2 adjusts the frequency division ratio of the frequency divider 212 so that the frequency of the clock supplied by the frequency divider 212 becomes high when the data amount in the buffer 11 is large. When the data amount is small, the clock frequency is controlled to be low. The frequency divider 212 performs frequency division according to the frequency division ratio thus determined by the frequency division ratio controller 213 and supplies its output to the digital signal processing system 10 as an operating clock.
【０００８】なお、これら２つの実施例は、システムの
動作用のクロックの速度を連続的あるいは離散的に可変
としているが、これらを組み合わせる事で，より広い範
囲に亘ってクロック速度の円滑な制御が可能となること
は言うまでもない。In these two embodiments, the clock speed for operating the system is made variable continuously or discretely, but by combining these, smooth control of the clock speed over a wider range is possible. Needless to say, it becomes possible.
【０００９】[0009]
【発明の効果】以上説明した如く、本発明によれば、デ
ィジタル信号処理システムの動作用のクロックを，同シ
ステムに課せられる負荷の量に応じて変化できるので、
システムの消費電力の無駄を省く効果が得られる。As described above, according to the present invention, the clock for operating the digital signal processing system can be changed according to the amount of load imposed on the system.
The effect of eliminating waste of system power consumption can be obtained.
【図１】 本発明のディジタル信号処理システムの基本
構成を示す原理図FIG. 1 is a principle diagram showing a basic configuration of a digital signal processing system of the present invention.
【図２】 本発明の第１の実施例の構成を示すブロック
図FIG. 2 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.
【図３】 本発明の第２の実施例の構成を示すブロック
図FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.
１は処理量検出手段、２はクロック速度制御手段、21は
制御電圧発生器、22は電圧制御発振器、211 は固定周波
数の発振器、212 は分周器、213 は分周比制御器であ
る。Reference numeral 1 is a processing amount detecting means, 2 is a clock speed controlling means, 21 is a control voltage generator, 22 is a voltage controlled oscillator, 211 is a fixed frequency oscillator, 212 is a frequency divider, and 213 is a frequency division ratio controller.
Claims (2)
信号を得るディジタル信号処理システムにおいて、該デ
ィジタル信号処理システム(10)の処理量を検出する手段
(1)と該処理量検出手段の検出信号により駆動されて,同
システム(10)を動作させるため発生するクロックの速度
を制御するクロック速度制御手段(2)とを具え、システ
ムの信号処理量が少ない時は、クロック速度制御手段
(2)が発生クロックの周波数を低くするように制御し、
処理量が多い時は、発生クロックの周波数を高くするよ
うに制御することを特徴とするディジタル信号処理シス
テム。1. A digital signal processing system for digitally processing an input signal to obtain an output signal, said means for detecting a processing amount of said digital signal processing system (10).
(1) and clock speed control means (2) for controlling the speed of the clock generated for operating the system (10) driven by the detection signal of the processing amount detection means, and the signal processing amount of the system When there is little, clock speed control means
Control (2) to lower the frequency of the generated clock,
A digital signal processing system characterized by controlling the frequency of a generated clock to be high when there is a large amount of processing.
ック速度制御手段(2)が、固定周波数の信号を発振する
発振器(211)と其の出力を所定の周波数比に分周する分
周器(212)と其の分周比を定める分周比制御器(213)から
成り、該分周比制御器(213)が該分周器(212)の分周比
を, 処理量が多い時は出力のクロックの周波数が高くな
るように,処理量が少ない時はクロック周波数が低くな
るように制御することを特徴とした請求項１記載のディ
ジタル信号処理システム。2. A clock speed control means (2) of the digital signal processing system comprises an oscillator (211) which oscillates a signal of a fixed frequency and a frequency divider (212) which divides its output to a predetermined frequency ratio. And a frequency division ratio controller (213) that determines the frequency division ratio, the frequency division ratio controller (213) outputs the frequency division ratio of the frequency divider (212) when the processing amount is large. 2. The digital signal processing system according to claim 1, wherein the clock frequency is controlled so that the clock frequency becomes high and the clock frequency becomes low when the processing amount is small.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3275875A JPH05113834A (en) | 1991-10-24 | 1991-10-24 | Digital signal processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3275875A JPH05113834A (en) | 1991-10-24 | 1991-10-24 | Digital signal processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05113834A true JPH05113834A (en) | 1993-05-07 |
Family
ID=17561657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3275875A Withdrawn JPH05113834A (en) | 1991-10-24 | 1991-10-24 | Digital signal processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05113834A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6240524B1 (en) | 1997-06-06 | 2001-05-29 | Nec Corporation | Semiconductor integrated circuit |
| JP2005278194A (en) * | 2004-03-25 | 2005-10-06 | Sony Corp | Image-decoding instrument, method therefor, and program |
| JP2007233881A (en) * | 2006-03-03 | 2007-09-13 | Fujitsu Ltd | Operational speed control program, operational speed control device, operational speed control method |
| JP2012059206A (en) * | 2010-09-13 | 2012-03-22 | Toshiba Corp | Semiconductor integrated circuit, interconnect, and control program |
-
1991
- 1991-10-24 JP JP3275875A patent/JPH05113834A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6240524B1 (en) | 1997-06-06 | 2001-05-29 | Nec Corporation | Semiconductor integrated circuit |
| JP2005278194A (en) * | 2004-03-25 | 2005-10-06 | Sony Corp | Image-decoding instrument, method therefor, and program |
| TWI395486B (en) * | 2004-03-25 | 2013-05-01 | Sony Corp | Image decoder and image decoding method and program |
| JP2007233881A (en) * | 2006-03-03 | 2007-09-13 | Fujitsu Ltd | Operational speed control program, operational speed control device, operational speed control method |
| JP4732195B2 (en) * | 2006-03-03 | 2011-07-27 | 富士通株式会社 | Control program, control device, and control method |
| JP2012059206A (en) * | 2010-09-13 | 2012-03-22 | Toshiba Corp | Semiconductor integrated circuit, interconnect, and control program |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990107 |