JPH08190535A - Component processor and power distributed multiprocessor - Google Patents

Abstract

PURPOSE: To provide a power distributed multiprocessor which can reduce the useless power consumption. CONSTITUTION: A processor 101 controls a phase locked loop circuit 102 and increases the clock frequency when the processing load is large. When the processing load is small, the processor 101 also controls the circuit 102 to reduce the clock frequency. The circuit 102 produces a signal of the N-fold or 1/N frequency synchronously with the signal given from a clock signal line 204. The frequency is increased or reduced by the processor 101 through a PLL control line 205. In a multiprocessor of such a constitution, each component processor decides its operating speed in response to each load. In a steady state, each component processor is always carrying out its processing and has no non-operation state. Therefore, since the useless processing carried out from shift between the operation and non-operation states and the absence of a non- operation state are eliminated, the useless power is never consumed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of power consumption, load distribution, and power distribution in a multiprocessor that uses a plurality of element processors and cooperates with each other to perform certain information processing. .

[0002]

2. Description of the Related Art FIG. 16 shows an element processor that constitutes a conventional multiprocessor. The processor 101 synchronizes with the clock signal input from the clock signal line 203, processes the data obtained from the input data line 201, and outputs the data to the output data line 202. In such a conventional element processor, the load of the element processor, or
The operating frequency did not change due to the load of the element processor connected to the processor.

[0003]

When a certain information processing is processed by a multiprocessor, its load must be equally assigned to each element processor. However, in reality, the load weight varies among the element processors. Therefore, in such a state where the load is not evenly distributed to each element processor, there is a non-operating state in which the element processor is not performing processing, and the element processor consumes useless power during that period. Further, when the element processors whose loads are not distributed repeat the operating state and the non-operating state in a short cycle, the processing overhead required for switching the operation and unnecessary power consumption increase.

An object of the present invention is to provide an element processor capable of reducing wasteful power consumption.

Another object of the present invention is to provide a multiprocessor capable of reducing wasteful power consumption even if the load weights of the respective element processors vary.

[0006]

SUMMARY OF THE INVENTION An element processor of the present invention includes a processor for processing data obtained from an input data line and outputting the data to an output data line, and a processor for synchronizing with a clock signal input from a clock signal line. From P
A phase-locked loop circuit that generates a clock signal whose frequency changes according to an LL control line, and the processor operates using the output clock signal of the phase-locked loop circuit as a clock signal.

Further, the element processor of the present invention generates a processor for processing data obtained from an input data line and outputting it to an output data line, and a clock signal whose oscillation frequency changes by a VCO control line from the processor. An external frequency control type oscillator may be provided, and the processor may operate by using an output clock signal of the external frequency control type oscillator as a clock signal.

Further, the element processor of the present invention generates a third voltage from the first power source by the processor which processes the data obtained from the input data line and outputs it to the output data line, and the DDC control line from the processor. DC-D
A C converter may be provided, and the processor may be operated by using a potential difference between a third voltage generated by the DC-DC converter and an output voltage of the second power supply as a power supply voltage.

Further, the element processor of the present invention processes the data obtained from the input data line and outputs it to the first output data line, and stores the data obtained from the first output data line, and the second processor. FI to output to the output data line
An output of the phase-locked loop circuit includes an FO buffer and a phase-locked loop circuit that generates a clock signal whose frequency is changed by a PLL control line from the processor in synchronization with the clock signal input from the clock signal line. The processor operates by using a clock signal as a clock signal, the amount of data stored in the FIFO buffer is input to the processor through a FIFO observation line, and the processor controls the phase locked loop circuit through the PLL control line. It can also be a feature.

Further, the element processor of the present invention stores the data obtained from the first output data line and the processor which processes the data obtained from the input data line and outputs the data obtained from the first output data line to the second processor. FI to output to the output data line
An FO buffer and an external frequency control type oscillator that generates a clock signal whose oscillation frequency changes by a VCO control line from the processor are provided, and the processor operates using an output clock signal of the external frequency control type oscillator as a clock signal. However, the amount of data stored in the FIFO buffer may be input to the processor through a FIFO observation line, and the processor may control the external frequency control type oscillator through the VCO control line.

The element processor of the present invention processes the data obtained from the input data line and outputs it to the first output data line, and stores the data obtained from the first output data line and stores the data obtained from the second output data line. FI to output to the output data line
DC-DC for generating a third voltage from a first power supply by a FO buffer and a DDC control line from the processor
A converter, the processor operates using the potential difference between the third voltage generated by the DC-DC converter and the output voltage of the second power supply as the power supply voltage, and the amount of data stored in the FIFO buffer is observed by the FIFO. Input to the processor by a line, and the processor inputs the DDC
It is also possible to control the DC-DC converter through a control line.

Also, the element processor of the present invention processes the data obtained from the second input data line and the FIFO buffer which stores the data obtained from the first input data line and outputs the data to the second input data line. And a phase locked loop circuit for generating a clock signal whose frequency changes in accordance with a PLL control line from the processor and which is synchronized with a clock signal input from a clock signal line. The processor operates by using the output clock signal of the phase locked loop circuit as a clock signal, the amount of data stored in the FIFO buffer is input to the processor through a FIFO observation line, and the processor receives the phase locked loop through the PLL control line. It can also be characterized as controlling a circuit.

Further, the element processor of the present invention processes the data obtained from the first input data line and the FIFO buffer which stores the data obtained from the first input data line and outputs the data to the second input data line. And an external frequency control type oscillator for generating a clock signal whose oscillation frequency changes according to a VCO control line from the processor, and clocks the output clock signal of the external frequency control type oscillator. The processor operates as a signal, the amount of data stored in the FIFO buffer is input to the processor through a FIFO observation line, and the processor controls the external frequency control type oscillator through the VCO control line. You can also

Also, the element processor of the present invention processes the data obtained from the first input data line by storing the data obtained from the first input data line and outputting it to the second input data line. And a DC-DC for generating a third voltage from the first power supply by the DDC control line from the processor
A converter, the processor operates using the potential difference between the third voltage generated by the DC-DC converter and the output voltage of the second power supply as the power supply voltage, and the amount of data stored in the FIFO buffer is observed by the FIFO. Input to the processor by a line, and the processor inputs the DDC
It is also possible to control the DC-DC converter through a control line.

In the multiprocessor of the present invention, a plurality of the element processors described above are prepared, the output data lines and the input data lines are connected to each other, and the plurality of element processors cooperate with each other. It is characterized in that processing is performed and the operating speed of each element processor is controlled according to the load of each element processor.

[0016]

The operation speed of each element processor constituting the multiprocessor is determined by the load of the element processor, the load of the element processor which receives the output data of the element processor, or the element processor which generates data input to the element processor. The operating speed of each element processor is independently determined by changing the load depending on the load. As a method of changing the operating speed of each element processor,
There is a method of changing the clock signal input to the element processor by a synchronous phase loop circuit or an external frequency control type oscillator, or a method of changing the power supply voltage of the processor by a DC-DC converter. The load of each element processor may be determined by the program of the element processor, by the state of the FIFO buffer attached to the input, or by the state of the FIFO buffer attached to the output.

When the operating speed of each element processor is determined as described above, in the steady state, each element processor is always in an operating state of processing information. That is, the process of switching between the operating state and the non-operating state does not occur. Further, each element processor operates at a speed necessary for the processor, so that wasteful power consumption can be reduced.

[0018]

Embodiments of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a first embodiment of the element processor of the present invention.

The element processor of this embodiment processes the data obtained from the input data line 201 and outputs the data from the output data line 2.
02 and the clock signal line 2
A phase-locked loop circuit 1 that generates a clock signal whose frequency changes in synchronization with a clock signal input from the processor 101 by a PLL control line 205 from the processor 101.
02, and the processor 101 includes the clock signal line 2
It operates using the output clock signal of the phase locked loop circuit 102 sent via 03 as a clock signal.

FIG. 10 shows the configuration of the phase locked loop circuit 102. The phase-locked loop circuit 102 includes a counter 1
09, 110, a phase comparator 106, a charge pump circuit 107, a low pass filter circuit 108, and an external frequency control type oscillator 103.

FIG. 11 shows the configuration of the phase comparator 106. This phase comparator is composed of a plurality of NAND circuits connected as shown.

FIG. 12 shows the configuration of the charge pump circuit 107. This charge pump circuit is composed of CMOS.

FIG. 13 shows the configuration of the low-pass filter circuit 108. This low-pass filter circuit is composed of a resistor and a capacitor.

FIG. 14 shows an external frequency control type oscillator 103.
Shows the configuration of. This oscillator is composed of FETs connected as shown.

A plurality of the above element processors are prepared, and the output data line 202 and the input data line 20 are mutually provided.
Connect 1. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. When the processing load is large, the processor 101 controls the phase locked loop circuit 102 to increase the clock frequency.
When the processing load is small, the phase-locked loop circuit 102 is similarly controlled to reduce the clock frequency. The phase locked loop circuit 102 is synchronized with the signal given from the clock signal line 204, and generates a clock signal having a frequency N times or 1 / N. Increase or decrease the frequency by PL
This is performed by the processor 101 through the L control line 205.

As a method for the processor 101 to determine the amount of load, there are the following methods, for example. That is, each element processor outputs a pilot data after outputting a processing result after processing a certain processing unit assigned to the element processor. When an element processor inputs at least two pilot data while executing a certain processing unit, the element processor determines that the load is heavy. On the other hand, when one pilot data is not input during execution of a certain processing unit, the element processor determines that the load is light.

In the conventional multiprocessor, there is no definitive method for distributing the load, and a load imbalance occurs in each element processor. That is, one element processor is heavily loaded and another element processor is lightly loaded. In such a case, the overall processing speed is often determined by the element processor with the heaviest load, which also causes a decrease in output throughput. In addition, in such an unbalanced load state, each element processor has a processing state, that is, an operating state, and a non-processing state, that is, a non-operating state, and the mutual state is moved. Wasteful processing required to do so and wasteful power consumption for it. Furthermore, in the non-operating state, wasteful power was consumed.

In the power distribution multiprocessor of the present invention,
As described above, each element processor determines its operating speed according to the load of each element processor. In the steady state, each element processor is always in a processing state, and there is no non-operation state. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

That is, it is difficult for the conventional multiprocessor to distribute the load, but in the power distribution multiprocessor of this embodiment, a certain degree of load imbalance is compensated by changing the operating speed of the processor, and the load is distributed. The heavy-duty element processor can autonomously supply the electric power required for its processing. That is, from the viewpoint of power, complete power distribution is performed.

FIG. 2 is a block diagram showing a second embodiment of the element processor of the present invention.

This element processor has an input data line 20.
1 which processes the data obtained from 1 and outputs it to the output data line 202, and V from the processor 201.
An external frequency control type oscillator 103 that generates a clock signal whose oscillation frequency changes by a CO control line 206 is provided, and the processor 101 operates using the output clock signal of the external frequency control type oscillator 103 as a clock signal.

The external frequency control type oscillator 103 is shown in FIG.
The oscillator shown in is used.

A plurality of the above element processors are prepared, and their output data lines and input data lines are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Controls the external frequency controlled oscillator 103 to increase the clock frequency when the processing load is large. Also,
When the processing load is small, the external frequency control type oscillator 103 is similarly controlled to decrease the clock frequency. Increasing or decreasing the frequency is performed by the processor 10 through the VCO control line 206.
1 does.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 3 is a block diagram showing a third embodiment of the element processor of the present invention.

This element processor has an input data line 20.
1 from the processor 101 for processing the data obtained from 1 and outputting to the output data line 202;
A DC-DC converter 104 that generates a third voltage from a first power source by a DC control line 207 is provided.
Is supplied to the processor 101 via the power supply line 208. The processor 101 operates using the potential difference between the third voltage generated by the DC-DC converter 104 and the output voltage of the second power supply as the power supply voltage.

FIG. 15 shows the configuration of the DC-DC converter 104. This converter is composed of a FET and a differential amplifier.

A plurality of the element processors described above are prepared, and their output data lines and input data lines are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Is a DC-DC converter 1 when the processing load is large.
04 to increase the power supply voltage applied to the processor 101. Similarly, when the processing load is small, DC
Control the DC converter 104 and reduce the power supply voltage. The processor 101 increases and decreases the power supply voltage through the DDC control line 207. That is, this utilizes the fact that the processing capability of the semiconductor integrated circuit that constitutes the processor increases when the power supply voltage increases and decreases when the power supply voltage decreases.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 4 is a block diagram showing a fourth embodiment of the element processor of the present invention.

This element processor has an input data line 20.
The first output data line 20 for processing the data obtained from
9 and the FIFO buffer 105 that stores the data obtained from the first output data line 209 and outputs the data to the second output data line 202, and the clock signal input from the clock signal line 204. , A phase locked loop circuit 102 that generates a clock signal whose frequency changes by a PLL control line 205 from the processor 101, and uses the output clock signal of the phase locked loop circuit 102 as a clock signal.
Operates and inputs the amount of data stored in the FIFO buffer 105 to the processor 101 through the FIFO observation line 210, and the processor 101 controls the phase locked loop circuit 102 through the PLL control line 205.

The phase-locked loop circuit 102 uses the circuit shown in FIG.

A plurality of the above element processors are prepared and the respective second output data lines 202 and input data lines 201 are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing.
When the processing load is large, the processor 101 controls the phase locked loop circuit 102 to increase the clock frequency. When the processing load is small, the phase-locked loop circuit 102 is similarly controlled to reduce the clock frequency. The phase locked loop circuit 102 includes the clock signal line 20.
A clock signal having a frequency N times or 1 / N is generated in synchronization with the signal supplied from the circuit 4. The processor 101 increases and decreases the frequency through the PLL control line 205.

As a method for the processor 101 to determine the amount of load, the amount of data stored in the FIFO buffer 105 is used. The data amount can be known to the processor 101 through the FIFO observation line 210. That is, F
When data is stored in the IFO buffer 105, the load of the element processor of the next stage connected to the second output data line 202 is heavy, and therefore the processor 101 determines that the load is light. On the other hand, when no data is stored in the FIFO buffer 105, the second output data line 20
The processor 101 determines that the load is heavy because it indicates that the element processor of the next stage connected to 2 has a margin and a light load.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 5 is a block diagram showing a fifth embodiment of the element processor of the present invention.

This element processor has an input data line 20.
The first output data line 20 for processing the data obtained from
9 and the FIFO buffer 105 for storing the data obtained from the first output data line 209 and outputting it to the second output data line 202, and the VCO control line 206 from the processor 101 And an external frequency control type oscillator 103 for generating a changing clock signal.
The processor 101 operates by using the output clock signal of No. 3 as a clock signal, and the processor 1 operates the data amount accumulated in the FIFO buffer 105 by the FIFO observation line 210.
01 and the processor 101 inputs the VCO control line 206
The external frequency control type oscillator 103 is controlled through.

The external frequency control type oscillator 103 is shown in FIG.
The oscillator shown in 4 is used.

A plurality of the above element processors are prepared, and their output data lines and input data lines are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Controls the external frequency controlled oscillator 103 to increase the clock frequency when the processing load is large. Also,
When the processing load is small, the external frequency control type oscillator 103 is similarly controlled to decrease the clock frequency. Increasing or decreasing the frequency is performed by the processor 10 through the VCO control line 206.
1 does.

In the power distribution multiprocessor of the present invention,
As described above, each element processor determines its operating speed according to the load of each element processor. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, since there is no useless processing for transitioning between the operating state and the non-operating state, wasteful power for that purpose, and no non-operating state,
It does not consume unnecessary power for that.

FIG. 6 is a block diagram showing a sixth embodiment of the element processor of the present invention.

This element processor has an input data line 20.
The first output data line 20 for processing the data obtained from
9 to the first output data line 209, the FIFO buffer 105 that stores the data obtained from the first output data line 209 and outputs it to the second output data line 202, and the DDC control line 207 from the processor 101. DC-DC converter 104 for generating a third voltage from
This third voltage is supplied to the processor 101 via the power supply line 208. DC-DC converter 104
The processor 101 operates using the potential difference between the third voltage generated by the processor and the output voltage of the second power supply as the power supply voltage,
The amount of data stored in the O buffer 105 is input to the processor 101 via the FIFO observation line 210, and the processor 101 controls the DC-DC converter 104 via the DDC control line 207.

The DC-DC converter 104 shown in FIG. 15 is used.

A plurality of the above element processors are prepared, and their output data lines and input data lines are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Is a DC-DC converter 1 when the processing load is large.
04 to increase the power supply voltage applied to the processor 101. Similarly, when the processing load is small, DC
Control the DC converter 104 and reduce the power supply voltage. The processor 101 increases and decreases the power supply voltage through the DDC control line 207. That is, this utilizes the fact that the processing capability of the semiconductor integrated circuit that constitutes the processor increases when the power supply voltage increases and decreases when the power supply voltage decreases.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 7 is a block diagram showing a seventh embodiment of the element processor of the present invention.

This element processor stores the data obtained from the first input data line 201, processes the data obtained from the second input data line 211, and the FIFO buffer 105 which outputs the data to the second input data line 211. A phase locked loop circuit 102 for generating a clock signal whose frequency is changed by a PLL control line 205 from the processor 101 in synchronism with a processor 101 which outputs to the output data line 202 and a clock signal which is input from a clock signal line 204. The processor 101 operates by using the output clock signal from the clock signal line 203 of the phase locked loop circuit 102 as a clock signal, and the amount of data stored in the FIFO buffer 105 is stored in the FIFO observation line 21.
0 to the processor 101, and the processor 101
Through the PLL control line 205.
Control 2

The phase-locked loop circuit 102 uses the circuit shown in FIG.

A plurality of the above element processors are prepared, and the respective second output data lines 202 and input data lines 201 are connected to each other. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing.
When the processing load is large, the processor 101 controls the phase locked loop circuit 102 to increase the clock frequency. When the processing load is small, the phase-locked loop circuit 102 is similarly controlled to reduce the clock frequency. The phase locked loop circuit 102 includes the clock signal line 20.
A clock signal having a frequency N times or 1 / N is generated in synchronization with the signal supplied from the circuit 4. The processor 101 increases and decreases the frequency through the PLL control line 205.

As a method for the processor 101 to determine the amount of load, the amount of data stored in the FIFO buffer 105 is used. The data amount can be known to the processor 101 through the FIFO observation line 210. That is, F
When data is stored in the IFO buffer 105, it indicates that the load of the preceding element processor connected to the first input data line 201 is light, and thus the processor 101 determines that the load is heavy. On the other hand, when no data is stored in the FIFO buffer 105, the first input data line 20
The processor 101 determines that the load is light because the load of the element processor in the preceding stage connected to 1 is heavy.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 8 is a block diagram showing an eighth embodiment of the element processor of the present invention.

This element processor stores the data obtained from the first input data line 201, processes the data obtained from the first input data line 211 and the FIFO buffer 105 which outputs to the second input data line 211. The external frequency control type oscillator 10 is provided with the processor 101 for outputting to the output data line 202 and the external frequency control type oscillator 103 for generating a clock signal whose oscillation frequency changes by the VCO control line 206 from the processor 101.
3, the processor 101 operates using the output clock signal from the clock signal line 203 of No. 3 as a clock signal,
The amount of data stored in the buffer 105 is input to the processor 101 through the FIFO observation line 210, and the processor 101 controls the external frequency control type oscillator 103 through the VCO control line 206.

The external frequency control type oscillator 103 is shown in FIG.
The oscillator shown in 4 is used.

A plurality of the element processors described above are prepared, and their output data lines and input data lines are mutually connected. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Controls the external frequency controlled oscillator 103 to increase the clock frequency when the processing load is large. Also,
When the processing load is small, the external frequency control type oscillator 103 is similarly controlled to decrease the clock frequency. Increasing or decreasing the frequency is performed by the processor 10 through the VCO control line 206.
1 does.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

FIG. 9 is a block diagram showing a ninth embodiment of the element processor of the present invention.

This element processor processes the data obtained from the first input data line 211 and the FIFO buffer 105 which stores the data obtained from the first input data line 201 and outputs it to the second input data line 211. Output to the output data line 202, and the DC-DC converter 104 that generates the third voltage from the first power supply by the DDC control line 207 from the processor 101.
And the third voltage is supplied to the processor 101 via the power supply line 208. DC-DC converter 10
The processor 101 operates using the potential difference between the third voltage generated by No. 4 and the output voltage of the second power supply as the power supply voltage, and the FI
FIFO the amount of data stored in the FO buffer 105
Input to the processor 101 through the observation line 210, and the processor 101 controls the DC-DC converter 104 through the DDC control line 207.

The DC-DC converter 104 is shown in FIG.
Use the one shown in.

A plurality of the above element processors are prepared, and their output data lines and input data lines are mutually connected. A plurality of element processors cooperate with each other to form a multiprocessor that performs certain information processing. Processor 101
Is a DC-DC converter 1 when the processing load is large.
04 to increase the power supply voltage applied to the processor 101. Similarly, when the processing load is small, DC
Control the DC converter 104 and reduce the power supply voltage. The processor 101 increases and decreases the power supply voltage through the DDC control line 207.

In the power distribution multiprocessor of this embodiment, each element processor determines its operating speed according to the load of each element processor as described above. In the steady state, each element processor is always in the processing state, and the non-operation state does not exist. Therefore, useless processing for transitioning between the operating state and the non-operating state, useless power for that purpose, and further, since there is no non-operating state, useless power for that purpose is not consumed.

That is, although it was difficult for the conventional multiprocessor to distribute the load, the power distribution multiprocessor of this embodiment compensates for a certain amount of load imbalance by changing the operating speed of the processor, and The heavy-duty element processor can autonomously supply the electric power required for its processing. That is, from the viewpoint of power, complete power distribution is performed.

[0074]

As described above, when a certain information processing is processed by a multiprocessor, its load must be equally assigned to each element processor. However, in reality, the load weight varies among the element processors. Therefore, in such a state where the load is not evenly distributed to each element processor, there is a non-operating state in which the element processor is not performing processing, and the element processor consumes useless power during that period. Further, when the element processors whose loads are not distributed repeat the operating state and the non-operating state in a short cycle, the processing overhead required for switching the operation and unnecessary power consumption increase.

In the power distribution multiprocessor of the present invention,
The operating speed of each element processor that constitutes the multiprocessor is determined by the load of that element processor, the load of the element processor that receives the output data of that element processor, or the load of the element processor that generates the data that is input to that element processor. By changing it, the operating speed of each element processor is independently determined.

As a method for changing the operating speed of each element processor, a clock signal input to the element processor is changed by a synchronous phase loop circuit or an external frequency control type oscillator, or the power supply voltage of the processor is DC-.
There is a method of changing with a DC converter. The load of each element processor is determined by the program of the element processor, or the FIF attached to the input.
Method depending on O buffer status or F attached to output
There is a method depending on the state of the IFO buffer.

When the operating speed of each element processor is determined as described above, in the steady state, each element processor is always in an operating state of processing information. That is, the process of switching between the operating state and the non-operating state does not occur. Further, each element processor operates at a speed necessary for the processor, so that wasteful power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of an element processor according to a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a block configuration of an element processor according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a block configuration of an element processor according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a block configuration of an element processor according to a fourth exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a block configuration of an element processor according to a fifth exemplary embodiment of the present invention.

FIG. 6 is a diagram showing a block configuration of an element processor according to a sixth exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a block configuration of an element processor according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a block configuration of an element processor according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a block configuration of an element processor according to a ninth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing a specific example of a phase-locked loop circuit.

FIG. 11 is a diagram showing a specific example of a phase comparator.

FIG. 12 is a diagram showing a specific example of a charge pump circuit.

FIG. 13 is a diagram showing a specific example of a low-pass filter circuit.

FIG. 14 is a diagram showing a specific example of an external frequency control type oscillator.

FIG. 15 is a diagram showing a specific example of a DC-DC converter.

FIG. 16 is a diagram showing a block configuration of a conventional element processor.

[Explanation of symbols]

 101 Processor 102 Phase Locked Loop Circuit 103 External Frequency Controlled Oscillator 104 DC-DC Converter 105 FIFO Buffer 106 Phase Comparator 107 Charge Pump Circuit 108 Low Pass Filter Circuit 109, 110 Counter 201, 211 Input Data Line 202, 209 Output Data Line 203 , 204 Clock signal line 205 PLL control line 206 VCO control line 207 DDC control line 208 Third power supply line 210 FIFO observation line

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[Procedure amendment]

[Submission date] December 6, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 8

[Correction method] Change

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[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 9

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

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Further, the element processor of the present invention processes the data obtained from the second input data line and the FIFO buffer which stores the data obtained from the first input data line and outputs the data to the second input data line. And an external frequency control type oscillator for generating a clock signal whose oscillation frequency changes according to a VCO control line from the processor, and clocks the output clock signal of the external frequency control type oscillator. The processor operates as a signal, the amount of data stored in the FIFO buffer is input to the processor through a FIFO observation line, and the processor controls the external frequency control type oscillator through the VCO control line. You can also

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[Correction target item name] 0014

[Correction method] Change

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The element processor of the present invention processes the data obtained from the second input data line and the FIFO buffer which stores the data obtained from the first input data line and outputs the data to the second input data line. And a DC-DC for generating a third voltage from the first power supply by the DDC control line from the processor
A converter, the processor operates using the potential difference between the third voltage generated by the DC-DC converter and the output voltage of the second power supply as the power supply voltage, and the amount of data stored in the FIFO buffer is observed by the FIFO. Input to the processor by a line, and the processor inputs the DDC
It is also possible to control the DC-DC converter through a control line.

Claims (10)

[Claims] 1. A processor for processing data obtained from an input data line and outputting the data to an output data line; and a processor synchronized with a clock signal inputted from a clock signal line,
A phase locked loop circuit that generates a clock signal whose frequency changes according to a PLL control line from the processor, wherein the processor operates using the output clock signal of the phase locked loop circuit as a clock signal. Processor. 2. A processor for processing data obtained from an input data line and outputting it to an output data line, and an external frequency control type oscillator for generating a clock signal whose oscillation frequency changes by a VCO control line from the processor. An element processor, comprising: the external frequency control oscillator, wherein the processor operates using an output clock signal of the external frequency control type oscillator as a clock signal. 3. A processor for processing data obtained from an input data line and outputting it to an output data line, and a DC-DC converter for generating a third voltage from a first power source by a DDC control line from the processor. And a third voltage and a second voltage generated by the DC-DC converter.
The element processor is characterized in that the processor is operated by using a potential difference from an output voltage of the power source as the power source voltage. 4. A processor for processing data obtained from an input data line and outputting it to a first output data line, and a FIFO for storing data obtained from the first output data line and outputting it to a second output data line. Synchronized with the buffer and the clock signal input from the clock signal line,
A phase locked loop circuit that generates a clock signal whose frequency changes according to a PLL control line from the processor, wherein the processor operates using the output clock signal of the phase locked loop circuit as a clock signal, and is stored in the FIFO buffer. FIF the amount of data
An element processor which inputs to the processor through an O observation line, and the processor controls the phase locked loop circuit through the PLL control line. 5. A processor for processing data obtained from an input data line and outputting it to a first output data line, and a FIFO for storing data obtained from the first output data line and outputting it to a second output data line. A buffer and an external frequency control type oscillator that generates a clock signal whose oscillation frequency changes by a VCO control line from the processor are provided, and the processor operates using an output clock signal of the external frequency control type oscillator as a clock signal. , The amount of data stored in the FIFO buffer is
An element processor which inputs to the processor through an O observation line, and the processor controls the external frequency controlled oscillator through the VCO control line. 6. A processor for processing data obtained from an input data line and outputting it to a first output data line, and a FIFO for storing data obtained from the first output data line and outputting it to a second output data line. A buffer and a DC-DC converter that generates a third voltage from a first power source by a DDC control line from the processor, and a third voltage and a second voltage generated by the DC-DC converter.
The processor operates using the potential difference from the output voltage of the power supply of the power supply as the power supply voltage, and the data amount stored in the FIFO buffer is
An element processor which inputs to the processor through an O observation line, and the processor controls the DC-DC converter through the DDC control line. 7. A FIFO buffer for storing data obtained from the first input data line and outputting it to the second input data line, and processing the data obtained from the second input data line and outputting it to the output data line. Synchronize with the clock signal input from the processor and clock signal line,
A phase locked loop circuit that generates a clock signal whose frequency changes according to a PLL control line from the processor, wherein the processor operates using the output clock signal of the phase locked loop circuit as a clock signal, and is stored in the FIFO buffer. FIF the amount of data
An element processor which inputs to the processor through an O observation line, and the processor controls the phase locked loop circuit through the PLL control line. 8. A FIFO buffer for storing the data obtained from the first input data line and outputting it to the second input data line, and a data buffer obtained by processing the data obtained from the first input data line and outputting it to the output data line. A processor and an external frequency control type oscillator that generates a clock signal whose oscillation frequency changes according to a VCO control line from the processor, and the processor operates by using an output clock signal of the external frequency control type oscillator as a clock signal. , The amount of data stored in the FIFO buffer is
An element processor which inputs to the processor through an O observation line, and the processor controls the external frequency controlled oscillator through the VCO control line. 9. A FIFO buffer for storing the data obtained from the first input data line and outputting it to the second input data line, and a data buffer obtained by processing the data obtained from the first input data line and outputting it to the output data line. A processor and a DC-DC converter that generates a third voltage from a first power source by a DDC control line from the processor, and a third voltage and a second voltage generated by the DC-DC converter.
The processor operates using the potential difference from the output voltage of the power supply of the power supply as the power supply voltage, and the data amount stored in the FIFO buffer is
An element processor which inputs to the processor through an O observation line, and the processor controls the DC-DC converter through the DDC control line. 10. A plurality of element processors according to any one of claims 1 to 9 are prepared, each output data line and input data line are mutually connected, and the plurality of element processors cooperate with each other. A power distribution multiprocessor characterized by performing certain information processing and controlling the operating speed of each element processor according to the load on each element processor.