JPH0286207A - Basic clock generating circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the entire microprocessor system by varying a clock to a microprocessor unit programmably. CONSTITUTION:In a basic clock generating circuit 10, an oscillator 7 outputs a basic clock, and a frequency divider 6 frequency-divides an output clock from the oscillator 7 and outputs a clock A. Moreover, the circuit 10 is provided with a phase comparator 2, a low pass filter 3, a voltage controlled oscillator 4, and a frequency divider 5 frequency-divides an MPU clock generated from the voltage controlled oscillator 4 and outputting variably properly an optional MPU clock in response to the application of the microprocessor system, which form a phase locked loop. Then a control circuit 1 controls the frequency divider 5 to vary the MPU clock programmably by executing a specific instruction for the MPU 8 in response to the application of the microprocessor system. Thus, the power consumption of the entire microprocessor system is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a basic clock generation circuit for a microprocessor system in which the instruction cycle time of the microprocessor is determined.

[Conventional technology]

In the conventional technology, the basic tarock generation circuit of a microprocessor system is a circuit 11 consisting of an oscillator or oscillator as shown in FIG. 2, and its frequency is fixed.
Almost the MAX value within the standard range of the microprocessor unit (MPU) 12 is used. The MPU 12 includes a display unit control circuit 13. Memory circuit 14. Input/output control circuit 155
The interrupt control circuit 16 and the microprocessor system are configured, but when the microprocessor system is in a standby state, even low-speed operation with a slow MPU clock can be used, but since the MPU clock does not change, the fast MPU It operates at high speed using the clock.

[Problem to be solved by the invention]

In the basic clock generation circuit of the conventional microprocessor system mentioned above, the frequency of the MPU clock is fixed and the frequency uses approximately the MAX value within the standard range, so that when the microprocessor system is in a standby state, etc. Even though it can be used at low speeds, it operates at high speeds because the MPU clock does not change. Therefore, even if it is possible to reduce power consumption by lowering the operating frequency, which is a characteristic of digital ICs, there is a drawback that the operating frequency is kept high and power consumption is wasted.

The purpose of the present invention is to eliminate such drawbacks and to provide timely MP
An object of the present invention is to provide a basic clock generation circuit that can smoothly vary the frequency of a U clock from a high frequency to a low frequency.

[Means for Solving the Problems] The present invention provides a basic clock generation circuit that generates a basic clock for a microprocessor system including a microprocessor unit. A first frequency divider that divides the frequency and outputs a first clock; a phase comparator that receives the first clock as one input; and a low-pass filter connected to the phase comparator.

A voltage controlled oscillator is connected to this low-pass filter and outputs the clock to the microprocessor unit.

a second frequency divider that divides the clock output from the voltage controlled oscillator and outputs a second clock that becomes the other input of the phase comparator;
The microprocessor unit has a control circuit that controls the frequency division ratio of the frequency divider, and is characterized in that the clock to the microprocessor unit is programmably varied by the microprocessor unit executing a specific instruction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the basic clock generation circuit of the present invention. This basic clock generation circuit IO is
An oscillator 7 that outputs a basic clock, a frequency divider 6 that divides the frequency of the output clock from this oscillator and outputs clock A, and a phase comparator 2 that forms a phase-locked loop. Low-pass filter 3. A voltage controlled oscillator 4, a frequency divider 5 that divides the MPU clock generated by the voltage controlled oscillator 4, and outputs an arbitrary MPU clock timely and variably according to the application of the microprocessor system; The control circuit 1 controls the frequency divider 5 in order to programmably vary the MPU clock by executing specific instructions in the MPU 8 accordingly.

Note that the microprocessor system is MP in this embodiment.
It is composed of U8, a timer control circuit 9, a display control circuit 13, a memory circuit 14, an input/output control circuit 15, and an interrupt control circuit 16.

Next, the operation of this embodiment will be explained.

When the microprocessor system is in a normal operating state, the frequency division ratio of the frequency divider 5 is set to 1 by the control circuit 1, and the MPU clock generated by the voltage controlled oscillator 4 is transferred to the frequency divider by the phase locked loop. 6 generated clock A
is synchronized with.

When the microprocessor system is in slow mode such as standby
When low-speed operation using the PU clock becomes possible, M
The PU 8 executes a specific command, controls the frequency division ratio of the frequency divider 5 by the control circuit 1, divides the MPU clock generated by the voltage controlled oscillator 4 by the frequency division ratio, and generates a low frequency clock B. form. This clock B is input to the phase comparator 2.

On the other hand, the phase comparator 2 receives a clock A obtained by dividing the basic clock from the oscillator 7 by the frequency divider 6. Phase comparator 2. A phase-locked loop composed of a low-pass filter 3 and a voltage-controlled oscillator 4 is connected to a clock B.
Synchronize with the basic cloth A. That is, this phase-locked loop compares the phases of clock A and clock B in phase comparator 2 and operates so as to eliminate the phase difference.

When the MPU clock generated by the voltage controlled oscillator 4 is synchronized and becomes the desired low frequency clock, the MPU 8 controls the control 'B circuit 1 to return the frequency division ratio of the frequency divider 5 to the original value, that is, to 1. Make it. In this way, the MPU clock generated by the voltage controlled oscillator 4 can be smoothly varied to a desired low frequency clock.

As described above, according to this embodiment, the MPU clock can be programmably varied depending on the application of the microprocessor system. By the way, if a fixed timer is required in the microprocessor system, the output clock A of the frequency divider 6 can be used as the basic clock for the timer control circuit 9 in the microprocessor system.

〔Effect of the invention〕

As explained above, in the present invention, when the microprocessor system becomes fully usable even in low-speed operation such as standby, the basic clock generation circuit of the microprocessor system changes the frequency of the MPU clock from a high frequency to a low frequency in a timely manner. By smoothly varying the frequency, it takes advantage of the fact that general microprocessor systems consume less power when the operating frequency is low.
It is possible to reduce the power consumption of the entire microprocessor system and operate it with optimal power consumption, making it possible to construct an economical microprocessor system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
1 is a block diagram of a microprocessor system using an oscillator as a basic clock generation circuit. FIG. 1... Control circuit 2... Phase comparator 3... Low pass filter 4... Voltage controlled oscillator 5, 6, 7, 11, 8, 12, 10・ ・ ・ ・Frequency divider・Oscillator・MPU・Basic clock generation circuit

Claims (1)

[Claims] (1) In a basic clock generation circuit that generates the basic clock of a microprocessor system including a microprocessor unit, there is an oscillator that outputs the basic clock, and the output clock from this oscillator is divided to output a first clock. a first frequency divider; a phase comparator having the first clock as one input; a low-pass filter connected to the phase comparator; and a microprocessor unit connected to the low-pass filter. a voltage controlled oscillator that outputs a clock; a second frequency divider that divides the clock output from the voltage controlled oscillator and outputs a second clock that is the other input of the phase comparator; and a microprocessor unit. controlled by the second
and a control circuit that controls the frequency division ratio of the frequency divider, and the clock to the microprocessor unit is programmably varied by the microprocessor unit executing a specific instruction. circuit