JP4732195B2 - Control program, control device, and control method - Google Patents

Description

  The present invention relates to an operation speed control program, an operation speed control device, and an operation speed control method for controlling the operation speed of an arithmetic circuit.

  In recent years, LSI (Large Scale Integrated circuit) chips generate a large amount of heat as power consumption increases, which hinders improvement in LSI performance. Therefore, in order to reduce power consumption, hardware having a function of reducing the operation speed by reducing the power supply voltage and the operation frequency during the operation of the chip has been put into practical use.

As a related art related to the present invention, in decoding a moving picture experts group (MPEG) stream, a QoS (Quality of Quality) is increased by dynamically increasing a power supply voltage and an operating frequency in accordance with the characteristics of the MPEG stream. Service) is maintained (for example, see Patent Document 1).
JP 2004-153553 A

  However, the above-described function for reducing power consumption has a scheduling problem as to which power supply voltage and operating frequency are changed during operation. In addition, there are cases where optimum scheduling is required if an application is specified, but there is no general-purpose scheduling method.

  In addition, in order to perform appropriate power supply voltage and operating frequency control in the above-described MPEG stream decoding, a designer having MPEG expertise needs to design a dedicated control method using MPEG parameters. .

  The present invention has been made to solve the above-described problems, and provides an operation speed control program, an operation speed control apparatus, and an operation speed control method capable of performing general-purpose operation speed control for an arithmetic circuit. For the purpose.

  In order to solve the above-described problems, the present invention provides a computer for controlling the operation speed of an arithmetic circuit which is at least one arithmetic circuit and has at least one buffer provided on at least one of its input / output sides. An operation speed control program to be executed, wherein a buffer status acquisition step for acquiring a buffer status affected by a processing status of the arithmetic circuit as a buffer status value; and a buffer status value acquired by the buffer status acquisition step. Based on this, the computer is caused to execute an operation speed parameter setting step for setting an operation speed parameter that is a parameter that affects the operation speed of the arithmetic circuit.

  In the operating speed control program according to the present invention, the operating speed parameter setting step compares a preset threshold value with the buffer status value, and when the buffer status value exceeds or falls below the threshold value. In this case, the operation speed parameter is switched.

  In the operating speed control program according to the present invention, the operating speed parameter setting step is characterized in that the threshold value is changed based on a possibility that an interrupt process is entered in the arithmetic circuit.

  In the operating speed control program according to the present invention, the operating speed parameter setting step calculates the operating speed parameter using the buffer state value and a predetermined function.

  In the operation speed control program according to the present invention, the buffer affected by the arithmetic circuit includes a buffer connected to the input of the arithmetic circuit, a buffer connected to the output of the arithmetic circuit, One of the buffers connected through the circuit is included.

  In the operation speed control program according to the present invention, the buffer state acquisition step calculates a new buffer state value based on buffer state values acquired from a plurality of buffers, and the operation speed parameter setting step includes the new operation state parameter setting step. The operation speed parameter is set based on the buffer state value.

  In the operating speed control program according to the present invention, the operating speed parameter setting step sets operating speed parameters for a plurality of arithmetic circuits.

  In the operation speed control program according to the present invention, the buffer state value is an amount of data accumulated in the buffer.

  In the operating speed control program according to the present invention, the operating speed parameter includes a power supply voltage or an operating frequency of the arithmetic circuit.

  The present invention also relates to an operation speed control device that controls the operation speed of an operation circuit that includes at least one operation circuit that includes at least one buffer provided on at least one of its input and output sides. A buffer state acquisition unit for acquiring a buffer state affected by the processing state of the arithmetic circuit as a buffer state value; and an operation speed of the arithmetic circuit based on the buffer state value acquired by the buffer state acquisition unit. And an operation speed parameter setting unit for setting an operation speed parameter that is a parameter that affects the operation.

  In the operation speed control device according to the present invention, the operation speed parameter setting unit compares a preset threshold value with the buffer status value, and when the buffer status value exceeds or falls below the threshold value. In this case, the operation speed parameter is switched.

  In the operation speed control device according to the present invention, the operation speed parameter setting unit changes the threshold based on a possibility that an interrupt process is entered in the arithmetic circuit.

  In the operation speed control device according to the present invention, the operation speed parameter setting unit calculates the operation speed parameter using the buffer state value and a predetermined function.

  In the operation speed control device according to the present invention, the buffer affected by the arithmetic circuit may include a buffer connected to the input of the arithmetic circuit, a buffer connected to the output of the arithmetic circuit, One of the buffers connected through the circuit is included.

  In the operation speed control device according to the present invention, the buffer state acquisition unit calculates a new buffer state value based on buffer state values acquired from a plurality of buffers, and the operation speed parameter setting unit The operation speed parameter is set based on the buffer state value.

  In the operation speed control device according to the present invention, the operation speed parameter setting unit sets operation speed parameters for a plurality of arithmetic circuits.

  In the operation speed control device according to the present invention, the buffer state value is an amount of data accumulated in the buffer.

  In the operation speed control device according to the present invention, the operation speed parameter includes a power supply voltage or an operation frequency of the arithmetic circuit.

  The present invention is also an operating speed control method for controlling the operating speed of an arithmetic circuit which is at least one arithmetic circuit and has at least one buffer provided on at least one of its input / output sides. A buffer state acquisition step for acquiring a buffer state affected by the processing state of the arithmetic circuit as a buffer state value, and an operation speed of the arithmetic circuit based on the buffer state value acquired by the buffer state acquisition step. An operation speed parameter setting step for setting an operation speed parameter that is a parameter that affects the operation is executed.

  According to the present invention, it is possible to control the general-purpose operation speed for the arithmetic circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

  In the present embodiment, an example in which the operation speed control device is applied to an MPEG2 decoder will be described.

  First, the configuration of the MPEG2 decoder will be described.

  FIG. 1 is a block diagram showing an example of the configuration of an MPEG2 decoder according to the present embodiment. This MPEG2 decoder includes buffers 10a, 10b, 10c and 10d, a VLD (Variable Length Decoding) / IQ (Inverse Quantization) unit 11, an IDCT (Inverse Discrete Cosine Transform) unit 12, an MC (Motion Compensation) unit 13, and an operation speed control. The unit 20 is provided. The operation speed control unit 20 includes a buffer state acquisition unit 21 and an operation speed parameter setting unit 22.

  In the present embodiment, it is assumed that VLD / IQ unit 11, IDCT unit 12, and MC unit 13 operate at the same power supply voltage and the same operating frequency. In addition, the power supply voltage values that can be taken are two (VH, VL), and the possible operating frequency values are two (FH, FL). The relationship between VH, VL and FH, FL is VH> VL, FH> FL, respectively.

  The conditions of the bit stream input to the MPEG2 decoder are shown below.

-Bit rate = 5 Mbps
(This value depends on the input environment of the MPEG2 decoder application)
-Screen size = 720 x 480 pixels-4: 2: 0 format-Macroblock = 8 x 8 pixels

  The video signal output from the MPEG2 decoder is 30 frames / second. If the number of output frames falls below this value, frame dropping or the like occurs, and normal image display cannot be performed.

  First, the operation of MPEG2 decoding will be described.

  The MPEG2 bit stream input to the MPEG2 decoder is written to the buffer 10a in bit units. The VLD / IQ unit 11 performs variable length decoding and inverse quantization on the data read from the buffer 10a, and writes the result to the buffer 10b in units of pixels. The IDCT unit 12 performs inverse discrete cosine transform on the data read from the buffer 10b, and writes the result in the buffer 10c in units of macroblocks. The MC unit 13 performs motion compensation on the data read from the buffer 10c, and writes the result in the buffer 10d in units of frames. The data in the buffer 10d is output from the MPEG2 decoder as a video signal.

  Next, the operation of the operation speed control unit 20 will be described.

  FIG. 2 is a flowchart showing an example of the operation of the operation speed control unit according to the present embodiment. Here, the operation speed parameter setting unit 22 uses the power supply voltage (VH or VL) and the operation frequency (FH or FL) as the operation speed parameters that affect the operation speed, the VLD / IQ unit 11, and the IDCT unit. 12 is given to the MC unit 13. First, the buffer status acquisition unit 21 reads the data amount of each buffer as a buffer status value indicating the buffer status (S11). The buffer 10a stores the accumulated data amount NB (number of bits), the buffer 10b stores the accumulated data amount NP (number of pixels), the buffer 10c stores the accumulated data amount NM (number of macroblocks), and the buffer 10d accumulates. The data amount NF (the number of frames) being sent is notified to the buffer status acquisition unit 21.

  Next, the buffer status acquisition unit 21 calculates the total data amount NT accumulated in the MPEG2 decoder as a new buffer status value based on NB, NP, NM, and NF (S12).

  Regarding the relationship between NB, NP, NM, and NF, for example, the following conversion formula can be obtained according to the specifications of MPEG2.

1 frame = 720 × 480 × 1.5 / (8 × 8) = 8100 macroblock (4: 2: 0 format, so one frame is 1.5 (4 + 2) / 4 times the screen size (pixel )
1 macroblock = 8 × 8 = 64 pixels 1 pixel = 5 Mbps / (720 × 480 × 1.5 × 30) = 0.32 bits (5 Mbit per second on the input side, 30 per second on the output side) (Because it is a frame, one pixel on the output side corresponds to 0.32 bits on the input side.)

  A formula f (NF, NM, NP, NB) for calculating the total data amount NT expressed by the number of pixels from NB, NP, NM, NF is expressed by the following formula.

・ NT = f (NF, NM, NP, NB)
= (8100 × 64) × NF + 64 × NM + NP + (1 / 0.32) × NB

  Next, the operation speed parameter setting unit 22 adjusts the low threshold TL (S21). Here, the operation speed parameter setting unit 22 sets TL higher than normal when there is a possibility that interrupt processing other than MPEG2 decoding may occur in the MPEG2 decoder. For example, when the time occupied by interrupt processing in one second is predicted to be 1/30 at worst, TL is increased by one. This is because 1/30 seconds corresponds to the output time of one frame.

  Next, the operation speed parameter setting unit 22 determines whether NF is lower than TL (S22). When NF falls below TL (S22, Y), the operation speed parameter setting unit 22 changes the power supply voltage and the operation frequency to VH and FH, respectively (S23), and ends this flow. That is, when the final buffer data amount NF is small, the operation speed is increased in order to maintain normal image display.

  On the other hand, when NF does not fall below TL (S22, N), the operation speed parameter setting unit 22 determines whether NT exceeds TH (S24). When NT exceeds TH (S24, Y), the operation speed parameter setting unit 22 changes the power supply voltage and the operation frequency to VL and FL, respectively (S25), and ends this flow. That is, when NT representing the data amount of all buffers is large, the operation speed is lowered to reduce power consumption. On the other hand, if NT does not exceed TH (S24, N), this flow ends. Thereafter, this flow is repeatedly executed every predetermined time.

  In the present embodiment, a buffer state value (data amount) representing the state of the buffer is acquired, and operating speed parameters (power supply voltage and operating frequency) of the arithmetic circuit (VLD / IQ unit 11, IDCT unit 12, MC unit 13) are obtained. The operation speed control device (operation speed control unit 20) for setting the above is described.

  As described above, the operation speed control unit 20 switches the operation speed according to the data amount in the buffers 10a, 10b, 10c, and 10d, thereby increasing the power consumption due to the operation speed being too high and the operation speed being too low. Therefore, the functional circuit can be prevented from deteriorating, and the arithmetic circuit can operate at an appropriate operation speed. In addition, it is possible to realize appropriate control of the operation speed even without expertise related to the MPEG2 decoder.

  In the present embodiment, different buffer state values (NT, NF) are used for the determination to lower the operation speed and the determination to increase the operation speed. However, the same is used for both the determination to decrease the operation speed and the determination to increase the operation speed. May be used. In this embodiment, the operating speed is controlled by changing both the power supply voltage and the operating frequency. However, only one of the power supply voltage and the operating frequency may be changed. In the present embodiment, the operation speed control unit 20 switches the operation speed parameter based on the result of the comparison between the buffer state value and the threshold value, but uses a predetermined function for calculating the operation speed parameter from the buffer state value. Thus, the operation speed parameter may be calculated from the buffer state value.

  Moreover, although the operation speed control unit 20 in the present embodiment sets the same power supply voltage and the same operation frequency for all arithmetic circuits, different power supply voltages and operation frequencies are set for a plurality of arithmetic circuits. Different power supply voltages and operating frequencies may be determined using different buffer state values for a plurality of arithmetic circuits.

  Examples of other operation speed control devices will be described.

  FIG. 3 is a block diagram illustrating an example of the configuration of the arithmetic device according to the present embodiment. The arithmetic device includes a buffer 30, arithmetic circuits 31 and 32, and an operation speed control unit 40. The buffer 30 is subsequent to the arithmetic circuit 31 and is upstream of the arithmetic circuit 32. The configuration of the operation speed control unit 40 is the same as that of the operation speed control unit 20, but the contents of the process are different.

  The operation speed control unit 40 acquires the data amount N of the buffer 30 and sets a low threshold A and a high threshold B for N in advance. When N <A, the operation speed control unit 20 increases the operation speed of the arithmetic circuit 31 in the previous stage. When N> B, the operation speed control unit 20 reduces the operation speed of the arithmetic circuit 31 in the previous stage. FIG. 4 is a graph illustrating an example of a temporal change in the data amount in the buffer according to the present embodiment.

  As described above, the operation speed control unit 40 switches the operation speed according to the amount of data in the buffer 30, thereby increasing the power consumption due to the operation speed being too high and reducing the function due to the operation speed being too low. And the arithmetic circuit can operate at an appropriate operation speed. In addition, even if there is no specialized knowledge regarding the arithmetic circuits 31 and 32, it is possible to realize an appropriate operation speed control.

  When N <A, the operation speed control unit 40 may decrease the operation speed of the arithmetic circuit 32 at the subsequent stage. When N> B, the operation speed control unit 40 may increase the operation speed of the arithmetic circuit 32 at the subsequent stage.

  The operation speed control unit 40 controls the operation speed of the arithmetic circuit based on the state of the buffer used by the arithmetic circuit for direct input or the buffer used for the direct output by the arithmetic circuit. The operation speed of the arithmetic circuit may be controlled based on the state of a buffer connected to the output via another circuit.

  In addition, the operation speed control device according to the present embodiment can be easily applied to the information processing device, and can further improve the performance of the information processing device. Here, the information processing apparatus may include an apparatus including an arithmetic circuit that performs an operation using hardware and an apparatus including an arithmetic circuit that performs an operation using software.

  Furthermore, a program that causes a computer constituting the operation speed control apparatus to execute the above steps can be provided as an operation speed control program. By storing the above-described program in a computer-readable recording medium, the computer constituting the operation speed control device can be executed. Here, examples of the recording medium readable by the computer include an internal storage device such as a ROM and a RAM, a portable storage such as a CD-ROM, a flexible disk, a DVD disk, a magneto-optical disk, and an IC card. It includes a medium, a database holding a computer program, another computer and its database, and a transmission medium on a line.

  The buffer state acquisition step corresponds to the processes S11 and S12 in the embodiment. The operation speed parameter setting step corresponds to steps S21 to S25 in the embodiment.

(Supplementary Note 1) An operating speed control program for causing a computer to control the operating speed of at least one arithmetic circuit and having at least one buffer provided on at least one of its input / output sides. There,
A buffer status acquisition step for acquiring a buffer status affected by the processing status of the arithmetic circuit as a buffer status value;
An operation speed control for causing a computer to execute an operation speed parameter setting step for setting an operation speed parameter that is a parameter affecting the operation speed of the arithmetic circuit based on the buffer state value acquired by the buffer state acquisition step. program.
(Supplementary note 2) In the operation speed control program described in supplementary note 1,
The operation speed parameter setting step compares a preset threshold value with the buffer state value, and switches the operation speed parameter when the buffer state value exceeds or falls below the threshold value. An operating speed control program.
(Appendix 3) In the operation speed control program described in Appendix 2,
The operating speed control program characterized in that the operating speed parameter setting step changes the threshold based on the possibility of interrupt processing entering in the arithmetic circuit.
(Supplementary Note 4) In the operation speed control program described in Supplementary Note 1,
The operating speed parameter setting step calculates the operating speed parameter using the buffer state value and a predetermined function.
(Supplementary Note 5) In the operation speed control program according to any one of Supplementary Notes 1 to 4,
The buffer affected by the arithmetic circuit is a buffer connected to the input of the arithmetic circuit, a buffer connected to the output of the arithmetic circuit, or a buffer connected to the arithmetic circuit through another circuit. An operating speed control program comprising:
(Supplementary note 6) In the operation speed control program according to any one of supplementary notes 1 to 5,
The buffer status acquisition step calculates a new buffer status value based on buffer status values acquired from a plurality of buffers,
The operating speed parameter setting step sets an operating speed parameter based on the new buffer state value.
(Supplementary note 7) In the operation speed control program according to any one of supplementary notes 1 to 6,
The operating speed parameter setting step sets operating speed parameters for a plurality of arithmetic circuits.
(Supplementary note 8) In the operation speed control program according to any one of supplementary notes 1 to 7,
The operation speed control program, wherein the buffer status value is an amount of data accumulated in the buffer.
(Supplementary note 9) In the operation speed control program according to any one of supplementary notes 1 to 8,
The operating speed control program, wherein the operating speed parameter includes a power supply voltage or an operating frequency of the arithmetic circuit.
(Supplementary Note 10) An operation speed control device that controls the operation speed of an arithmetic circuit that is at least one arithmetic circuit and has at least one buffer provided on at least one of its input and output sides.
A buffer status acquisition unit that acquires a buffer status affected by the processing status of the arithmetic circuit as a buffer status value;
An operation speed control device comprising: an operation speed parameter setting unit configured to set an operation speed parameter that is a parameter affecting the operation speed of the arithmetic circuit based on the buffer state value acquired by the buffer state acquisition unit.
(Supplementary note 11) In the operation speed control device according to supplementary note 10,
The operating speed parameter setting unit compares a preset threshold value with the buffer status value, and switches the operating speed parameter when the buffer status value exceeds or falls below the threshold value. An operation speed control device.
(Supplementary note 12) In the operation speed control device according to supplementary note 11,
The operation speed control device is characterized in that the operation speed parameter setting unit changes the threshold value based on a possibility that an interrupt process is entered in the arithmetic circuit.
(Supplementary note 13) In the operation speed control device according to supplementary note 12,
The operation speed parameter setting unit calculates the operation speed parameter using the buffer state value and a predetermined function.
(Supplementary Note 14) In the operation speed control device according to any one of Supplementary Notes 10 to 13,
The buffer affected by the arithmetic circuit is a buffer connected to the input of the arithmetic circuit, a buffer connected to the output of the arithmetic circuit, or a buffer connected to the arithmetic circuit through another circuit. An operation speed control device comprising:
(Supplementary Note 15) In the operation speed control device according to any one of Supplementary Notes 10 to 14,
The buffer status acquisition unit calculates a new buffer status value based on buffer status values acquired from a plurality of buffers,
The operation speed parameter setting unit sets an operation speed parameter based on the new buffer state value.
(Supplementary Note 16) In the operation speed control device according to any one of Supplementary Notes 10 to 15,
The operating speed parameter setting unit sets operating speed parameters for a plurality of arithmetic circuits.
(Supplementary Note 17) In the operation speed control device according to any one of Supplementary Notes 10 to 16,
The operation speed control device, wherein the buffer status value is an amount of data accumulated in the buffer.
(Supplementary note 18) In the operation speed control device according to any one of supplementary note 10 to supplementary note 17,
The operation speed control device, wherein the operation speed parameter includes a power supply voltage or an operation frequency of the arithmetic circuit.
(Supplementary note 19) An operation speed control method for controlling the operation speed of an arithmetic circuit which is at least one arithmetic circuit and has at least one buffer provided on at least one of its input and output sides,
A buffer status acquisition step for acquiring a buffer status affected by the processing status of the arithmetic circuit as a buffer status value;
An operation speed control method for executing an operation speed parameter setting step for setting an operation speed parameter, which is a parameter affecting the operation speed of the arithmetic circuit, based on the buffer state value acquired by the buffer state acquisition step.
(Supplementary note 20) In the operation speed control method according to supplementary note 19,
The operation speed parameter setting step compares a preset threshold value with the buffer state value, and switches the operation speed parameter when the buffer state value exceeds or falls below the threshold value. An operation speed control method characterized by the above.

It is a block diagram which shows an example of a structure of the MPEG2 decoder which concerns on this Embodiment. It is a flowchart which shows an example of operation | movement of the operation speed control part which concerns on this Embodiment. It is a block diagram which shows an example of a structure of the arithmetic unit which concerns on this Embodiment. It is a graph which shows an example of a time change of the amount of data in a buffer concerning this embodiment.

Explanation of symbols

10a, 10b, 10c, 10d buffer, 11 VLD / IQ unit, 12 IDCT unit, 13 MC unit, 20 operation speed control unit, 21 buffer state acquisition unit, 22 operation speed parameter setting unit, 30 buffer, 31, 32 arithmetic circuit , 40 Operation speed controller.

Claims (4)

A computer for controlling the operation circuit Ru a buffer,
Acquires the data amount of data stored in the buffer from the buffer,
When the acquired data amount is smaller than the first threshold, a parameter for increasing the operation speed of the arithmetic circuit is set in the arithmetic circuit, and when the acquired data amount is larger than the second threshold , The parameter setting for lowering the operation speed of the arithmetic circuit is set in the arithmetic circuit .
Ru to execute the process control program. In the control program according to claim 1,
Before Kiba Ffa is characterized in that it comprises buffer connected to an input of the arithmetic circuit, buffer connected to the output of the arithmetic circuit, any of the buffers connected via other circuits to the arithmetic circuit It shall be the control program. A control device for controlling the operation circuit Ru a buffer,
A resulting portion preparative you get the data amount of data stored in the buffer from the buffer,
If the amount of data acquired been collected is less than the first threshold value, to set the parameters to increase the operating speed of the arithmetic circuit in the arithmetic circuit, when the amount of data acquired is greater than the second threshold value includes a row cormorant setting tough to the arithmetic circuit sets parameters to lower the operation speed of the arithmetic circuit,
Ru equipped with a control device. A control device for controlling the operation circuit Ru a buffer,
Acquires the data amount of data stored in the buffer from the buffer,
When the acquired data amount is smaller than the first threshold, a parameter for increasing the operation speed of the arithmetic circuit is set in the arithmetic circuit, and when the acquired data amount is larger than the second threshold , The parameter setting for lowering the operation speed of the arithmetic circuit is set in the arithmetic circuit .
That control method to perform the processing.

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