JP3251026B2 - Memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system for transmitting a sampling clock on a transmitting side to a receiving side as frequency information and reproducing the sampling clock on the receiving side to transmit and receive image data. And a memory control device for controlling a memory of the image decoding device .

[0002]

2. Description of the Related Art In a conventional image decoding apparatus, transmission line data transmitted from a transmission side is separated into image data and frequency information, and image data is written into a memory in accordance with a transmitted transmission line clock. Do. The image data is read from the memory by calculating the difference between the separated frequency information and the frequency information generated from the reproduced sampling clock reproduced based on this frequency information, integrating the difference, and then D / A The voltage signal is obtained by the conversion, and the voltage control frequency oscillator is controlled by the voltage signal to obtain a reproduced sampling clock. As described above, in the conventional memory control method, the voltage control oscillator is controlled based on the transmitted frequency information in order to match the image sampling frequency with the transmission side,
Reproducing the sampling frequency.

[0003]

However, in the conventional memory control system, when an error occurs in the transmitted frequency information due to a transmission line error or the like, an erroneous sampling clock is reproduced accordingly. That is, the reading speed of the image data from the memory varies with the writing speed. If such fluctuations occur repeatedly, the occupation amount of the data in the memory changes, and there is a problem that overflow or underflow occurs.

An object of the present invention is to provide a memory control device capable of preventing a memory overflow and an underflow caused by an error in frequency information due to a transmission error.

[0005]

[0006]

According to the present invention, in order to solve the problems], transmit the frequency information and the image data as a result of the sampling clock and counted in a cycle of 1 / N of the cycle of the line clock as multiplexing transmission path data A memory control device that is provided on a receiving side of a transmission system that writes the image data to a memory with the transmission line clock and reads the image data from the memory with a reproduced sampling clock reproduced based on the frequency information A separation circuit that separates the input transmission line data into the image data and the frequency information, a frequency divider that divides the input transmission line clock by N, and a signal from the frequency divider. A counter that counts the reproduced sampling clock at a clock cycle, a subtractor that outputs a difference between the frequency information and the output of the counter, and integrates the output of the subtractor A D / A converter for digital-to-analog conversion of the output of the integrator; a voltage controlled frequency oscillator for outputting a frequency signal corresponding to the output of the D / A converter as the reproduction sampling clock; A memory in which the image data is written at the transmission path clock and the memory reads the image data at the reproduction sampling clock. A full flag output means for outputting a full flag when a predetermined amount of
And an empty flag output means for outputting an empty flag when the full flag is less than or equal to a predetermined amount.
On the basis of the empty flag correcting the frequency information, the memory control device is obtained, characterized in that the corrected frequency information provided correction circuit for outputting to the subtracter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of one embodiment of the present invention.
The image control device of the present embodiment includes a data input terminal 11, a clock input terminal 12, a separation circuit 13, a memory 14, a frequency divider 15, a counter 16, a correction circuit 17, a subtracter 18, an integrator 19, a digital / analog. A (D / A) converter 20, a voltage controlled oscillator (VCO) 21, a data output terminal 22, and a reproduced clock output terminal 23 are provided. The transmission line data 101 input to the data input terminal is separated by the separation circuit 13 into image data 102a and frequency information 103. Here, the frequency information 103 represents the result of counting the transmission side sampling clock by dividing the transmission side sampling clock by N. Image data 102a separated by the separation circuit 13
Is written to the memory 14 with the transmission line clock 104 input to the clock input terminal 12.

The frequency information 103 is input to the correction circuit 17, but is normally output to the subtracter 18 without any operation. The subtractor 18 calculates frequency information 103 from the correction circuit.
And frequency information 105 from the counter 16 to be described later. The obtained difference is integrated by the integrator 19, and D /
The signal is converted into an analog voltage signal by the A converter 20. The voltage signal is input to the VCO 21, and the VCO 21 reproduces the sampling clock 106 having a frequency according to the voltage signal. The reproduction sampling clock 106 is output to the memory 14, and image data is read from the memory 14 by the reproduction sampling clock 106. Then, the read image data 10
2b is supplied to the data output terminal 22.

The reproduction sampling clock 106 is supplied to the clock output terminal 23 and is input to the counter 16. The counter 16 outputs the reproduced sampling clock 106 to one cycle of the transmission line clock 104 divided by N by the frequency divider 15.
Is counted. The counting result is the frequency information 105 described above.
Is output to the subtractor 18.

In this manner, writing and reading of image data to and from the memory 14 are performed. By the way, if an error occurs in the frequency information due to a transmission error or the like, the writing speed of the image data and the reading speed temporarily differ. When such a state where the writing speed and the reading speed are different repeatedly occurs, the memory occupancy of the data gradually becomes 0%,
Or approach 100%. Therefore, the memory 14
A full flag 107 that changes from a high level to a low level when the data memory occupancy exceeds 80%;
When the memory occupancy of the data falls below 20%, the empty flag 108 that changes from a high level to a low level is output to the correction circuit 17. During normal operation (when both the full flag 107 and the empty flag 108 are at high level), the correction circuit 17 outputs the frequency information 103 input as described above to the subtractor 18 as it is. However, when the full flag 107 or the empty flag 108 from the memory 14 changes to a low level, the frequency information 103 is corrected and the corrected frequency information is output. That is, a predetermined value is added to the frequency information 103 when the full flag 107 becomes low level, and a predetermined value is subtracted from the frequency information when the empty flag 108 becomes low level. As a result, when the data memory occupancy exceeds 80%, the frequency of the reproduction sampling clock 106 is increased so as to increase the read speed, and when the data memory occupancy is less than 20%, the read speed is decreased. First, the frequency of the reproduction sampling clock 106 is lowered.

In the memory control device of this embodiment, for example,
The frequency of the clock divided by N by the frequency divider 15 is 31.2
5Hz, frequency of reproduction sampling clock is 14.3MHz
Then, the count value of the counter 16 becomes 228800.
The frequency information output from the separation circuit 13 is 228800
When the full flag and the empty flag are at the high level, the read / write is performed in this state. If the frequency information changes while the full flag and the empty flag are at the high level, the counter 1
The VCO 21 is controlled based on the difference from the frequency information from No. 6 and the sampling clock corresponding to the frequency information is reproduced in due course. When either the full flag or the empty flag changes to low level, the correction circuit 17 corrects the frequency information and controls the read speed to avoid the memory overflow or underflow.

[0012]

According to the present invention, the memory capacity of the memory is the first.
The frequency information transmitted is corrected so as to increase the reading speed when the amount exceeds the predetermined amount, and to reduce the reading speed when the storage amount of the memory becomes equal to or less than the second predetermined amount. By doing so, it is possible to prevent memory overflow and underflow.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 data input terminal 12 clock input terminal 13 separation circuit 14 memory 15 frequency divider 16 counter 17 correction circuit 18 subtracter 19 integrator 20 D / A converter 21 voltage controlled frequency oscillator 22 data output terminal 23 clock output terminal

Continuation of front page (56) References JP-A-47-27411 (JP, A) JP-A-58-92166 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) G06T 1 / 60 G06F 12/00-12/08 G11C 11/34

Claims (2)

(57) [Claims] 1. A receiving side of a transmission system for multiplexing frequency information and image data as a result of counting a sampling clock at a period of 1 / N of a period of a transmission line clock and transmitting the multiplexed image data as transmission line data, A memory control device that writes the image data to a memory with the transmission line clock and reads the image data from the memory with a reproduced sampling clock reproduced based on the frequency information, wherein the input transmission line A separation circuit that separates data into the image data and the frequency information; a frequency divider that divides the input transmission line clock by N; and a count of the reproduced sampling clock based on a clock cycle from the frequency divider A counter that outputs the difference between the frequency information and the output of the counter, an integrator that integrates the output of the subtractor, and a digitizer that outputs the output of the integrator. A digital-to-analog (D / A) converter for performing analog / digital conversion, a voltage-controlled frequency oscillator for outputting a frequency signal corresponding to the output of the D / A converter as the reproduction sampling clock, and writing the image data with the transmission line clock And a memory from which the image data is read out by the reproduction sampling clock, wherein a full flag is output to the memory when the memory occupation amount of the image data becomes equal to or more than a first predetermined amount. Full flag output means, and empty flag output means for outputting an empty flag when the value becomes equal to or less than a second predetermined amount, and corrects the frequency information based on the full flag and the empty flag to output corrected frequency information to the subtractor. A memory control device comprising a correction circuit for outputting. 2. The memory control device according to claim 1 , wherein the correction circuit increases the frequency of the reproduction sampling clock at a predetermined rate when the full flag is input.
A memory control device, wherein when the empty flag is input, the frequency information is corrected so as to lower the frequency of the reproduced sampling clock at a predetermined rate.