JP2002198939A - Digital av signal processing equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital AV signal processing equipment which can control D/A converting speed of digital data stored in a buffer memory. SOLUTION: The digital AV signal processing equipment in this invention is provided with a buffer memory which memorize the input data of the digital AV processing equipment and outputs the digital data as the output digital data; a D/A converter which converts the output digital data to analogue data; a voltage control type oscillator which generates a clock signal for the conversion speed control of the D/A converter; a controller of the voltage control type oscillator which detects the data quantity of the digital data memorized in the buffer memory and controls the frequency of the clock signal based on the deviation from the started first value of the detected data quantity and the time integral value of the deviation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital AV signal processing device. More specifically, the present invention relates to a digital AV signal processing device capable of controlling the speed at which digital data stored in a buffer is DA converted.

[0002]

2. Description of the Related Art In recent years, with the spread of computer networks, digital AV signals representing AV contents are distributed via computer networks, and the receiving apparatus plays back (DA-converts) the digital AV signals while receiving the digital AV signals. The mode of viewing content is becoming widespread.

[0003] In a computer network, the data transmission speed fluctuates, and a short fluctuation (for example, jitter) in the speed of the transmission data may occur. Also, since the clocks are not synchronized between the transmitting device (server or personal computer) and the receiving device (digital AV signal processing device), a clock is generated between the transmitting device clock and the receiving device clock. There is a difference.

When transmitting normal data for processing by a computer, such jitter and clock difference do not matter, but when transmitting digital AV signals, jitter and clock difference become problems. . This is because unpleasant disturbance (for example, skipping sound) occurs in the audio signal or the video signal due to such jitter or clock difference.

Therefore, it is necessary to control the speed at which the digital data stored in the buffer is DA-converted in order to remove unpleasant disturbances occurring in the audio and video signals.
Therefore, the digital data stored in the buffer is
Techniques have been developed to control the speed at which the conversion takes place.

FIG. 12 shows a configuration of a conventional digital AV signal processing apparatus 300. Digital AV signal processing device 30
0 indicates a buffer 31, a DA converter 32, and a voltage-controlled oscillator (Voltage-Controlled Os).
(hereinafter referred to as “VCO”) 33,
A voltage-controlled oscillator controller (hereinafter referred to as “VCO controller”) 34.

[0007] The buffer 31 stores digital data input to the digital AV signal processing device 300 through a transmission system (for example, a computer network), and outputs the digital data as output digital data. D
The A converter 32 converts the output digital data into analog data. The conversion speed of the DA converter 32 is VCO
33 is determined by the clock signal generated.

When the conversion speed of the DA converter 32 is higher than the input speed of the digital data input to the buffer 31,
The data amount of the buffer 31 decreases. From the input speed of the digital data input to the buffer 31, the DA converter 32
If the conversion speed is slow, the data amount of the buffer 31 increases.

The VCO controller 34 includes a buffer 31
Is detected, and the frequency of the clock signal generated by the VCO 33 is controlled so that the conversion speed of the DA converter 32 becomes an appropriate value.

The VCO 33 receives the output data DA3 output from the VCO controller 34. VCO33
Is the output data D output from the VCO controller 34
The higher the value of A3, the higher the frequency of the clock signal. The VCO 33 outputs the data DA output from the adder 36.
The smaller the value of 3, the lower the frequency of the clock signal.

The VCO controller 34 includes a comparator 35
, An adder 36, a reference data amount memory 37, and a reference voltage memory 38.

The reference data amount memory 37 includes a buffer 31
Is stored in a data amount BHLF that is half of the total capacity of BHLF. The reference voltage memory 38 outputs output data DA2 which is data for generating a reference clock frequency. The adder 36
The value of the output data DA1 is added to the value of the output data DA2, and the output data DA3 is output.

FIG. 13 shows the operating characteristics of the comparator 35.
The horizontal axis indicates the data amount BDAT of the buffer 31, and the vertical axis indicates the output data DA1 output from the comparator 35. BMAX is the data amount of the entire capacity of the buffer 31, BH
LF is a data amount that is half of the total capacity of the buffer 31.

If the data amount BDAT increases, the comparator 3
5 increases the value of the output data DA1. When the value of the output data DA1 increases, the value of the output data DA3 increases, and the frequency of the clock signal generated by the VCO 33 is increased to suppress an increase in the data amount BDAT. When the data amount BDAT decreases, the value of the output data DA1 output from the comparator 35 decreases. When the value of the output data DA1 decreases, the value of the output data DA3 decreases, and the VCO 33
, The frequency of the clock signal generated is reduced to suppress a decrease in the data amount BDAT.

By the above operation, the speed at which the digital data stored in the buffer is DA converted is controlled.

[0016]

FIG. 14 shows a digital A
5 shows a change over time of the input speed of digital data input to the V signal processing device 300. The horizontal axis indicates time. The vertical axis is
Indicates the input speed of digital data. At times t1 to t2, times t4 to t5, and times t7 to t8, a short fluctuation (jitter) of the cycle of the input speed occurs. Time t3
From t6 to t6, a long fluctuation of the speed cycle occurs because the clock frequency of the server or the personal computer is unstable.

FIG. 15 shows the amount of data in the buffer 31 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG. The horizontal axis indicates time, and the vertical axis indicates the data amount BDAT of the buffer 31. The times t1, t2, t3, t4, t5, t6, t7, and t8 correspond to the times t1, t2, t3, t4, t4 in FIG.
5, t6, t7 and t8.

FIG. 16 shows the frequency of the reproduced clock signal generated by the VCO 33 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG. The horizontal axis indicates time, and the vertical axis indicates the frequency of the reproduced clock signal generated by the VCO 33. Time t1,
t2, t3, t4, t5, t6, t7 and t8 are the times t1, t2, t3, t4, t5, t6, t7 in FIG.
And t8.

The effect of the short-period fluctuation of the input speed cycle shown in FIG. 14 (see times t1 to t2, times t4 to t5, and times t7 to t8 in FIG. 14) greatly affects the frequency of the reproduced clock signal. Not. That is, the fluctuation (pitch fluctuation) of the frequency of the reproduced clock signal shown in FIG. 16 is suppressed (see time t1 to t2, time t4 to t5, and time t7 to t8 in FIG. 16), and the reproduced sound quality is improved. .

However, the conventional digital AV signal processing apparatus 300 controls the frequency of the clock signal from a predetermined value of the amount of digital data stored in the buffer (for example, a half value BHLF of the buffer capacity). In this case, the data amount BDAT of the digital data stored in the buffer remains constant with a deviation from a predetermined value (time t3 to t3 in FIG. 15).
6), the value of the frequency of the clock signal remains constant (FIG. 1).
6 from time t3 to t6). Therefore, when the input speed of the input digital data is accompanied by a long-period fluctuation, the state in which the data amount of the digital data stored in the buffer deviates from a predetermined value may continue. In such a state, buffer overflow or underflow is likely to occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and stores data in a buffer such that a deviation in the data amount of the buffer caused by a long-term fluctuation of the input speed of input digital data is eliminated. It is an object of the present invention to provide a digital AV signal processing device capable of controlling a speed at which converted digital data is DA-converted.

[0022]

SUMMARY OF THE INVENTION A digital A according to the present invention.
The V signal processing device includes a buffer for storing digital data input to the digital AV signal processing device and outputting the digital data as output digital data; a DA converter for converting the output digital data into analog data; A voltage-controlled oscillator for generating a clock signal for controlling the conversion speed of the converter, and detecting a data amount of the digital data stored in the buffer, and calculating a predetermined first value of the detected data amount. And a voltage-controlled oscillator controller that controls the frequency of the clock signal based on the deviation of the clock signal and the time integral of the deviation, thereby achieving the above object.

The voltage-controlled oscillator controller may be arranged such that a ratio of a change in the frequency of the clock signal to a change in the deviation when the deviation is larger than a predetermined range is:
The frequency of the clock signal may be controlled so as to be greater than a ratio of a change in the frequency of the clock signal to a change in the difference when the difference is smaller than the predetermined range.

The buffer is a ring buffer;
The digital data input to the digital AV signal processing device is input to the ring buffer at a data write position of the ring buffer, and the ring buffer outputs the digital data at a data read position in the ring buffer. The voltage-controlled oscillator controller calculates the data amount of the digital data stored in the ring buffer based on the data read position and the data write position, and the voltage-controlled oscillator controller includes: When the data amount is larger than a predetermined second value larger than the predetermined first value, or when the data amount is smaller than a predetermined third value smaller than the predetermined first value. The data read position and the data write position Kutomo may be changed either.

The voltage controlled oscillator controller may change at least one of the data read position and the data write position so that the data amount after the change becomes substantially half the capacity of the ring buffer. Good.

The digital data is input to the digital AV signal processing device in the form of a plurality of packets, and the voltage-controlled oscillator controller detects the amount of data in the buffer in synchronization with the timing at which the plurality of packets are input. May be.

The digital data is input to the digital AV signal processing device in the form of a plurality of packet groups. Each of the plurality of packet groups has a predetermined number of first packets and second packets having a first data amount. A predetermined number of second packets having a data amount are composed of a plurality of packets arranged in a predetermined order, and the voltage-controlled oscillator controller changes the data amount of the buffer to a timing at which the plurality of packet groups are input. Detection may be performed in synchronization.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a digital A according to an embodiment of the present invention.
1 shows a configuration of a V signal processing device 100. The digital AV signal processing device 100 includes a buffer 1, a DA converter 2,
It includes a CO3 and a VCO controller 4.

The buffer 1 is a digital A through a transmission system.
The digital data input to the V signal processing device 100 is stored, and this digital data is output as output digital data. The DA converter 2 converts the output digital data into analog data. The conversion speed of the DA converter 2 is determined by a clock signal generated by the VCO 3. When the conversion speed of the DA converter 2 is faster than the input speed of the digital data input to the buffer 1, the data amount of the buffer 1 decreases. When the conversion speed of the DA converter 2 is lower than the input speed of the digital data input to the buffer 1, the data amount of the buffer 1 increases. The VCO controller 4 detects the data amount of the digital data stored in the buffer 1, and generates a clock signal generated by the VCO 3 based on a deviation of the detected data amount from a predetermined value and a time integral value of the deviation. To control the frequency.

The VCO controller 4 includes a first control means 5, a second control means 7, a reference data amount memory 13 for storing half the data amount of the total capacity of the buffer 1, an adder 11, 2 holding means 12.

The first control means 5 includes a data amount BDAT of the buffer 1 and a data amount BH which is half the total capacity of the buffer 1.
A first comparator 6 (K1 indicates a gain) for comparing with LF is included. The first comparator 6 detects a deviation between the data amount BDAT and the data amount BHLF, and outputs output data DA1 based on the deviation and the gain K1 to the adder 11.

FIG. 2 shows the operating characteristics of the first comparator 6. The horizontal axis indicates the data amount BDAT of the buffer 1, and the vertical axis indicates the output data DA1 output from the first comparator 6.
Is shown. BMAX is the data amount of the entire capacity of the buffer 1, B
HLF is a data amount that is half of the total capacity of the buffer 1.
The operating characteristic of the first comparator 6 is as follows.
F, 0). The operation cycle of the first control means 5 is set to 10 msec. Based on the operation characteristic (gradient K1) of the first comparator 6 and the operation cycle of the first control means 5, the first control means 5
The time constant of the control means 5 is determined.

The second control means 7 calculates the data amount BDAT of the buffer 1 and the data amount BH which is half the total capacity of the buffer 1.
LF and the output data DA output from the second comparator 8 (K2 indicates a gain).
It includes an integrator 9 for time-integrating 0 and first holding means 10 for holding the output of the integrator 9.

FIG. 3 shows the operating characteristics of the second comparator 8. The horizontal axis indicates the data amount BDAT of the buffer 1, and the vertical axis indicates the output data DA0 output from the second comparator 8.
Is shown. BMAX is the data amount of the entire capacity of the buffer 1, B
HLF is a data amount that is half of the total capacity of the buffer 1.
The operating characteristic of the second comparator 8 is as follows.
F, 0). The operation cycle of the second control means 7 is set to 100 msec. The second control means 7 determines the time constant of the second control means 7 based on the operation characteristics (gradient K2) of the second comparator 8 and the operation cycle of the second control means 7.

The gradient K2 is set to a value much smaller than the gradient K1. The operation cycle of the first control means 5 is set to 10 msec. The second control means 7
The operation cycle is set to 100 msec. here,
1 / time constant = gradient / operation period. Therefore, the first
The time constant of the control means 5 is smaller than the time constant of the second control means 7.

The second comparator 8 detects a deviation between the data amount BDAT and the data amount BHLF, and outputs output data DA0 based on the deviation and the gain K2 to the integrator 9.

The integrator 9 integrates the output data DA0 output from the second comparator 8 with time to obtain an integrated value. The integrated value obtained by the integrator 9 is held by the first holding means 10.

The first hold means 10 outputs the hold value to the adder 11 as output data DA2. The first hold means 10 updates the hold value at a period of 100 ms. The first holding means 10 is provided with the second control means 7
Is necessary when the control cycle of the first control means 5 is set longer than the control cycle of the first control means 5.

The adder 11 adds the output data DA1 and the output data DA2 to obtain output data DA3 output from the VCO controller 4.

The second hold means 12 outputs the output data DA3 of the adder 11 to the VCO 3. The second hold means 12 updates the hold value at a period of 10 ms.

As described above, the first control means 5, the second control means 7, the adder 11, and the second hold means 12
And the reference data amount memory 13 detects the data amount of the digital data stored in the buffer as a whole,
It functions as a VCO controller 4 that controls the frequency of the clock signal based on the deviation of the detected data amount from a predetermined value and the time integral of the deviation.

FIG. 4 shows the operating characteristics of the VCO controller 4. The horizontal axis indicates the data amount BDAT of the buffer 1, and the vertical axis indicates the output data DA3 output from the VCO controller 4. BMAX is the data amount of the entire capacity of the buffer 1, and BHLF is half the data amount of the entire capacity of the buffer 1.

The operating point P0 indicates a state where the input speed of the input data is constant and the data amount is balanced at half of the total capacity of the buffer 1 (BHLF-BDAT = 0). The output data DA3 of the VCO controller 4 at this time is the output data DA30.

Referring to FIG. 4, it is assumed that digital data having a short-period fluctuation and a long-period fluctuation in the input speed is input to digital AV signal processing apparatus 100 including buffer 1.

The data amount of the buffer 1 starts to increase due to the short fluctuation of the cycle of the input speed, and the first control means 5 having a small time constant reacts. Output data D of first control means 5
The value of A1 increases, and the operating point moves from P0 to P1.
The VCO controller 4 generates the output data DA31 and increases the clock frequency to thereby increase the data amount BD.
AT1 enters the equilibrium state once.

Thereafter, the second control means 7 having a large time constant
Of the output data DA2 gradually increases from the output data DA20, and shifts to P2, which is a direction in which the data amount deviation (BHLF-BDAT) is reduced. When the deviation of the data amount (BHLF-BDAT) decreases, the absolute value of the value of the output data DA1 of the first control means 5 also decreases, so that
The value of the output data DA1 and the value of the output data DA2 cancel each other, and as a result, the value of the output data DA3 does not change.
The parallel movement is performed from P1 to P2.

FIG. 5 shows a change in the data amount of the buffer 1 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing apparatus 100 including the buffer 1. The horizontal axis indicates time. The vertical axis indicates the data amount BDAT of the buffer 1. Times t1, t2, t3, t4,
t5, t6, t7, and t8 are the times t1,
These correspond to t2, t3, t4, t5, t6, t7, and t8.

FIG. 6 shows a change in the frequency of the reproduced clock signal generated by the VCO 3 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing device 100 including the buffer 1. The horizontal axis indicates time.
The vertical axis indicates the frequency of the reproduced clock signal generated by the VCO 3. Times t1, t2, t3, t4, t5, t6, t
7, and t8 are times t1, t2, t3, t in FIG.
4, t5, t6, t7, and t8.

From the comparison between FIG. 5 and FIG. 15 and the comparison between FIG. 6 and FIG. 16, the digital AV signal processing apparatus 100 can maintain the stability of the reproduced clock to the same level as in the conventional example.
It can be seen that, compared to the conventional digital AV signal processing device 300, the deviation of the data amount of the buffer from a predetermined value caused by the long fluctuation of the input speed of the input digital data is extremely small.

In the embodiment of the present invention, all the components of the VCO controller 4 are realized by software of a microcomputer. Since the processing load is extremely light, the microcomputer to be used does not need to be a dedicated microcomputer, and is realized by using a part of the processing capacity of the system microcomputer to control the entire device.

It is not essential that the digital AV signal processing device 100 includes the DA converter 2. Digital AV
The output digital data of the signal processing device 100 may be output to a speaker system with a built-in DA converter.

The data amount of the buffer 1 is determined in order to efficiently prevent overflow and underflow of the buffer.
It is desirable that the total capacity of the buffer 1 is about half.
Therefore, the reference data memory 13 is set to store half the data amount of the entire capacity of the buffer 1. However, the data amount stored in the reference data memory 13 may be substantially half of the total capacity of the buffer. Even in this case, the overflow and the underflow of the buffer can be efficiently prevented.

According to the digital AV signal processing apparatus 100 of the embodiment of the present invention, the clock is determined based on the deviation of the data amount of the digital data stored in the buffer from the predetermined value and the time integral of the deviation. Control the frequency of the signal.

When the deviation of the data amount of the digital data stored in the buffer from the predetermined value increases rapidly, the voltage-controlled oscillator controller determines whether the data amount of the digital data stored in the buffer is small. The frequency of the clock signal can be quickly controlled based on a deviation from a predetermined value. Therefore, when the input speed of the input digital data is accompanied by a short-period fluctuation, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.

When the data amount of the digital data stored in the buffer deviates from a predetermined value and becomes constant, the time integral value of the deviation increases with the passage of time. The value never stays constant. Therefore, when the input speed of the input digital data fluctuates with a long period, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.

(Use of Comparator Having Nonlinear Operating Characteristics) In the present invention, it is not essential that the operating characteristics of the first comparator 6 and the second comparator 8 are linear.

When the deviation between the data amount BDAT of the buffer 1 and the data amount BHLF of half of the total capacity of the buffer exceeds a predetermined value, the first comparator 6 and the second comparator 8
Of these, at least one of the operating characteristics may be configured to be steeper. Further, at least one of the first comparator 6 and the second comparator 8 may have a curved operating characteristic.

FIG. 7 shows another operation characteristic of the first comparator 6. The horizontal axis shows the data amount BDAT of the buffer 1,
The vertical axis represents the output data DA output from the first comparator 6.
1 is shown. BMAX is the data amount of the entire capacity of the buffer 1,
BHLF is a data amount that is half of the total capacity of the buffer 1. The operating characteristic of the first comparator 6 is the data amount BDAT
Is the data amount BDAT1 to BDAT2, it is set to a straight line passing through the point (BHLF, 0) with the gradient K10. The operating characteristic of the first comparator 6 is the data amount BDAT
Is the data amount BDAT2 to BMAX, the gradient K
Eleven straight lines are set. The operating characteristic of the first comparator 6 is set to a straight line with a gradient K12 when the data amount BDAT is 0 to BDAT1.

The gradient K11 is larger than the gradient K10. The gradient K12 is larger than the gradient K10.

When the comparator 6 is designed to have the operation characteristics shown in FIG. 7, even if the input data of the buffer 1 fluctuates in a short period of the input speed, the buffer 1 underflows or overflows. Can be effectively prevented.

For example, the data amount B due to abnormal jitter or the like
Even when the DAT becomes small and the operation point moves to an operation point having a data amount equal to or less than the data amount BDAT1, overflow and underflow can be prevented.

FIG. 8 shows another operating characteristic of the second comparator 8. The horizontal axis shows the data amount BDAT of the buffer 1,
The vertical axis represents the output data DA output from the second comparator 8.
Indicates 0. BMAX is the data amount of the entire capacity of the buffer 1,
BHLF is a data amount that is half of the total capacity of the buffer 1. The operating characteristic of the second comparator 8 is the data amount BDAT
Is a data amount BDAT1 to BDAT2, a straight line passing through the point (BHLF, 0) with the gradient K20 is set. The operating characteristic of the second comparator 8 is the data amount BDAT
Is the data amount BDAT2 to BMAX, the gradient K
21 straight lines are set. The operating characteristic of the second comparator 8 is set to a straight line with a gradient K22 when the data amount BDAT is 0 to BDAT1.

The gradient K21 is larger than the gradient K20. The gradient K22 is larger than the gradient K20. When the comparator 8 is designed to have the operation characteristics shown in FIG. 8, even if the input data of the buffer 1 has a long period of change in the input speed, the underflow and the overflow of the buffer 1 can be effectively prevented. Can be prevented.

When the data amount BDAT of the buffer 1 greatly deviates from the data amount BHLF which is half of the total capacity of the buffer 1, the control interval of the second control means 7 is changed and the second control means 7 The constant may be shortened.

As described above, according to the digital AV signal processing apparatus of the embodiment of the present invention, the ratio of the change in the frequency of the clock signal to the change in the deviation when the deviation is larger than the predetermined range is determined by the constant deviation. It is set to be larger than the ratio of the change of the frequency of the clock signal to the amount of change of the deviation when it is smaller than the range. Therefore, overflow and underflow of the buffer can be efficiently prevented.

(Use of Ring Buffer) In the configuration of the digital AV signal processing apparatus 100, the buffer 1 may be the ring buffer 21. Hereinafter, the digital AV signal processing device 100 including the ring buffer 21 will be described.

FIG. 9 shows the concept of a ring buffer. The data amount from the read position RP to the write position WP in the traveling direction indicated by the arrow A is the data amount (unread data amount) stored in the ring buffer 21. The data amount from the write position WP to the read position RP in the traveling direction indicated by the arrow B has already been
Is the data amount of the output digital data output to. The data from the write position WP to the read position RP in the traveling direction indicated by the arrow B is eventually rewritten with newly received digital data.

The digital data input to the digital AV signal processing apparatus 100 is input to the ring buffer 21 at the data write position WP of the ring buffer 21. The ring buffer 21 outputs digital data at a data reading position RP in the ring buffer 21.

The VCO controller 4 calculates the amount of digital data stored in the ring buffer 21 based on the data read position RP and the data write position WP. When the data amount becomes larger than a predetermined value larger than the data amount BHLF, or when the data amount becomes smaller than a predetermined value smaller than the data amount BHLF, the VCO controller 4 sets the data read position RP and the data read position. At least one of the writing positions WP is changed.

When a large input delay occurs in the data input to the ring buffer 21, the read position RP catches up with the write position WP, and an underflow occurs. In addition, a large amount of data that has been delayed due to input delay
1, the write position WP becomes the read position R
P catches up and overflows.

However, the VCO controller 4 controls the write position WP so as not to catch up with the read position RP.
At least one of the write position WP and the read position RP is changed so that the read position RP cannot catch up with the write position WP. Therefore, overflow and underflow of the ring buffer 21 can be prevented. Furthermore, in the case of an underflow, the ring buffer 21
Automatically sends past data that has been written to the device, so there is no instantaneous interruption of sound, and since the sound to be played back is the immediately preceding data, it plays a highly natural sound with a high correlation with the current data It has the advantage of being able to.

When changing at least one of the data read position RP and the data write position WP, the VCO controller 4 sets the write position WP and the read position so that the data amount becomes substantially half of the total capacity of the buffer 1. It is desirable to change at least one of the RPs.

(Case of Digital Data in Packet Format) Hereinafter, a case where digital data input to the digital AV signal processing apparatus 100 is in the form of a plurality of packets will be described.

FIG. 10 shows a digital AV signal processing apparatus 10.
The figure shows the time variation of the data amount of the buffer 1 when the digital data input to 0 is in the form of a packet. The horizontal axis indicates time. The vertical axis indicates the data amount BDA of the buffer 1
T is shown. BMAX is the data amount of the entire capacity of the buffer 1,
BHLF is a data amount that is half of the total capacity of the buffer 1.

Each time a packet arrives, new data in the packet is stored in the buffer 1, and thereafter, the amount of data in the buffer 1 decreases uniformly until the next packet is received. Thus, the digital AV signal processing device 100
Is digital, the data amount BDAT of the buffer 1 increases or decreases in a saw-tooth wave even when there is no jitter. Therefore, the VCO controller 4 is set to detect the data amount of the buffer 1 in synchronization with the timing at which the packet is input.
Further, it is preferable that the total capacity BMAX of the buffer 1 be sufficiently larger than the packet size. For example, the total capacity BMAX of the buffer 1 is at least twice the packet size.

As shown in FIG. 10, at times t1, t2, t3,.
The VCO controller 4 can detect an accurate data amount by reading out the data amount.

As described below, even when digital data input to the digital AV signal processing apparatus 100 is divided into packets having different packet sizes,
By reading the data amount in synchronization with the timing at which the packet is input, the VCO controller 4 can detect the correct data amount of the buffer 1.

FIG. 11 shows a digital AV signal processing apparatus 10.
The figure shows the time variation of the data amount of the buffer 1 when the digital data input to 0 is in the form of a packet divided so as to have a different packet size. The horizontal axis indicates time. The vertical axis indicates the data amount BDAT of the buffer 1.
BMAX is the data amount of the entire capacity of the buffer 1, and BHLF is half the data amount of the entire capacity of the buffer 1.

IEC958 audio signal (sampling frequency 48 kHz, transfer rate 1.536 Mb
ps) to Universal Serial Bus (Universa)
In the case of transmitting a packet using 1 Serial Bus (hereinafter, referred to as “USB”), the USB has a packet structure of 1 msec, and therefore, a 192 byte packet may be transmitted every 1 msec.

On the other hand, when another audio signal of IEC958 (sampling frequency is 44.1 kHz and transfer rate is 1.4112 Mbps) is transmitted as a packet by USB, since the USB has a packet structure of 1 msec, it is cut out at 10 msec. It is necessary to divide the fixed-length data unit of 1764 bytes into ten element packets, for example, nine 176-byte packets and one 180-byte packet.

FIG. 11 shows this signal (the sampling frequency is 44.1 kHz and the transfer rate is 1.4112 Mbp).
5 shows the time variation of the amount of data in the buffer 1 when s) is sent.

In this transmission mode, if the data amount is read at the timing of input of the element packet, it can be seen that the data size of the buffer cannot be accurately detected because the packet sizes are not uniform.

In order to easily detect an accurate data amount, a packet group (10 element packets of 9 176-byte packets and one 180-byte packet)
If the amount of data is detected in synchronization with the timing of input, the amount of data can be accurately grasped.

As described above, the digital data is in the form of a plurality of packet groups in the digital AV signal processing apparatus 100.
, And each of the plurality of packet groups includes nine first packets having a first data amount (176 bytes) and one second packet having a second data amount (180 bytes). , The VCO controller 4 detects the amount of data in the buffer in synchronization with the timing at which a plurality of packet groups are input.

As described above, the digital AV signal processing device 1
When the digital data input to 00 is in the form of a packet, the data amount BDAT of the buffer 1 increases and decreases in a sawtooth manner even in a state without jitter. Therefore, the VCO controller 4 included in the digital AV signal processing device 100 can accurately detect the data amount of the buffer 1 by reading the data amount in synchronization with the timing at which the packet is input.

[0087]

According to the digital AV signal processing apparatus of the present invention, the frequency of the clock signal is determined based on the deviation of the amount of digital data stored in the buffer from a predetermined value and the time integral of the deviation. Control.

When the deviation of the data amount of the digital data stored in the buffer from the predetermined value increases rapidly, the voltage-controlled oscillator controller determines whether the data amount of the digital data stored in the buffer is small. The frequency of the clock signal can be quickly controlled based on a deviation from a predetermined value. Therefore, when the input speed of the input digital data is accompanied by a short-period fluctuation, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.

When the data amount of the digital data stored in the buffer deviates from a predetermined value and becomes constant, the time integral value of the deviation increases with the passage of time. The value never stays constant. Therefore, when the input speed of the input digital data fluctuates with a long period, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.

Further, according to the digital AV signal processing device of the present invention, the ratio of the change of the frequency of the clock signal to the change of the deviation when the deviation is larger than the predetermined range is equal to the deviation of the deviation when the deviation is smaller than the predetermined range. It is set to be larger than the ratio of the change of the frequency of the clock signal to the amount of change. Therefore, overflow and underflow of the buffer can be efficiently prevented.

Further, according to the digital AV signal processing apparatus of the present invention, at least one of the write position WP and the read position RP can be changed by using a ring buffer as a buffer. Therefore, overflow and underflow of the ring buffer can be prevented.

Further, according to the digital AV signal processing device of the present invention, even when digital data input to the digital AV signal processing device is in a packet state, the data amount of the buffer is synchronized with the timing of inputting the packet. Is detected so that the data amount of the buffer can be accurately detected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital AV signal processing device 100 according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation characteristics of a first comparator 6;

FIG. 3 is a diagram showing operation characteristics of a second comparator 8;

FIG. 4 is a diagram showing operating characteristics of a VCO controller 4;

FIG. 5 is a digital AV signal processing device 1 including a buffer 1.
FIG. 14 shows a change in the data amount of buffer 1 when digital data having the characteristics shown in FIG.

6 is a digital AV signal processing device 1 including a buffer 1. FIG.
14 is a diagram showing a change in the frequency of a reproduced clock signal generated by the VCO 3 when digital data having the characteristics shown in FIG.

FIG. 7 is a diagram showing another operation characteristic of the first comparator 6.

FIG. 8 is a diagram showing another operation characteristic of the second comparator 8;

FIG. 9 is a diagram showing the concept of a ring buffer.

FIG. 10 is a diagram showing a time variation of the data amount of the buffer 1 when digital data input to the digital AV signal processing device 100 is in a packet state.

FIG. 11 is a diagram showing a temporal change in the data amount of the buffer 1 when digital data input to the digital AV signal processing apparatus 100 is in a packet state where the digital data is divided so as to have different packet sizes.

FIG. 12 is a diagram showing a configuration of a conventional digital AV signal processing device 300.

FIG. 13 is a diagram showing operation characteristics of the comparator 35;

FIG. 14 is a diagram showing a change over time of the input speed of digital data input to the digital AV signal processing device 300;

15 is a diagram showing a data amount of a buffer 31 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG.

16 is a diagram showing a VC when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG.
The figure which shows the frequency of the reproduction | regeneration clock signal which O33 generates.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer 2 DA converter 3 VCO 4 VCO controller 5 1st control means 6 1st comparator 7 2nd control means 8 2nd comparator 9 Integrator 10 1st hold means 11 Adder 12 2nd Holding means 13 Reference data amount memory 100 Digital AV signal processing device

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hiroyuki Kotani 1006 Kadoma, Kadoma, Osaka Matsushita Electric Industrial Co., Ltd. F term (reference) 5C021 PA23 PA26 PA58 PA79 PA86 SA08 YC02 5C053 FA27 HC02 JA26 KA01 KA07 KA25 LA15 5C063 AB03 AB07 AC01 AC05 CA09 5K047 AA06 CC01 DD01 DD02 GG11 GG44 GG45 GG52 KK01 KK12 KK17 LL02 MM24 MM44 MM50

Claims (6)

[Claims] A buffer for storing digital data input to a digital AV signal processing device and outputting the digital data as output digital data; and a buffer for converting the output digital data into analog data.
An A converter, a voltage-controlled oscillator that generates a clock signal that controls the conversion speed of the DA converter, and a data amount of the digital data stored in the buffer. Predetermined first
Based on the deviation from the value of and the time integral of the deviation,
A digital AV signal processing device comprising a voltage-controlled oscillator controller for controlling the frequency of the clock signal. 2. The voltage-controlled oscillator controller according to claim 1,
When the deviation is larger than a certain range, the rate of change of the frequency of the clock signal with respect to the change of the deviation is the ratio of the frequency of the clock signal to the change of the deviation when the deviation is smaller than the certain range. 2. The digital AV signal processing device according to claim 1, wherein the frequency of the clock signal is controlled so as to be larger than a rate of change. 3. The ring buffer, wherein the digital data input to the digital AV signal processing device is input to the ring buffer at a data write position of the ring buffer, and the ring buffer is Outputting the digital data at a data read position in a ring buffer, wherein the voltage-controlled oscillator controller outputs the data of the digital data stored in the ring buffer based on the data read position and the data write position Calculating the amount; if the data amount is greater than a predetermined second value that is greater than the predetermined first value, or if the data amount is the predetermined first value.
The digital AV signal processing device according to claim 1, wherein at least one of the data read position and the data write position is changed when the value becomes smaller than a predetermined third value smaller than the value. 4. The voltage-controlled oscillator controller according to claim 1,
4. The digital AV signal processing device according to claim 3, wherein at least one of the data read position and the data write position is changed such that the data amount after the change becomes substantially half of the capacity of the ring buffer. 5. The digital data is input to a digital AV signal processing device in the form of a plurality of packets, and the voltage controlled oscillator controller synchronizes the data amount of the buffer with the timing at which the plurality of packets are input. The digital AV signal processing device according to claim 1, wherein the digital AV signal processing device performs detection. 6. The digital data is input to the digital AV signal processing device in a form of a plurality of packet groups,
Each of the plurality of packet groups includes a plurality of packets in which a predetermined number of first packets having a first data amount and a predetermined number of second packets having a second data amount are arranged in a predetermined order. The digital AV signal processing device according to claim 1, wherein the voltage-controlled oscillator controller detects the amount of data in the buffer in synchronization with a timing at which the plurality of packet groups are input.