JPH0697899A - Adjusting method for reproduced clock frequency - Google Patents

Abstract

PURPOSE:To realize normal reproduction of a correct amount of data by adjusting the frequency of a reproduction clock in the digital signal reproducing device which cannot obtain a signal synchronized with the sampling period. CONSTITUTION:A feedback loop is formed by a FIFO buffer 202, a circuit which adjusts the frequency by pulse drop out, and a digital signal reproducing device 301. A reception-side reference clock f0 is set to a frequency slightly higher than a transmission-side reference clock, and a pulse is periodically dropped out to adjust the frequency as the number of clock pulses per unit time. A pulse drop out period N and an adjustment frequency (f) have relations f=f0 (1-1/N, and N is increased when the data volume in the buffer is large, and N is reduced when it is small.

Description

Detailed Description of the Invention

[0001]

[Field of Industrial Application] Reproduction clock frequency when a signal synchronized with a sampling cycle is not given in a signal reproduction apparatus that requires real-time reproduction such as data reproduction for digital communication and data reproduction from a digital data reproduction apparatus. Adjustment method.

[0002]

2. Description of the Related Art When an analog signal such as a voice signal is digitized by PCM and transmitted, and is reproduced by a reproducing device such as a D / A converter, the sampling period during reproduction matches the sampling period during encoding. Need to be
The same applies to the case where a signal digitized by PCM is recorded on a recording medium and this data is read and reproduced. The data read cycle corresponds to the sampling cycle at the time of encoding. Must match the sampling period. If the sampling cycle at the time of encoding is different from that at the time of reproducing, that is, at the time of decoding, excess or deficiency of data occurs and normal reproduction cannot be performed. For example, in the case of an audio signal, it appears as a phenomenon such as waveform distortion, sound interruption, and sound skipping.

In order to realize the matching of the sampling periods, it is common to use a single reference clock and make both sampling periods the same. For example,
When data is read from the recording medium, servo control is performed so that the data read cycle becomes equal to this with reference to the clock during reproduction.

Data can also be compressed after being transferred in a certain amount on a time axis and transferred. If this data transfer is frame synchronous transfer and is sent at the timing synchronized with the sampling cycle, the PLL (Phase Locked L
It is possible to generate a reproduction clock by using the (oop) circuit. Further, the reproduction clock can be generated by the PLL circuit even in the byte synchronous transfer in which the data transfer is synchronized with the reference clock on the transmitting side.

A compact disc (hereinafter abbreviated as CD) player is a typical digital audio data reproducing device. In a CD player dedicated to audio reproduction, the data reading section and the digital audio reproduction section are in one housing,
There is a single reference clock, and control is performed based on this reference clock so that the data read speed from the CD and the digital audio reproduction speed become equal.

On the other hand, a CD-RO is used as a device for recording digital data by using a music CD player technology.
There is an M device, which is used as a storage device of a computer. Digital audio data is obtained from this CD-ROM device, and audio reproduction is performed on the host computer side.
There is also a system in which the data reading unit and the audio reproducing unit are separated. In such a separated audio reproducing system, when reproducing in real time, it is necessary to provide a means for matching the data read cycle from the CD with the sampling cycle during reproduction.

If different oscillators are used even though they have the same frequency on the data reading side and the audio reproducing side, a slight difference in frequency between the two oscillators is accumulated, resulting in excess or deficiency of data.

Therefore, in general, as shown in FIG. 8A, a digital data reproducing device such as a CD-ROM device is used.
A read clock from 11 is directly applied to the digital audio data reproducing device 12, or a signal synchronized with the read clock is applied from the digital data reproducing device 21 to the reproducing device side and reproduced using the PLL circuit 23 as shown in FIG. 8B. A method of generating a clock and giving it to the digital audio data reproducing device 22 is adopted.

[0009]

However, if the data transfer is performed asynchronously and there is no synchronization signal that determines the sampling period, the above method cannot be used.

A similar problem arises in the field of digital voice communication, and means for ensuring clock synchronism is required in order to make the sampling periods of the transmitting side and the receiving side coincide with each other. If the transmission line is time division multiplexed and data is transmitted at equal time intervals on the time axis, synchronization can be achieved by the PLL circuit, but in order to improve the use efficiency of the line, time axis compression or adaptive differential pulse code modulation is performed. In some cases, the audio signal is compressed by (ADPCM), the data is compressed by the variable length coding method, and the synchronization signal cannot be sent due to the delay of the line.

That is, when a signal synchronized with the sampling period cannot be obtained at the time of data reception, or when data is asynchronously sent to the reproducing apparatus, there is a problem that the reproduction clock cannot be generated by the PLL circuit.

An object of the present invention is to adjust the reproduction speed so that the reproduction device does not have an excess or deficiency of data by receiving data sent asynchronously. As a method of adjusting the reproduction clock at the time of reception, there is a method of adjusting the frequency of the reproduction clock by judging from the amount of received data, and there is, for example, Japanese Patent Laid-Open No. 2-179045.

According to the present invention, the adjustment range of the recovered clock is within a minute range within the frequency deviation due to the deviation of the reference clock of the transmitting side, which is peculiar to the oscillator, and temperature and power supply voltage fluctuations, and
Focusing on the fact that it is not necessary to completely match the frequencies if an IFO buffer is used, rather than performing feedback control in an analog manner with a voltage controlled oscillator as in the conventional example, the frequency of the recovered clock is adjusted only with a fixed oscillator and a digital circuit. Provide a way to achieve.

[0014]

[Means for Solving the Problems] (1) A FIFO buffer for temporarily storing data that has been time-axis compressed and is sent asynchronously, (2) a frequency adjustment circuit for adjusting the frequency of a clock that determines a reproduction sampling period, and its control means,
(3) A digital signal reproducing device for reproducing data by reading data from the FIFO buffer. A feedback loop is formed by the above, and the data reproducing speed is controlled so that excess or deficiency of data does not occur.

In order to adjust the frequency deviation of the reference clock of the transmission side and the amount of frequency fluctuation due to various factors, the reference clock of the reception side is set higher than the reference clock of the transmission side, and a periodic loss of clock pulses occurs in this. After processing, the frequency as the number of pulses in a unit time is adjusted by changing the missing period. The reception side reference clock has a frequency that is an integral multiple times sufficiently larger than the sampling frequency to ensure the resolution of frequency adjustment due to pulse loss. The reproduction sampling cycle is given by dividing the clock adjusted based on this reference clock by an integer ratio, and the fluctuation of the cycle due to the adjustment is suppressed to a time corresponding to one clock pulse of the reference clock at most.

[0016]

The oscillator on the receiving side is set to a frequency higher than the maximum frequency excursion of the oscillator on the transmitting side in order to secure a frequency adjustment range due to missing pulses.

The FIFO buffer serves to temporarily store digital audio data, and serves as a buffer between the writing speed of data that is time-axis compressed and sent asynchronously and the reading speed that changes sequentially by clock adjustment, and the data is stored. Prevent loss. The amount of internal data is a criterion for adjusting the reproduction clock frequency.

The reproduced clock generation circuit and control means due to pulse loss periodically generate a missing clock pulse so that the data reception speed and the reproduction speed match, and adjust the frequency of the reproduced clock.

The digital signal reproducing device reads out the data from the FIFO buffer and reproduces the signal at the timing synchronized with the adjusted reproduction clock.

[0020]

EXAMPLE A first example will be described.

FIG. 1 is a block diagram when the present invention is applied to a system composed of a digital data reproducing device and a digital audio reproducing device, and a dotted line inside 200 is a portion for adjusting the reproduced clock of the present invention.

The reference clock on the transmitting side is an fc Hz clock output from the oscillator 101, and the digital data reproducing apparatus 103 synchronizes this reference clock with the clock frequency-divided by the frequency dividing circuit 102 at an integer ratio. The digital audio data from the recording medium. This data is time-axis compressed, read asynchronously, and then the FIFO buffer 202
Stored in. In the case of data compressed by variable length coding, decompression processing is performed and then the FIFO buffer
Written in 202.

Considering the frequency deviation of the oscillator and the frequency fluctuation due to temperature and power supply voltage fluctuations, the maximum frequency deviation Δf
(Maximum of about 200ppm for a crystal oscillator) is decided, and (fc-Δ
The adjustment range is from f) Hz to (fc + Δf) Hz. And, f0 = (fc + Δf + fs) Hz which is slightly higher than fcHz
The oscillator 201 is used as a reference clock on the audio reproducing side. Here, fs is the frequency of the offset added to obtain the adjustment resolution in the vicinity of (fc + Δf) Hz.

The control means 203 judges the amount of data stored in the FIFO buffer 202, and the pulse missing period generation circuit
A control signal for changing the period is given to 204. The pulse drop cycle generation circuit 204 gives the pulse drop timing to the pulse drop circuit 205 by the reference clock given by the oscillator 201 and the internal counter. The pulse missing circuit 205 is a circuit for causing a pulse missing in the reference clock, and periodically outputs a pulse missing clock. This clock is frequency-divided by the frequency divider circuit 206 by the same integer value as that of the frequency divider 102 on the transmission side, and the digital audio reproducing device 301 reads data from the FIFO buffer 202 using this as a sampling clock for reproduction, and D / A Playback by conversion is performed and an audio signal is output.

FIG. 2 shows the relationship between the pulse loss period N and the adjusted frequency f. The frequency of the clock generated by missing pulses (the number of pulses per unit time) is f = f0 (1
-1 / N). fε is the frequency when N is changed by 1, and since the formula is non-linear, it varies depending on each value of N. The minimum resolution required is (fc-Δ
f) Given at the position of NL corresponding to Hz. If there is no offset frequency fs, f = (fc + Δf) becomes an asymptote, so that an attempt to adjust the frequency in this vicinity requires an extremely large value of N, which increases the number of bits of the counter and is not practical. Further, the wider the adjustable N range is, the higher the frequency resolution can be obtained.

FIG. 3 shows an example of a frequency adjusting circuit due to missing pulses. The N-ary counter 11 counts the reference clock of the oscillator 10, and when the count number reaches N, CY =
Output'H '. The D-FF 12 has a role of synchronizing the asynchronous CY output and a role of giving a reload signal to the N-ary counter. The OR gate 13 causes a pulse drop in the reference clock. FIG. 4 shows the timing of this circuit. For convenience of explanation, the value of N is set to a small value of N = 5, but in actuality, a large value of 100 or more is used for N to obtain frequency resolution.
Further, at the time of resetting, an initial value Nc is loaded so that the adjustment clock f becomes closest to fc.

FIG. 5 shows writing and reading of data in the FIFO buffer. Data writing to the FIFO buffer is discretely performed, and data reading is continuously performed.

FIG. 6 shows an example of the control method. f is the frequency,
n is the data amount, N is the pulse loss period, and the subscript t means the transmitting side and r means the receiving side.

The frequency adjustment control is performed at each transfer time of the block data compressed on the time axis. Assuming that T is the block data write cycle and A is the number of clocks required to reproduce 1 byte of data, the write data amount is nt = (ft /
A) · T, and the read data amount is nr = (fr / A) · T. However, because of asynchronous transfer, there is a delay time ΔT in the write cycle. Although the data write amount on the transmission side is constant, this delay time ΔT is converted into the data amount nx = ((fr / A) · ΔT) by the data reproduction speed on the read side, and the write data amount is equivalently ((( ft / A) ・
T-nx). That is, the variation of the transfer delay time corresponds to noise for the control system that receives the amount of data in the buffer as an input. This noise is a high-frequency component when compared with the DC component due to the frequency deviation of the transmitter oscillator and the drift component due to temperature fluctuations, and can be removed by a low pass filter (LPF).

This LPF can be realized by a digital circuit based on the following equation.

[0031]

[Equation 1]

N is the amount of data in the buffer, and n0 is the amount of data in the buffer serving as a control reference. C is a coefficient that determines the time constant of the LPF, and is set to a value that can remove noise. This LPF can be configured by a shift calculation and addition / subtraction calculation circuit, where C is a power of 2, and a register that stores the average value of n.

The transmission side frequency ft becomes the data amount nt through the f-n conversion 11, the data amount fluctuation nx due to the delay time is added to this, and the difference from the feedback data amount nr is taken to obtain the LPF 12
Entered in. The average value of the output n of the LPF 12 is subjected to n-N conversion 13 and becomes a pulse missing period N, and this N is N-f converted.
14 and becomes the reception side frequency fr. Furthermore, fr is f-n
It is converted into the feedback data amount nr. The NN conversion is a conversion with a characteristic having a positive slope as shown in the figure. When the amount of data in the FIFO buffer is large, the read frequency is increased to increase the data read speed, and when the amount of data in the FIFO buffer is small. Reversely lowers the frequency to slow down the reading speed. Therefore, by this feedback loop, the receiving side frequency fr is controlled so as to follow the transmitting side frequency ft.

The second embodiment will be described.

This is different from the first embodiment in the frequency adjusting circuit and control method due to the pulse loss, but the basic operation of changing the clock frequency of the digital signal reproducing apparatus based on the data amount information in the FIFO buffer is the same. is there.

FIG. 7 shows an example of a circuit in which the missing period is constant, which is effective when Δf is small. The control is performed by two values, that is, whether or not a pulse loss having a fixed cycle is generated. The fixed cycle NL is set so that the reproduced clock is (fc-Δf) Hz when a pulse drop is always generated. In this case, the above-mentioned fs is unnecessary and the reference clock f0 of the oscillator 10 may be set to f0 = (fc + Δf) Hz. AND gate 13
Serves as a switch that determines whether or not the pulse drop timing signal is transmitted to the OR gate 14 which is the pulse drop circuit by the control signal CTRL. The operation is the same as that of the circuit of FIG. 3 except that a fixed value is given to the N-ary counter 11.

Next, the control method will be described.

When the amount of data in the FIFO buffer is larger than the reference value, the control signal C is set so that f = (fc + Δf).
When TRL = 'L' and the amount of data is small, f = (fc-Δ
The control of CTRL = 'H' is performed as in (f). When such binary control is performed, the long-term frequency is f
It is determined by the ratio of the period on the time axis occupied by H and fL.

Although the two embodiments have been described above, the control can be performed not only by a digital circuit but also by software using a microcomputer.

[0040]

Even if data is given to the digital signal reproducing apparatus asynchronously, the reproduction speed of the signal is adjusted by the reproduction clock generating method according to the present invention, so that normal reproduction without excess or deficiency of data becomes possible. . Further, since it is composed of only a digital circuit and a fixed frequency oscillator, analog parts are not required, and it is easy to integrate it into a digital integrated circuit, and the adjustment peculiar to the analog circuit is also unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram of a system in which the present invention is applied to a digital audio reproducing device.

FIG. 2 is a diagram showing a relationship between a frequency generated by pulse loss and a pulse loss period.

FIG. 3 is a frequency adjustment circuit diagram due to missing pulses.

FIG. 4 is a timing diagram of the circuit of FIG.

FIG. 5 is a diagram showing writing and reading of data to and from a FIFO buffer.

FIG. 6 is a diagram illustrating a control method of a frequency adjustment circuit.

FIG. 7 is a frequency adjustment circuit diagram due to pulse loss in binary control.

FIG. 8 is a diagram showing a conventional example.

[Explanation of Codes] 101 ... Oscillator on transmission side, 102 ... Divider on transmission side, 103 ... Digital data reproducing device, 200 ... Frequency adjusting unit for reproduced clock, 201 ... Oscillator on receiving side, 202 ... FIFO buffer memory, 203 ... Control means, 204 ... Pulse missing period generation circuit, 205 ... Pulse missing circuit, 301 ... Digital audio reproducing device.

Claims (1)

[Claims] 1. A method for adjusting a reproduction clock frequency, which is described below, when a signal synchronized with a data sampling period is not provided in a digital signal reproducing apparatus for performing real-time reproduction. (1) Received data is FIFO (first-in first-out)
Store in buffer. (2) A clock pulse having a frequency slightly higher than an integral multiple of the sampling frequency is processed so as to cause a missing pulse periodically, and divided by the same integral ratio to generate a reproduced clock. (3) The pulse loss period is changed according to the amount of data in the FIFO buffer, and control is performed so that data is neither excessive nor insufficient during reproduction.