JP2594665B2 - Sampling frequency control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sampling frequency control method for an image encoding apparatus that transmits and reproduces frequency information synchronously sampled with an input image.

(Prior Art) Conventionally, in a frequency control method of an image coding apparatus, a frequency information difference between frequency information transmitted from a transmission side and reproduction frequency information reproduced on a reproduction side is extracted and integrated by an integrator. Further, the value output by the integrator is converted into an analog value by a digital-to-analog converter, and a voltage-controlled crystal oscillator (hereinafter referred to as VCO) is controlled by the analog value to generate a signal having a reproduction sampling frequency. Output.

(Problems to be Solved by the Invention) In the above-mentioned conventional method, the voltage of the VCO is controlled so that the frequency information on the reproducing side and the frequency information on the transmitting side match, but if the frequency information contains an error, the reproduction is performed. It was not possible to match the sampling frequency with the sampling frequency on the transmitting side.

It is an object of the present invention to provide a sampling frequency control method capable of accurately reproducing a signal having a sampling frequency without being affected by an error included in frequency information.

(Means for Solving the Problems) The present invention relates to an apparatus for reproducing an image signal transmitted through a digital communication circuit operating at a signal of a transmission line frequency f _L at a reproduction sampling frequency f _SR , A first frequency divider for dividing the transmission line frequency f _L to 1 / M, a second frequency divider for dividing the reproduction sampling frequency f _SR to 1 / N, and the first frequency divider A reproduction side counter for counting a signal having a frequency divided by the second frequency divider at a period interval of a signal having a frequency divided by the divider;
The transmission side that has been sent by counting the signal having the frequency obtained by _{dividing the} sampling frequency _fSS by 1 / N with the transmission counter at the period interval of the signal having the frequency obtained by dividing f _L by 1 / M. A subtractor for obtaining a difference between the frequency information and the frequency information counted by the reproduction-side counter; and temporarily storing the transmitted data, and outputting the output of the subtractor in accordance with a phase difference between writing and reading the stored data. Means for compensating for the difference, an integrator for integrating the value output from the correction means, a digital-to-analog converter for converting the value output from the integrator to digital-to-analog, and an output from the digital-to-analog converter. A voltage-controlled crystal oscillator for generating a signal having a frequency of the reproduction sampling frequency f _SR based on the set value.

The correction means selects one of an elastic store for temporarily storing the transmitted data and one of a plurality of predetermined values according to a phase difference between a write / read pointer of the elastic store. And a selector for adding the output of the subtractor and the value output by the selector.

(Example) An example of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a transmission line frequency f _L of a signal input from a terminal 1 is divided by a first frequency divider 3 at a predetermined division ratio M. Reproduction sampling frequency f on the reproduction side
Voltage controlled crystal oscillator for generating a signal having a _SR (hereinafter, V
Recorded as CO. ) The frequency output from 12 to the second frequency divider 4
As a result, frequency division is performed at a predetermined frequency division ratio N.
The counter 5 counts the number of clocks having a certain frequency output from the second frequency divider 4 in the cycle interval of the signal having the frequency divided by the first frequency divider 3.

As an example, the frequency after being frequency-divided by the first frequency divider 3 is 31.25 Hz, and the frequency f _{SR of} the signal output from the VCO 12
Assuming that the frequency division ratio is N = 2 and the frequency division ratio is N = 2, the coefficient is calculated at the period interval (1 / 31.25 Hz = 32 msec) of the frequency divided by the first frequency divider 3 output from the counter 5. The frequency of the signal output from the second frequency divider 4 (14.32 MHz / 2
= 7.16 MHz) The number of clocks is 7.16 × 10 ⁶ (Hz) × 32 × 10 ^-3
(Sec) = 229120, and this frequency information is output to the subtractor 6.

Similarly, frequency information obtained by counting by the transmission side counter is input to the subtractor 6 through the terminal 2. The subtracter 6 calculates the difference between the frequency information obtained by counting on the transmitting side and the frequency information obtained by counting on the counter 5 on the reproducing side.

The present invention includes means for correcting the frequency difference extracted as described above. This correction means includes an elastic store (hereinafter referred to as ES) 7, a selector 8, an adder 9
And temporarily store the transmitted data
ES7 write / read pointer phase difference, that is, ES7
The remaining amount of the internal memory is monitored, and the information is sent to the selector 8.

An example of the information transmission is shown below. When the remaining amount of the memory inside the ES 7 is opened by + L samples or more from the reference phase difference, the selector 8 selects the correction value + α by the selector 8 to return to the reference phase difference, that is, to output the data inside the ES 7 earlier, and the voltage of the VCO 12 To the + side to increase the sampling frequency of the signal generated by the VCO 12. Conversely, when the remaining amount of memory in the ES7 is opened by -L samples or more from the reference phase difference, the selector 8 selects the correction value -α to return to the reference phase difference, that is, to accumulate the data inside the ES7 quickly. Then, the voltage of the VCO 12 is lowered to the negative side to lower the sampling frequency of the signal generated by the VCO 12. If the remaining amount of the memory inside the ES 7 is within the reference phase difference ± L samples, the selector 8 selects the correction value 0 so as to maintain the data amount inside the ES 7 so as not to change the sampling frequency.

Next, the adder 9 adds the correction value output from the selector 8 to the frequency information difference output from the subtractor 6,
Make corrections.

The information output from the adder 9 is input to the integrator 10 and
The integrated information is input to the digital / analog converter 11. The information converted into the analog value controls the oscillation frequency of the VCO 12 to change the frequency. The oscillated signal having the reproduction sampling frequency f _SR is output to the terminal 13 and to the frequency divider 4.

In this way, if the reproduced sampling frequency does not match the sampling frequency on the transmitting side due to the fact that the frequency information contains an error, the phase difference detected by the ES7 shifts, and the position detected by the ES7 By correcting the frequency information according to the phase difference, the sampling frequency on the reproduction side is suppressed in voltage by the VCO 12 so as to match the sampling frequency on the transmission side.

By repeating this, the sampling frequency on the transmission side and the reproduction sampling frequency can be matched.

(Effect of the Invention) As described above, the present invention provides an image encoding apparatus that transmits and reproduces frequency information synchronously sampled with an input image, in which the calculation result of the transmission-side frequency information and the reproduction-side frequency information has an error. Is included, the sampling frequency on the reproduction side can be matched with the sampling frequency on the transmission side.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 2 ... Transmission-side frequency information input terminal, 3,4 ... divider, 5 ... counter, 6 ... subtractor, 7 ... ES (elastic store), 8 ... selector, 9 ... adder, 10 ... integrator, 11: Digital / analog converter, 12: VCO (voltage controlled crystal oscillator), 13: Reproduction sampling frequency output pin.

Claims (3)

(57) [Claims] 1. An apparatus for reproducing an image signal transmitted through a digital communication circuit operated by a signal having a transmission line frequency f _L at a reproduction sampling frequency f _SR, wherein the transmission line frequency f _L is 1 / A first frequency divider that divides the frequency by M, a second frequency divider that divides the reproduction sampling frequency _fSR by 1 / N, and a frequency that is frequency-divided by the first frequency divider are A reproduction-side counter for counting a signal having a frequency divided by the second frequency divider at a period interval of a signal having the signal;
The transmission side that has been sent by counting the signal having the frequency obtained by _{dividing the} sampling frequency _fSS by 1 / N with the transmission counter at the period interval of the signal having the frequency obtained by dividing f _L by 1 / M. A subtractor for obtaining a difference between the frequency information and the frequency information counted by the reproduction-side counter; and temporarily storing the transmitted data, and outputting the output of the subtractor in accordance with a phase difference between writing and reading the stored data. Means for compensating for the difference, an integrator for integrating the value output from the correction means, a digital-to-analog converter for converting the value output from the integrator to digital-to-analog, and an output from the digital-to-analog converter. A sampling frequency control method, comprising: a voltage-controlled crystal oscillator that generates a signal having a frequency of a reproduction sampling frequency f _SR based on the set value. 2. The sampling frequency control system according to claim 1, wherein said correction means includes a phase difference between an elastic store for temporarily storing transmitted data and a write / read pointer of said elastic store. And a selector for selecting and outputting one of a plurality of values determined in advance in accordance with a frequency information difference output from the subtractor and a value output from the selector. Characteristic sampling frequency control method. 3. The sampling frequency control method according to claim 2, wherein said selector has three of the predetermined plurality of values of + α, 0, and −α. Frequency control method.