JP2001156760A - Communication system, control method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate delay fluctuations caused on a network. SOLUTION: Synchronization information represents a difference (β) between a count N (=3240000) and a PCR value E caused equivalently to a case that a 3rd PCR packet reaches a transmitter 201 at a point of time (time t1) when the count N reaches 3240000 on the basis of a difference (α) between a PCR value E3 and a count N3 caused while clocks by (count value N3-a reference clock value B) are counted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus, a communication method, and a recording medium, and more particularly, to a communication apparatus capable of transmitting and receiving audio data and video data digitized using ATM communication technology. And methods and media.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration example of a conventional data transmission system. It is assumed that the network 3 to which each of the encoding side and the decoding side is connected uses a satellite, similarly to the transmission method in digital CS broadcasting. That is, it is assumed that data transmitted via the network 3 has a delay at a constant interval.

An encoder 1 converts video data and audio data as data to be transmitted, for example, into MPEG data.
Encode according to the -2 method and output to the system encoder 2. The system encoder 2 packetizes the input video data and audio data, generates a transport stream packet, and multiplexes it with another transport stream as necessary,
Output on the network 3.

The system encoder 2 also incorporates a PCR (Program Clock Reference), which is a time stamp, into the header of the generated transport stream packet as shown in FIG. A stream packet is called a PCR packet.) This PCR is the system clock C in the system encoder 2 counted at the timing when the transport stream is output from the encoding side.
1 (Clock with a frequency of 27 MHz for MPEG-2 system)
Is the count value. According to the MPEG-2 standard, the PCR is incorporated in the transport stream so that at least one PCR is output from the encoding side every 0.1 second.

Returning to FIG. 1, a transport stream packet (including a PCR packet) output from the encoding side reaches the decoding side via the network 3 and is input to the system decoder 4. Note that the transport stream transmitted via the network 3 has a constant delay, so that the
The packet arrives at the decoding side at the same interval as that transmitted from the encoding side (the difference is within +/- 500 ns of the MPEG-2 standard).

[0006] The system decoder 4 depackets the input transport stream packet and outputs the resulting audio stream or video stream to the decoder 5. As shown in FIG. 2, the system decoder 4 extracts the PCR from the PCR packet, and compares the PCR with the count value of the decoding-side system clock C2 (clock of 27 MHz) counted at the timing when the PCR is extracted. The speed of the system clock C2 is adjusted based on the comparison result and supplied to the decoder 5.

The decoder 5 decodes the audio data or the video data supplied from the system decoder 4 in synchronization with the system clock C2 supplied from the system decoder 4.

Next, the generation (adjustment) processing of the system clock C2 on the decoding side will be further described with reference to FIGS. The system decoder 4 is configured as shown in FIG. The transport stream packet supplied to the system decoder 4 is supplied to the system decoder 11 and the time stamp extracting circuit 12 of the system decoder 4.

[0009] As shown in FIG. 2, the time stamp extracting circuit 12 extracts the PCR incorporated in the PCR packet and outputs the extracted PCR to the PLL circuit 13. The PLL circuit 13 is configured, for example, as shown in FIG.
PCR extracted by the time stamp extraction circuit 12,
And the count value of the counter 24 (the D / A converter / VCO 23
The clock count value output from the) is input.
The subtracter 21 receives the PCR from the time stamp extracting circuit 12.
, And the difference from the count value from the counter 24 is calculated and output to a low-pass filter (hereinafter abbreviated as LPF) 22. The LPF 22 temporally smoothes the input operation result from the subtractor 21 and outputs the result to a D / A converter / VCO (voltage controlled oscillator) 23. D / A converter and VCO23 are LPF
The digital signal input from the converter 22 is converted into an analog signal, and the analog signal is used as a control voltage to generate a system clock C2 having a frequency corresponding to the control voltage.
The D / A converter / VCO 23 outputs the generated system clock C2 to the counter 24 and the decoder 5.

The counter 24 is a D / A converter / VCO 23
, And supplies the count value to the subtractor 21 as a signal representing the frequency and phase of the system clock C2 at that time. That is, in the PLL circuit 13, the PCR incorporated in the transport stream packet and the system clock C counted at the timing at which the PCR is taken out (the timing at which the PCR packet arrives at the decoding side).
The speed of the system clock C2 is adjusted so that the difference between the count values of 2 is eliminated. As a result, a system clock C2 on the decoding side that is synchronized with the system clock C1 on the encoding side is generated.

Returning to FIG. 3, the system decoding unit 11
The input transport stream packet is depacketized, and the resulting audio stream and video stream are output to the decoder 5.

When a satellite is used as the network 3 in a manner similar to the transmission method in satellite broadcasting, a fixed delay is added to the transport stream packet transmitted from the encoding side. That is, the transport stream packet transmitted from the encoding side arrives at the decoding side with a delay of a predetermined time or hasten. In this case, since the delay time or the speeding time is constant, the arrival interval of the transport stream packet (including the PCR packet) to the decoding side is the same as the output interval from the encoding side. Therefore, in this case, by using the method described with reference to FIGS. 3 and 4, the system clock C2 on the decoding side is generated so as to be synchronized with the system clock C1 on the encoding side.

[0013]

However, when an ATM (Asynchronous Transfer Mode) network is used as the network 3, the transport stream packet transmitted from the encoding side has, for example, A delay fluctuating in the range of 1 ms to 2 ms (hereinafter referred to as delay fluctuation) is added. In this case, in the data transmission system described above, the delay fluctuation is not absorbed, and eventually, the magnitude of the delay is reduced according to the MPEG-2 standard.
The data is not properly reproduced because it greatly exceeds the range of +/- 500ns.

Therefore, a synchronization method such as an adaptive clock method has been proposed in which a system clock is generated after the delay fluctuation is reduced to some extent on the decoding side.

FIG. 5 shows an example of the configuration of an adaptive clock section 51 of a decoding device to which the adaptive clock method is applied. It is assumed that data transmitted via the network 50 has a delay fluctuation.

The data having delay fluctuation transmitted through the network 50 is input to the FIFO 52 of the adaptive clock unit 51. The FIFO 52 temporarily stores input data and outputs data in response to a predetermined read clock supplied from the control unit 53. The FIFO 52 also determines its own data occupancy by LP
Output to F54. The LPF 54 smoothes the data occupancy of the FIFO 52 and outputs it to the control unit 53.

The control unit 53 controls the speed of the read clock output to the FIFO 52 so that the data (smoothed data occupancy of the FIFO 52) supplied from the LPF 54 becomes a predetermined value. That is, in the adaptive clock method, the clock controlled by the control unit 53 is the system clock on the decoding side.

As described above, in the adaptive clock system, the system clock on the decoding side is generated based only on the received data, so that the configuration of the apparatus can be simplified. However, in this example, since the jitter component is only shaved in an analog manner, the jitter component remains in a long time,
There is a problem that the delay fluctuation is not sufficiently absorbed.

On the encoding side, a transmitting device 61 having a configuration as shown in FIG. 6 and on the decoding side,
A data transmission system including a receiving device 62 having a configuration as shown in FIG. 7 has also been proposed. This is, for example,
This is a system for transmitting a plurality of programs synchronized with respective clocks in each television broadcasting station or program creation company.

[0020] As shown in FIG.
L circuit 71 and N synchronous data creating units 72-1 to 72
−N (hereinafter, when there is no need to distinguish them here, simply described as a synchronization data creation unit 72. The same applies to other parts). The PLL circuit 71 is supplied with an 8 KHz clock which is a network clock of the network 63. The PLL circuit 71 is provided with a phase comparator 91 configured as shown in FIG. The VCO 92 of the phase comparator 91 generates a predetermined phase of 27 MHz based on the signal supplied from the phase comparator 94, outputs it to the frequency divider 93, and generates the synchronous data generators 72-1 to 72-. Also output to each of N.

The frequency divider 93 receives the 2 input from the VCO 92.
The 7 MHz clock is divided into 1/3375 to generate an 8 KHz clock, which is output to the phase comparison unit 94. The phase comparison unit 94 compares the phase of the 8 kHz clock from the network 63 with the phase of the 8 kHz clock from the frequency divider 93 and outputs the comparison result to the VCO 92.

The synchronous data generator 72-1 includes a PLL circuit 8
1, a latch circuit 82, a clock 83, and the like. PLL circuit 81 of synchronous data creation unit 72-1
Is supplied with a time stamp included in data created in synchronization with a predetermined clock. PLL
The circuit 81 has basically the same configuration as the PLL circuit 13 shown in FIG. That is, the PLL circuit 81 generates a predetermined clock based on the input time stamp and outputs the clock to the latch circuit 82.

The latch circuit 82 performs a latch process in accordance with the clock from the PLL circuit 81 and the clock from the clock 83. Data reproduced according to the processing result of the latch processing is set as synchronous data, and is incorporated into a predetermined transport stream packet.

Synchronous data generators 72-2 to 72-N
Has the same configuration as that of the synchronization data creation unit 72-1. Although illustration and detailed description are omitted, a time stamp included in data created in synchronization with different clocks is input. , And creates synchronous data corresponding to the clock.

[0025] As shown in FIG.
L circuit 101 and N system clock reproducing units 102-
1 to 102-N are provided. The PLL circuit 101 has a network clock 8 of the network 63.
A KHz clock is supplied. The PLL circuit 101, like the PLL circuit 71 of the transmission device 61, generates a 27 MHz clock corresponding to the input 8 KHz clock, and outputs it to each of the system clock reproducing units 102-1 to 102-N.

The system clock reproducing unit 102-1 includes a clock 110, a PLL circuit 111, and the like. Clock 1 of system clock reproducing unit 102-1
10, the clock supplied from the PLL circuit 101 is input, and the clock 110 divides the clock by 1/270000000.
The frequency is divided to 0 and output to the PLL circuit 111. PLL circuit 111
In addition to the clock from the clock 110, the transmitting device 6
The synchronization data created by the first synchronization data creation unit 72-1 is supplied. Therefore, the PLL circuit 111 reproduces the system clock based on the input clock and the synchronization data.

System clock reproducing units 102-2 to 102-1
02-N also has a configuration similar to that of the system clock reproduction unit 102-1 and is not shown in the figure, but they are supplied from the corresponding synchronization data generation unit 72 of the transmission device 61. Regenerate system clock using synchronous data. Since the reproduced system clock is synchronized with the clock at the time of encoding the respective data, the data is appropriately reproduced by decoding the data according to the clock.

However, in the above-described data transmission system, it is necessary to provide the synchronous data generating unit 72 and the system clock reproducing unit 102 for each clock at the time of encoding, and the configuration of the device becomes complicated and the size becomes large. was there.

The present invention has been made in view of such a problem, and can easily and surely absorb delay fluctuations, and can implement a plurality of programs without increasing the size and complexity of the apparatus. The corresponding data can be transmitted and received.

[0030]

According to the present invention, there is provided a communication apparatus, comprising: detecting means for detecting unit data arranged in a stream and having the same value as synchronous data incorporated at the head of a packet constituting the stream. Detecting unit data arranged in the stream for each packet size from the arrangement position on the stream of the unit data having the same value as the synchronous data detected by the detecting means, and detecting the continuous data among the detected unit data. First counting means for counting the number of unit data having the same value as the synchronous data detected by
When the number of unit data counted by the first counting means and having the same value as the continuously detected synchronous data reaches a predetermined number, one of the detected unit data is counted.
The apparatus is characterized in that the arrangement position of one unit data on the stream is set as the head of the packet, and a synchronization establishing means for establishing the synchronization of the streams is provided.

[0031] The unit data arranged in the stream is detected for each packet size from the arrangement position of the unit data at the head of the packet on the stream to which synchronization has been established by the synchronization establishment unit. Then, a second counting means for counting the number of unit data having a value different from the synchronization data, which is continuously detected, among the detected unit data, may be further provided.
When the number of unit data counted by the second counting means and having a value different from the continuously detected synchronization data has reached a predetermined number, the number is equal to the synchronization data.
The unit data arranged in the stream can be detected again.

In the case where a predetermined time stamp is added to the stream, the first counting means determines that when unit data having the same value as the synchronization data, the same value as the time stamp, and the same value as the synchronization data are successively detected, It can be assumed that the unit data having the same value as the synchronous data is continuously detected.

According to a fourth aspect of the present invention, there is provided a communication method comprising the steps of: detecting a unit data arranged in a stream, which has the same value as synchronous data incorporated at the head of a packet constituting the stream; From the detected arrangement position of the unit data in the stream having the same value as the synchronization data, the unit data arranged in the stream is detected for each packet size, and the detected unit data is continuously detected. A counting step for counting the number of unit data having the same value as the synchronization data; and the number of unit data having the same value as the synchronization data detected continuously in the counting step is a predetermined number. When the position of one of the detected unit data on the stream is set as the head of the packet, Characterized in that it comprises a synchronization establishment step of establishing the period.

According to a fifth aspect of the present invention, the recording medium includes a detecting step of detecting unit data arranged in the stream and having the same value as the synchronization data incorporated at the head of a packet constituting the stream, and a processing of the detecting step. From the detected arrangement position of the unit data in the stream having the same value as the synchronization data, the unit data arranged in the stream is detected for each packet size, and the detected unit data is continuously detected. A counting step for counting the number of unit data having the same value as the synchronization data; and the number of unit data having the same value as the synchronization data detected continuously in the counting step is a predetermined number. When the position of one of the detected unit data on the stream is set as the head of the packet, Characterized in that it comprises a synchronization establishment step of establishing the period.

In the communication device according to the first aspect, the communication method according to the fourth aspect, and the program of the recording medium according to the fifth aspect, the same value as the synchronization data incorporated at the head of the packet constituting the stream. The unit data arranged in the stream is detected, and the unit data arranged in the stream is detected for each packet size from the detected arrangement position on the stream of the unit data having the same value as the synchronization data. Of the detected unit data, the number of continuously detected unit data having the same value as the synchronization data is counted, and the counted unit data having the same value as the continuously detected synchronization data is counted. Number,
When the predetermined number is reached, the arrangement position of one of the detected unit data on the stream is set as the head of the packet, and the synchronization of the stream is established.

[0036]

FIG. 9 shows a configuration example of a data transmission system to which the present invention is applied. In this system, an MPEG transport stream conforming to the MPEG-2 system is transmitted over a network 202 which is an ATM network.
Sent and received via That is, the network 202
Causes delay fluctuations in data transmitted via the.

An MPEG transport stream packet in which a plurality of encoded programs are multiplexed is input to the transmission device 201. The MPEG transport stream packet incorporates a PCR packet so that the PCR arrives at the receiving device 203 at least within an interval of 0.1 second.

As shown in FIG. 10, the MPEG transport stream packet includes a header section, an adaptation field section, a payload section, and the like.
It is a fixed packet of bytes. In the header part, synchronization byte (8 bits), error indication (1 bit), unit start indication (1 bit), transport packet priority (1 bit), PID (Packet Identification) (13 bits)
Bits), scramble control (2 bits), adaptation field control (2 bits), and cyclic counter (4 bits). Note that the synchronization byte is 47h.

The adaptation field portion includes an adaptation field length (8 bits), a discontinuity indication (1 bit), a random access indication (1 bit), a stream priority indication (1 bit), a flag (5 bits),
It includes a program clock reference base (33 bits), a reserve (6 bits), and a program clock reference extension (9 bits). Note that there are five types of flags including a PCR flag (1 bit).

The payload section contains data.

The MPEG transport stream packet has the above data structure. However, as shown in FIG. 10, the adaptation field control of the header is set to "10" or "11", and the adaptation field of the adaptation field is When the adaptation field length is a value other than 00h and the PCR flag is set to “1” (hereinafter, such data setting is referred to as a PCR packet condition), the MPEG transport stream packet is a PCR packet. The combination of the value of the program clock reference base and the value of the program lock reference extension in the adaptation field portion indicates the PCR value.

In the program clock reference base, values from 0 to 299 are set (counted) in order, and the value of the program clock reference base is 2
At the timing of returning (resetting) from 99 to 0, the value of the program clock reference extension is incremented by one. That is, a total of 42 bits of the program clock reference base and the program clock reference extension count 24 hours of time in units of a 27 MHz system clock in the MPEG-2 system.

Returning to FIG. 9, the input
The MPEG transport stream packets (including the PCR packets) are then converted into ATM cells and transmitted over the network 202.
Predetermined synchronization information (described later) created based on the value is written.

The ATM cell transmitted via the network 202 arrives at the receiving device 203, where the ATM cell
Although converted to a transport stream, the PCR value included in the PCR packet is modified based on the synchronization information written in the PCR packet. MPEG transport stream packets containing PCR packets with modified PCR values
The data is supplied to a decoder (not shown) and decoded there.

FIG. 11 shows a configuration example of the transmitting apparatus 201. An MPEG transport stream packet supplied to the transmitting apparatus 201 is input to an MPEG transport stream packet synchronizer (hereinafter, abbreviated as a TS packet synchronizer) 211. The TS packet synchronization unit 211
The head of the input MPEG transport stream packet is detected, frame synchronization is established, and after the frame synchronization is established, the MEPG transport stream packet is output to the PCR packet detection unit 212.

The PCR packet detecting section 212 refers to the header section and the adaptation field section of the MPEG transport stream packet (the MPEG transport stream packet with frame synchronization) input from the TS packet synchronizing section 211, It is determined whether or not the PCR packet condition is set, and if it is determined that the PCR packet condition is set, that is, if the MPEG transport stream packet is a PCR packet, a signal indicating that (hereinafter, a signal indicating that). A PCR packet detection signal is output to the synchronous information processing unit 213. Note that the PCR packet detection unit 212 outputs the input MPEG transport stream packet to the synchronous information processing unit 213 without performing any processing.

The synchronous information processing unit 213 receives the MPEG transport stream packet and the PCR packet detection signal from the PCR packet detection unit 212,
From 4, the count value is input.

The synchronous information processing section 213 reads the PCR from the MPEG transport stream packet (PCR packet) specified by the PCR packet detection signal from the PCR packet detection section 212 and reads the PCR. , And calculates predetermined synchronization information (details will be described later). The synchronization information processing unit 213 writes the calculated synchronization information into the PCR packet,
Output to TM conversion section 216.

The memory 215 stores data necessary for calculating the synchronization information supplied from the synchronization information processing unit 213 as appropriate. In this example, the synchronization information calculation processing by the synchronization information processing unit 213 is performed for each program (set in the MEPG transport stream packet).
(For each PID), so that the memory 215 stores the data supplied from the synchronous information processing unit 213 for each program.

[0050] The MPEG / ATM conversion section 216 converts the MPEG transport stream packet into an ATM cell and transmits the ATM cell to the network 202. The MPEG / ATM conversion unit 216 also receives ATM cells sequentially transmitted from the network 202, generates an 8 KHz clock synchronized with the network clock of the network 202 based on the received ATM cells, and outputs the clock to the PLL circuit 217. I do.

The PLL circuit 217 has a phase comparator 250 as shown in FIG. 12, for example, like the PLL circuit 71 in FIG. The VCO 251 generates a predetermined phase of 27 MHz based on the signal supplied from the phase comparison unit 252,
Output to the counter 214 and the frequency divider 253. The frequency divider 253 divides the frequency of the 27 MHz clock input from the VCO 251 by 1/3375, generates an 8 KHz clock, and outputs the clock to the phase comparator 252. Phase comparison unit 252
Compares the phase of the 8 KHz clock from the MPEG / ATM conversion unit 216 with the phase of the 8 KHz clock from the frequency divider 253, and outputs the comparison result to the VCO 251. That is, the phase of the 27 MHz clock output to the counter 214 is adjusted so as to synchronize with the network clock of the network 202.

Returning to FIG. 11, the counter 214 counts the 27 MHz clock from the PLL circuit 217 to 1/324000.
It divides by 0, counts, and outputs the count value N to the synchronous information processing unit 213. That is, the counter 214 counts a clock synchronized with the network clock of the network 202.

Next, the operation of TS packet synchronization section 211 of transmitting apparatus 201 will be described with reference to the flowchart of FIG.

In step S1, the TS packet synchronization unit 211 reads the data of the input MPEG transport stream packet byte by byte, and determines that the read value is 47h (FIG. 10) equal to the synchronization byte. stand by. When determining that the value of the read one byte is 47h, the TS packet synchronization unit 211 proceeds to step S2 and initializes the value of a counter i for counting the number of times 47h is read to 1.

Next, in step S3, the TS packet synchronizer 211 reads data (data after 188 bytes) separated by 188 bytes from 47h read in step S1.
Is determined. If it is determined in step S4 that the data read in step S3 is not 47h, the TS packet synchronization unit 211 returns to step S1 and executes the subsequent processing. On the other hand, if it is determined in step S4 that the read data is 47h, the TS packet synchronization unit 211 proceeds to step S5.

In step S5, the TS packet synchronizer 211 determines whether or not the value of the counter i is 5,
When it is determined that the value is not 5, the process proceeds to step S6, the value of the counter i is incremented by 1, and the process returns to step S3 to execute the subsequent processes. Step S
When it is determined at 5 that the value of the counter i is 5,
That is, when 47h is read five times consecutively every 188 bytes from the data of the input MPEG transport stream packet, the process proceeds to step S7.

In step S7, the TS packet synchronizer 211 sets 47h detected at the fifth time as a synchronization byte,
That is, frame synchronization is established using the data as the head data of the MPEG transport stream packet. In step S7, before the frame synchronization is established, the transmission device 20
The data input to 1 is not supplied to the PCR packet detection unit 212 and is discarded.

As described above, frame synchronization is established.

Next, in step S8, the TS packet synchronizer 211 initializes the value of the counter i to 1 and proceeds to step S9, where the synchronization byte is converted from 47h to 188.
The byte-separated data is read, and in step S10, it is determined whether or not it is 47h.

If it is determined in step S10 that the data read in step S9 is not 47h,
The TS packet synchronizer 211 proceeds to step S11, determines whether or not the value of the counter i is 3, and if it determines that the value is not 3, proceeds to step S12, and increases the value of the counter i by 1 The value is incremented, the process returns to step S9, and the subsequent processes are executed. On the other hand, step S11
When it is determined that the value of the counter i is 3, the process returns to step S1, and the subsequent processes are executed. That is, if it is determined in step S9 that the data read is not 47h three times in a row, it is determined that frame synchronization of the MPEG transport stream packet is not established, and the process returns to step S1 to establish synchronization. Is performed from the beginning. In addition, before the process for establishing synchronization is performed again from the beginning,
Data of 3 × 188 bytes, which is expected not to be synchronized, is supplied to the PCR packet detection unit 212.

In step S10, the TS packet synchronizer 211 stores the data read in step S9 for 47h.
If it is determined that the above is true, the process returns to step S9, and the subsequent processing is executed.

Another method for establishing synchronization will be described with reference to the flowchart in FIG. In this example, the TS packet synchronization unit 211 has 188 memory areas i (= 1, 2,..., 1) as shown in FIG.
88) is built in. In the initial state, a value 0 is set in each memory area i of the 47h counting section.

In step S21, the TS packet synchronizer 211 reads out the input MPEG transport stream packet byte by byte, waits until 47h is detected, and when 47h is detected, proceeds to step S22, in which the value of the counter i is read. Is incremented by one, and in step S23, the value of the memory area i (= 1) specified by the value of the counter i is incremented by one.

In FIG. 16B, 47
Data 1 to Data 5 divided every 188 bytes from the position where h is detected are shown. FIG. 16A shows the bytes constituting each data and the corresponding 47h count area memory area i of the count section. Values are shown. The value of the memory area 1 corresponding to the first data (47h) of the data 1 is
1 is set. In FIG. 16, xxh is 47
Data other than h are shown.

Next, in step S24, the TS packet synchronizer 211 detects the 47h
The next one byte of data is read, and step S25
, The value of the counter i is incremented by one.

In step S 26, the TS packet synchronization unit 211 stores the data read in step S 24
h, and if it is not 47h, the process proceeds to step S27.

In the case of data 1 in FIG. 16, the next 1 after 47h
Since the byte data is not 47h (“xx
h ”), step S2
Proceeding to 7, the TS packet synchronization unit 211 sets 0 in the memory area 2.

Next, in step S28, the TS packet synchronizer 211 determines whether or not the value of the counter i is 189, and when it is determined that the value is not 189,
Returning to step S24, the subsequent processing is executed.

If it is determined in step S26 that the read data is 47h, the process proceeds to step S29.
The TS packet synchronization unit 211 increments the value of the memory area i specified by the value of the counter i by one. Since the data that is k bytes away from the first byte of data 1 is 47h, the value of the memory area k is incremented by one.

Next, in step S30, the TS packet synchronizer 211 determines in step S29 whether or not the value of the memory area i whose value is incremented by 1 is 5, and if the value is not 5, If it is determined, the process returns to step S28, and the subsequent processes are executed.

If it is determined in step S28 that the value of the counter i is 189, the process returns to step S22, and the TS packet synchronizer 211 determines in step S30 to execute the subsequent processing that the value of the memory area i is If it is determined that the value is 5, the process proceeds to step S31, and when the counter i = 5, the TS packet synchronization unit 211 sets 47h read in step S24 as a synchronization byte and establishes frame synchronization of the MPEG transport stream. FIG.
In the example of No. 6, when 47h, which is k bytes away from the head data of the data 5, is being read, the value of the memory area k is 5
Therefore, 47h of the data 5 read at that time is set as a synchronization byte, and frame synchronization is established.

The processes in steps S32 to S36 are the same as those in steps S8 to S12 in FIG. 13, and a description thereof will be omitted.

Next, the processing procedure of the synchronization information processing unit 213 when calculating the synchronization information will be described with reference to the flowchart of FIG. This processing is executed for each PID set for the MPEG transport stream (for each PID of up to 8192 programs).
The synchronization information calculation process executed corresponding to one PID will be described as an example.

In a state where the frame synchronization of the MPEG transport stream packet is established by the TS packet synchronization unit 211, in step S51, the PCR
For example, as shown in FIG. 18A, the packet detection unit 212 detects the first PCR packet (first PCR packet) input to the transmission device 201 after the frame synchronization is established at time P1, A PCR packet detection signal is output to synchronous information processing section 213. Synchronous information processing unit 213
Sets in the memory 215 a flag indicating that a PCR packet has been detected.

Next, in step S52, the synchronous information processing section 213 calculates an offset value O. Specifically, first, the synchronous information processing unit 213 sends the first PC
The PCR value E1 (FIG. 18 (C)) of the R packet is acquired, and is set as a reference clock value B (FIG. 18 (B)). At this time, the synchronous information processing unit 213 instructs the counter 214 at the timing when the count value N becomes the reference clock value B as shown in FIG.
In (A)), a command to reset the count value N is issued. next,
The synchronization information processing unit 213 holds the count value N1 (FIG. 18B) supplied from the counter 214 when the PCR packet detection signal is input in step S51 as a reference point, and uses it as the reference clock value B At the same time, the offset value O is calculated by substituting into the following equation (1). Offset value O = PCR value E1 (= reference clock value B) -count value N1 (1)

In step S53, the synchronization information processing section 213 stores the reference clock value B and the offset value O in the memory 215.

Next, in step S54, the synchronous information processing section 213 determines whether or not the PCR packet detection signal has been input from the PCR packet detection section 212 before the count value N from the counter 214 indicates 3240000. However, if it is determined that a PCR packet detection signal has been input by then, the process proceeds to step S55. In the case of this example, as shown in FIGS.
After the count value N of the counter 214 is reset at 2 (time t0), when the counting of 324,000 clocks is completed (at time t1 (FIG. 18A)), the second
Since the second PCR packet is detected, step S55
Proceed to. When no PCR packet is input,
The synchronous information processing unit 213 cancels the flag indicating that the PCR packet has been detected.

In step S55, the synchronization information processing section 213 changes the synchronization byte in the header of the PCR packet (in this case, the second PCR packet) from 47h to -128. The meaning of the processing here will be described later.

In step S54, the counter 214
PCR until the count value N becomes 3240000
If it is determined that no packet has been detected, the synchronous information processing unit 213 sends the count value N to the counter 214 at the timing when the count value N = 3240000.
, And then the process proceeds to step S56.

In step S56, the synchronous information processing section 213 waits until a PCR packet is detected (until a PCR packet detection signal is input). In the case of this example, the counter 214 has 1/3240000
Since the clock of 27 MHz divided into 2 is counted, it takes 0.12 seconds (= 3240000/27000000) to complete the counting of 324,000 clocks.
0) is required. That is, according to the MPEG-2 system, the PCR packet is transmitted at least at a rate of one every 0.1 seconds. Therefore, after the value of the count value N is reset in step S54 (see, for example, FIG. 18). Until the counting of 324,000 clocks is completed (for example, time t1 in (A)) (for example, time t2 in FIG. 18A), one PCR packet (in this case, the third PCR packet in this example) is always required. ) Is detected.

In step S56, when a PCR packet (third PCR packet in this example) is detected, the synchronization information processing section 213 proceeds to step S57, where the synchronization information to be written in the third PCR packet is determined. Is calculated. Specifically, the synchronization information processing unit 213 acquires the PCR value E3 (FIG. 18C) of the third PCR packet that has arrived. Next, the synchronization information processing unit 213
When a PCR packet is detected, the counter value N3 (FIG. 1)
8 (B)). Further, the synchronous information processing unit 213
Substitutes the PCR value E1, the PCR value E3, the count value N3, and the reference clock value B into the following equation (2) to calculate synchronization information.

Synchronization information = ((PCR value E3−PCR value E1) − (count value N3−reference clock value B)) × 3240000 ÷ (count value N3−reference clock value B)) (2)

That is, this synchronization information is obtained by counting the PCR value E3 (the count value of the system clock of the system encoder) and the count value N3 (the network value) while the clock of (count value N3-reference clock value B) is counted. From the difference (α) from the count value of the clock generated by the PLL circuit 217 that is synchronized with the network clock of 202, the third PCR packet is transmitted at the time when the count value N becomes 3240000 (time t1). It represents the difference (β) between the PCR value E and the counter value N (= 3240000) when it arrives at 201.

Next, in step S58, the synchronization information processing section 213 writes the synchronization information calculated in step S57 into the third PCR packet. Specifically, the synchronization information processing unit 213 changes the synchronization byte (47h) in the header of the third PCR packet to the calculated synchronization information.

The synchronous information processing section 213 determines in step S55
Alternatively, after changing the synchronization byte in step S58, the process proceeds to step S59, and 39h is subtracted from the value. As described above, by subtracting the value of 39h, for example, the synchronization byte of the PCR packet not including the synchronization information (the synchronization byte changed to -128 in step S55)
47h. Accordingly, in the receiving apparatus 102, the synchronization of the MPEG transport stream packet is established by the synchronization processing described in the flowchart of FIG. 13 or FIG.

Next, in step S60, the synchronization information processing section 213 adds the synchronization information calculated in step S57 to 320000 (clock), sets it as a new reference clock value B, and calculates in step S52. The synchronization information is added to the offset value O that has been set, and the new offset value O is added to the synchronization information. That is, when the next PCR packet is input, the synchronization information is calculated based on the changed reference clock value B and offset value O.

The above processing is performed by the synchronous information processing unit 213.
Is executed, the reference clock value B (42 bits), the offset value O (42 bits),
And a flag (1 bit) are stored corresponding to the PID of the program.

In the above, as shown in FIG. 18, the time between time t0 and time t1 (FIG. 18A)
The second PCR packet is detected (transmitting device 201
Although the case where the third PCR packet is input during that time as shown in FIG. 19 is similarly processed, for example, as shown in FIG.
That is, in this case, the value of the synchronization byte in the header part of the second PCR packet and the third PCR packet is 47h.
(47h obtained by subtracting 39h from -128) is set, and the fourth PCR packet includes step S5.
The synchronization information calculated in the process in 7 is written to the synchronization byte.

In the above description, (1)
20), the case where the synchronization information is calculated has been described as an example. However, as shown in FIG. 20, in the case where a plurality of programs (two programs) are supported, Each synchronization information is calculated,
Written in a predetermined PCR packet.

FIG. 20 (A) is the same as FIG. 18 (B), and FIG. 20 (B) is a timing chart for explaining the synchronization information creation processing for another program. In the case of FIG. 20B, the offset value O is calculated from the count value N10.
A point separated by 1 is set as the reference clock value B, and the above-described synchronization information creation processing is performed. In this case, the offset value O and the reference clock B are stored in the memory 215 corresponding to the PID of the program.

Next, the amount of synchronization information will be described. According to the MPEG-2 standard, a 27 MHz clock used as a system clock (for example, the system clock of a system encoder or the PLL circuit 21 of the transmission device 201)
+/− 30 ppm (parts per million)
Deviation is allowed. That is, the clock of the system encoder and the frequency of the clock S are (27 MHz
It fluctuates in a range from −810 (= 27 × 10 ⁶ × 30 × 10 ⁻⁶ ) Hz) to (27 MHz + 810 Hz).

That is, as shown in FIG. 21, the difference between the two frequencies is that the frequency of the system clock of the system encoder is 27 MHz + 810 Hz (FIG. 21A), and the frequency of the clock S is 27 MHz-810 Hz (FIG. 21).
(C)), and conversely, as shown in FIG.
If the system clock frequency of the system encoder is 27
MHz-810 Hz (FIG. 22A) and the clock S
Is 27 MHz + 810 Hz (see FIG. 22).
(C)).

Therefore, when the number of clocks counted in one second of each clock in the case of FIG. 21 is obtained, it is 27 × 10 ^{6 in} the case of the assumed true 27 MHz (see FIG. )) And (27 × 10 ⁶ +810) in the case of the system encoder of FIG.
In the case of the clock S of 1 (C), (27 × 10 ⁶ −81
0). Similarly, when the number of clocks counted in one second of each clock in the case of FIG. 22 is obtained, in the case of the system clock of the system encoder of FIG. 22 (A), it becomes (27 × 10 ⁶ -810).
In the case of the clock S of (C), (27 × 10 ⁶ +810)
Individual. That is, when the frequency difference between the two becomes maximum, the difference in the number of clocks counted in one second is 1
620. (27 × 10 ⁶ +810) − (27 × 10 ⁶ −810) =
1620

By the way, the synchronization information described above is also used for the difference between the system clock of the system encoder and the clock S (PC
(The difference in the number of clocks counted between the arrival intervals of the R packet to the transmitting device 201), and the synchronization information is calculated by associating the count value N of the clock S with the time axis of the PCR. ing. That is, the maximum value of the synchronization information also needs to be obtained in accordance with the time axis of the PCR.
In this case, the synchronization information is 0.12 (= 324000/27000
Since 000) seconds, at least one or more are embedded in the MPEG transport stream packet, the synchronization information needs to be able to indicate a maximum of 0.12 second shift (difference in the number of clocks counted in 0.12 seconds). is there. That is, in the state shown in FIG. 21, the synchronization information has the maximum value on the plus side, and its value is 195 as shown below. ((1 + 30ppm) / (1-30ppm) -1) × 27MHz × 0.12s = 195

The above equation shows the period (1 / (27 MHz-810 Hz)) (time) of the clock S in FIG.
(A) is normalized (corresponding to the time axis of PCR) by the system clock cycle (1 / (27 MHz + 810 Hz)) of the system encoder, and the time of the normalized clock S (clock S corresponding to the time axis of PCR) And the time of PCR (1 unit) is calculated, and based on the calculated difference, the difference between the clocks generated in 0.12 seconds is indicated by the number of clocks.

On the other hand, in the state shown in FIG. 22, the synchronization information is
It becomes the maximum on the minus side, and its value is -195, as shown below. ((1-30 ppm) / (1 + 30 ppm) -1) × 27 MHz × 0.12s = −195 That is, from the above, the synchronization information can take a value in the following range. -195 <= synchronization information = <195

Thus, 9 bits are required to represent the synchronization information (although 2 bytes are required if the capacity is secured in byte units), one bit is deleted and 8 bits are deleted. In this case, only an error of +/- 1 clock is generated and the jitter does not exceed the MPEG-2 standard.
The standard of the jitter in the MPEG-2 system is +/- 500 ns,
Converting it to the number of clocks, +/- 13.5 (= +/- 500nsec
× 27MHz) clock. That is, the error of +/- 1 clock is within the range, and eventually, the synchronization information can be represented by 8 bits (1 byte (-128 to 128)).

In the case of this example, the synchronization information is set to one of values from -125 to 125, and the other values are used after giving meanings as shown in FIG. For example,
-128 means that the synchronization information is not set. That is, in step S52, the synchronization byte is -128.
This is to indicate that no synchronization information is written in the TS packet.

[0099] The transmission device -127 indicates a case where a large jitter occurs in the PCR packet, the interval between the input PCR packets is large, and the value of the synchronization information is out of the range of -125 to 125. At 201, it means that some error has occurred. −126, 126,
And 127 are reserve values.

FIG. 24 shows a configuration example of the receiving device 203. The ATM / MPEG converter 301 is connected to the network 20
ATM transmitted from the transmission device 201 transmitted through the
The cell is converted to an MPEG transport stream packet and output to the TS packet synchronization unit 304. The ATM / MPEG conversion unit 301 also controls the 8 KHz synchronized with the network clock of the network 202 based on the received ATM cells.
And outputs it to the PLL circuit 302. Since the PLL circuit 302 has the same configuration (having a phase comparison circuit) as the PLL circuit 217 in FIG. 11, detailed description thereof will be omitted, but the clock supplied from the ATM / MPEG converter 301 is Generate a synchronized 27MHz clock,
Output to the counter 303.

The counter 303 divides the 27 MHz clock from the PLL circuit 302 by 1/3240000, counts it, and outputs the count value M to the PCR rewriting unit 306.

The TS packet synchronizer 304 synchronizes the MPEG transport stream packet from the ATM / MPEG converter 301 in accordance with the processing of the flowchart shown in FIG. 13 or FIG. 14, similarly to the TS packet synchronizer 211 of FIG. Is established and output to the PCR packet detection unit 305.

When frame synchronization is established by the processing shown in the flowchart of FIG. 14, the TS packet synchronizer 304 uses the 47h count unit (FIG. 15). When input, the value of the memory area i of the 47h count unit may not be reset. A specific description is given with reference to FIG.

In a state where the value of the memory area k is set to 2 corresponding to the data of the data 11 and the data 12, 4A which is k bytes away from the head data of the data 13
When any of the values h to 44h is read, the value of the memory area k is not reset to 0 (the value 2 is held). This is because any one of the values 4Ah to 44h is the first data of the PCR packet including the synchronization information, and the frame synchronization is established.
In FIG. 25, xxh is 47h, 4Ah to 44h.
Other data are shown.

The PCR packet detector 305 determines whether the input M
Referring to the header and adaptation field of the PEG transport stream packet, it is determined whether or not the PCR packet condition is set.If it is determined that the PCR packet condition is set, the PCR packet detection signal is rewritten by the PCR. Output to the unit 306.

The PCR rewriting unit 306 performs processing such as reading synchronization information from the input PCR packet (in which synchronization information is written), calculates a new PCR value D, and converts the PCR value D into a PCR packet. Write (rewrite). In addition, PCR
Details of the processing in the rewriting unit 306 will be described later. The memory 307 stores data necessary for the PCR rewriting unit 306 to calculate the PCR value D.

Next, the operation of the PCR rewriting unit 306 when rewriting the PCR value of the PCR packet will be described with reference to the flowchart of FIG. In the state where the MPEG transport stream packets are synchronized in the TS packet synchronization unit 304, in step S71, the PC
The R rewriting unit 306 determines the offset value D. Details of this processing are shown in the flowchart of FIG.
That is, in step S81, the PCR rewriting unit 306
Obtains the PCR value E of the first input PCR packet after the frame synchronization is established, and uses it as the reference clock value B,
An offset value W is calculated by subtracting the reference clock value B from the counter value M from the counter 303 when the PCR packet is input. The PCR rewriting unit 306
The reference clock value B and the offset value W are stored in the memory 30.
7 is stored.

Next, in step S82, the PCR rewriting section 306 sets 1 to the value of the counter j, and sets
At 83, the PCR value E of the next input PCR packet is read, and the difference ΔE from the reference clock value B is calculated. Next, in step S84, the PCR rewriting unit 306
It is determined whether or not E is greater than a predetermined limit value L. If it is not, the process proceeds to step S85, and the value is stored in the memory 307. On the other hand, when it is determined in step S84 that ΔE is larger than the limit value L, the process returns to step S83.

At step S86, the PCR rewriting unit 30
6, it is determined whether or not the value of the counter j has become 7, and when it is determined that the value is not 7, the process proceeds to step S87, the value of the counter j is incremented by 1, and the process returns to step S83. The subsequent processing is performed on the next input PCR packet.

In step S86, when it is determined that the value of the counter j is 7, that is, as shown in FIG. 28, when seven ΔE1 to ΔE7 are calculated and stored in the memory 307, Proceeding to S88, the PCR rewriting unit 306 sets ΔE as shown in Expression (3).
Is divided by 7 to calculate the average value of ΔE,
07. Average value of ΔE = (ΔE1 + ΔE2 + ΔE3 + ΔE4 + ΔE5 + ΔE6 + ΔE7) / 7 (3)

Next, in step S89, the PCR rewriting unit 306 adds ΔE to the offset value W according to the equation (4).
The offset value D is calculated by adding the average value of
8). Offset value D = Average value of offset value W + ΔE (4)

As described above, when the offset value D has been calculated, the processing is terminated, and the flow advances to step S72 in FIG. At the timing when the offset value D is calculated (time t10 in the example of FIG. 29), the PCR rewriting unit 306
A predetermined flag (1 bit) indicating that the offset value D has been calculated is set in the memory 307. In addition, PCR
The rewriting unit 306 instructs the counter 303 to reset the count value M at the same timing.

At step S72, the PCR rewriting unit 30
6 waits until a PCR packet in which the synchronization information is written is input, and when it is input, step S73
After the counter 303 is reset in step S71, it is determined whether or not 320000 clocks have been counted. If it is determined that the count has not been completed, the flow proceeds to step S74. The first here
The second PCR packet is different from the first PCR packet shown in the description of the transmitting device 201.

At step S74, the PCR rewriting unit 30
6 calculates the PCR value D. As will be described with reference to FIG. 29, from the reset of the count value M in step S71 to the completion of the counting for 340000 clocks, the PCR packet in which the synchronization information is written (the first P packet).
CR packet) has been input. Therefore, the PCR rewriting unit 306 acquires the synchronization information of the first arrived PCR packet. Next, the PCR rewriting unit 306 holds the counter value M1 (FIG. 29B) from the counter 303 when the first PCR packet is input. Then, the PCR rewriting unit 306 converts the count value M1, the offset value D, the synchronization information, and the reference clock value B into Expression (5).
To calculate the PCR value D. PCR value D = (count value N1 + offset value D + synchronization information × (count value N1−reference clock B)) / 3240000 (5)

Next, in step S75, the PCR rewriting unit 306 rewrites the PCR value E1 of the first PCR packet with the calculated PCR value D, and outputs it to a decoder (not shown). Thereafter, the process ends.

In step S73, 320000
When it is determined that the count for the clock has been completed, that is, as shown in FIG. 30, after the count for 320000 clocks has been completed, the first PCR packet (the PCR packet in which the synchronization information is written) ) Is input, the process proceeds to step S76, and the reference clock value B is changed. Specifically, the PCR rewriting unit 306
The synchronization information is read from the first PCR packet, 3240000 is added thereto, and the addition result is overwritten in the memory 307 as a new reference clock value B. Thereby, the reference clock value B is changed.

Next, in step S77, the PCR rewriting section 306 changes the offset value D. In particular,
The PCR rewriting unit 306 calculates the offset value D from the memory 307.
, And the synchronization information of the first PCR packet is added thereto, and the addition result is overwritten in the memory 307 as a new offset value D. As a result, the offset value D is changed.

Then, returning to step S74, the PCR rewriting section 306 calculates the PCR value D based on the changed reference clock value B and offset value D.

The PCR rewriting process in the receiving device 203 described above is performed for each program (for example,
Channel). That is, similar processing is performed on a plurality of programs.

As described above, after the synchronization information is written in the transmitting device 201 and transmitted to the receiving device 203 via the network 202, the receiving device 203
Since the PCR is rewritten based on the synchronization information, a plurality of programs (for example, 8192 PIDs)
, The delay fluctuation is suppressed.

Next, another example of the configuration of the receiving apparatus 203 is shown in FIG. Note that, in the figure, the same reference numerals are given to parts corresponding to the case in FIG. That is, the ATM / MPEG converter 301 and the TS packet synchronizer 304
Between them, the adaptive clock unit 51 shown in FIG. 5 is provided. Thereby, the adaptive clock unit 5
The PCR value D is calculated from the MPEG transport stream packet whose fluctuation has been absorbed to some extent by 1.
As a result, in the decoder 400 as shown in FIG. 32, which receives the supply of the MPEG transport stream packets (including the PCR packets) from the receiving device 203, FIG.
As shown in FIG. 3, the breakdown of the VBV buffer 401 can be prevented.

In the decoder 400, the input MPEG
When no delay fluctuation occurs in the transport stream packet, the trajectory of the data occupancy of the VBV buffer 401 is as shown by a dotted line A in FIG. 33, and does not overflow or underflow. However, MP
When the EG transport stream packet arrives with a delay, the trajectory of the data occupation amount may be underflowed as indicated by the solid line B. When the vehicle arrives early, the trajectory may overflow as shown by a solid line C.

FIG. 34 shows a computer 501 functioning as the transmitting device 201 or the receiving device 203 as described above.
FIG. 2 is a block diagram showing a configuration of one embodiment. CPU (C
The CPU 511 is connected to an input / output interface 516 via a bus 515.
511, an input unit 518 including a keyboard, a mouse, and the like from the user via the input / output interface 516;
When a command is input from the ROM, for example, the ROM (Read Only Mem
ory) 512, the hard disk 514, or the magnetic disk 531 and the optical disk 5 mounted on the drive 520.
32, magneto-optical disk 533, or semiconductor memory 5
The program stored in a recording medium such as
It is loaded into an M (Random Access Memory) 513 and executed. Thereby, the various processes described above (for example, FIG.
3, FIG. 14, FIG. 17, FIG. 26, and FIG. 27). Further, the CPU 511
Indicates the processing result, for example, in the input / output interface 5
The data is output to a display unit 517 such as an LCD (Liquid Crystal Display) via the LCD 16 as necessary. The program is stored in the hard disk 514 or the ROM 512 in advance and provided to the user integrally with the computer 501, or provided as package media such as the magnetic disk 531, the optical disk 532, the magneto-optical disk 533, and the semiconductor memory 534. Or can be provided to the hard disk 514 via a communication unit 519 from a satellite, a network, or the like.

In the present specification, the step of describing a program provided by a recording medium may be performed not only in chronological order according to the described order but also in chronological order. This also includes processing executed in parallel or individually.

In this specification, the system is
It represents the entire device composed of a plurality of devices.

[0126]

According to the communication device of the first aspect, the communication method of the fourth aspect, and the program of the recording medium of the fifth aspect, the synchronization incorporated at the head of the packet constituting the stream. Detects unit data placed in the stream that has the same value as the data, and detects the unit data placed in the stream for each packet size from the placement position of the detected unit data in the stream that has the same value as the synchronization data. Is detected, and among the detected unit data, the number of continuously detected unit data having the same value as the synchronization data is counted. When the number of data reaches a predetermined number, the location of one of the detected unit data on the stream is set as the head of the packet, and It is possible to establish synchronization of over-time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a conventional data transmission system.

FIG. 2 is a diagram illustrating PCR.

FIG. 3 is a block diagram illustrating a configuration example of a system decoder 4 of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a PLL circuit 13 of FIG. 3;

FIG. 5 is a block diagram illustrating a configuration example of an adaptive clock unit.

FIG. 6 is a block diagram illustrating a configuration example of a transmission device 61.

FIG. 7 is a block diagram illustrating a configuration example of a receiving device 62.

FIG. 8 is a block diagram illustrating a configuration example of a phase comparator 91.

FIG. 9 is a diagram illustrating a configuration example of a data transmission system to which the present invention has been applied.

FIG. 10 is a diagram illustrating a data structure of an MPEG transport stream packet.

11 is a diagram illustrating a configuration example of a transmission device 201 in FIG.

FIG. 12 is a diagram illustrating a configuration example of a phase comparator 250.

FIG. 13 is a flowchart illustrating a synchronization establishment process.

FIG. 14 is another flowchart illustrating a synchronization establishment process.

FIG. 15 is a diagram showing a 47h counting unit.

FIG. 16 is a diagram illustrating a synchronization establishment process.

FIG. 17 is a flowchart illustrating a synchronization information creation process.

FIG. 18 is a timing chart illustrating a synchronization information creation process.

FIG. 19 is a timing chart illustrating a synchronization information creation process.

FIG. 20 is another timing chart illustrating the synchronization information creation processing.

FIG. 21 is a diagram illustrating a data amount of synchronization information.

FIG. 22 is another diagram illustrating the data amount of synchronization information.

FIG. 23 is a diagram illustrating the meaning of the value of synchronization information.

24 is a diagram illustrating a configuration example of a receiving device 203. FIG.

FIG. 25 is a diagram illustrating a synchronization establishment process.

FIG. 26 is a flowchart illustrating a PCR rewriting process.

FIG. 27 is a flowchart illustrating a calculation process of an offset value.

FIG. 28 is a diagram illustrating a calculation process of an offset value.

FIG. 29 is a timing chart illustrating a PCR rewriting process.

FIG. 30 is another timing chart for explaining the PCR rewriting process.

FIG. 31 is a block diagram illustrating another configuration example of the receiving apparatus 203.

FIG. 32 is a block diagram illustrating a configuration example of a decoder 400.

FIG. 33 is a diagram illustrating a locus of a data amount of a VBV buffer.

FIG. 34 is a block diagram illustrating a configuration example of a computer 501.

[Explanation of symbols]

201 transmitting device, 202 network, 203
Receiver, 211TS packet synchronization unit, 212 PCR
Packet detector, 213 synchronous information processor, 214
Counter, 215 memory, 216 MPEG / ATM
Converter, 217 PLL circuit, 301 ATM / MPEG converter, 302 PLL circuit, 303 counter, 304
TS packet synchronization unit, 305 PCR packet detection unit,
306 PCR rewriting unit, 307 memory

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/08 H04N 7/08 Z 7/081 7/13 Z 7/24 F term (reference) 5C059 KK34 MA00 RA01 RA04 RB01 RB10 RC02 RC03 RC04 RE01 RE04 SS06 UA05 UA09 UA34 UA38 5C063 AA20 AB03 AB07 AC01 AC05 CA11 5K028 AA01 EE03 KK32 MM16 NN01 5K030 HA08 HB02 HB15 KA21 LA15 5K047 AA02 GG56 HB MM BB11

Claims (5)

[Claims] 1. A detecting means for detecting unit data arranged in a stream, which has the same value as synchronous data incorporated at the head of a packet constituting a stream, and the synchronous data detected by the detecting means. From the arrangement position of the unit data having the same value on the stream, for each packet size, the unit data arranged in the stream is detected, and among the detected unit data, the unit data is continuously detected. First counting means for counting the number of the unit data having the same value as the synchronization data; and the number of the unit data having the same value as the continuously detected synchronization data counted by the first counting means. When a predetermined number is reached, the arrangement position of one of the detected unit data on the stream is changed to the previous position. The head of the packet, the communication device characterized by comprising a synchronization establishing means for establishing synchronization of the stream. 2. The method according to claim 2, wherein the synchronization establishing means sets the unit data at the head of the packet on the stream at which synchronization is established by the synchronization establishing means, for each packet size. Detecting the unit data arranged in the stream, and among the detected unit data, further comprises a second counting means for counting the number of the unit data that is continuously detected and has a value different from the synchronization data, The detecting means, when the number of the unit data counted by the second counting means and having a value different from the continuously detected synchronous data becomes a predetermined number, becomes equal to the synchronous data. The communication device according to claim 1, wherein the unit data arranged in the stream is detected again. 3. When a predetermined time stamp is added to the stream, the first counting means determines that the same value as the synchronization data, the same value as the time stamp, and the unit data having the same value as the synchronization data are successive. And detecting the unit data having the same value as the synchronization data continuously when the detection is detected.
The communication device according to claim 1. 4. A detecting step of detecting unit data arranged in the stream and having the same value as synchronous data incorporated at the head of a packet constituting the stream, and detecting the synchronization detected in the processing of the detecting step. From the arrangement position on the stream of the unit data having the same value as the data, for each packet size, the unit data arranged in the stream is detected, and among the detected unit data, the unit data is continuously detected. A counting step of counting the number of the unit data having the same value as the synchronization data, and the number of the unit data having the same value as the continuously detected synchronization data counted in the processing of the counting step, When the predetermined number is reached, the arrangement position of one of the detected unit data on the stream is determined. And the head of the packet, the communication method characterized by comprising a synchronization establishing step of establishing synchronization of said stream. 5. A detecting step of detecting unit data arranged in the stream and having the same value as synchronous data incorporated at the beginning of a packet constituting the stream, and detecting the synchronization detected in the processing of the detecting step. From the arrangement position on the stream of the unit data having the same value as the data, for each packet size, the unit data arranged in the stream is detected, and among the detected unit data, the unit data is continuously detected. A counting step of counting the number of the unit data having the same value as the synchronization data, and the number of the unit data having the same value as the continuously detected synchronization data counted in the processing of the counting step, When the predetermined number is reached, the arrangement position of one of the detected unit data on the stream is determined. And the head of the packet, recording medium on which the program for executing the process which comprises a synchronization establishment step to the computer to establish synchronization of the stream is recorded.