JP2001016267A - Communication equipment and method and medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output an MPEG transport packet to a decoder so that a video buffering verifier VBV buffer is not failed. SOLUTION: A conversion section 81 converts an asynchronous transfer mode ATM cell to an MPEG transport packet, outputs the converted packet to a synchronization section 84, generates a clock synchronously with a clock of a network on the basis of the received ATM cell and outputs the clock to a PLL circuit 82. The PLL circuit 82 generates a 27 MHz clock from the received clock and outputs the generated clock to a counter 83. The counter 83 outputs a count of the clocks to a packet output control section 87. A time stamp read section 85 reads the time stamp added to the packet, outputs a read result (clock value) to a data output control section 87 and outputs a packet to a FIFO 86. A packet output section 87 calculates a count for outputting a packet on the basis of the count from the counter 83 and the count from a time stamp read section 85 and outputs the packet stored in the FIFO 86 in the timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus and method, and a medium, and more particularly to an ATM (Asynchronous Transf
The present invention relates to a communication device and method, and a medium that can receive audio data and video data digitized using a communication technology or the like.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration example of a conventional data transmission system. It is assumed that the network 3 to which each of the encoding side and the decoding side is connected uses a satellite, similarly to the transmission method in digital CS broadcasting. That is, it is assumed that data transmitted via the network 3 has a delay at a constant interval.

An encoder 1 converts video data and audio data as data to be transmitted, for example, into MPEG data.
Encode according to the -2 method and output to the system encoder 2. The system encoder 2 packetizes and multiplexes the input video data and audio data to generate an MPEG transport packet,
A PCR (Program Clock Reference) is added and transmitted over the network 3. As shown in FIG. 2, the PCR represents the count value of the system clock on the encode side (system encoder 2), which is counted at the encode timing on the encode side (encoder 1). This system clock is set to 27 MHz in the case of the MPEG-2 system.

Returning to FIG. 1, data transmitted via the network 3 arrives at the decoding side and is input to the system decoder 4. Note that the data transmitted via the network 3 has a delay of a certain interval, so that the PCR arrives at the decoding side at the same interval as that transmitted from the encoding side.

[0005] As shown in FIG. 3, the system decoder 4 includes a system decoding unit 11, a PCR extraction circuit 12, and a PLL circuit 13. The system decoding unit 11 depacketizes the input packetized audio data and video data, and outputs the resulting audio stream and video stream to the decoder 5.

[0006] As shown in FIG.
The PCR included in the PEG transport packet is extracted and output to the PLL circuit 13. The PLL circuit 13 generates a 27 MHz system clock using the input PCR and outputs the generated system clock to the decoder 5.

[0007] The PLL circuit 13 is configured, for example, as shown in FIG. The subtracter 21 receives the PCR extracted by the PCR extraction circuit 12 and the count value input from the counter 24 (the count value of the clock output from the D / A converter / VCO 23). Subtractor 2
1 calculates the difference between the PCR and the count value, and outputs the difference to a low-pass filter (hereinafter abbreviated as LPF) 22. LPF22
Smoothes the input operation result from the subtractor 21,
/ A converter / VCO (voltage controlled oscillator) 23. The D / A converter / VCO 23 converts the digital signal input from the LPF 22 into an analog signal, and uses the analog signal as a control voltage to generate a clock having a frequency corresponding to the control voltage. This clock is used as a system clock on the decoding side (system decoder 4), is supplied to the decoder 5, and is input to the counter 24.

The counter 24 is a D / A converter / VCO
23, and counts the count value.
The signal is supplied to the subtractor 21 as a signal representing the phase of the frequency of the system clock at that time. That is, this
In the PLL circuit 13, the speed of the system clock is increased or decreased so that the difference between the PCR added to the MPEG transport packet and transmitted and the count value of the own system clock disappears. I do.

Returning to FIG. 1, the decoder 5 decodes the streams of audio data and video data supplied from the system decoder 11 of the system decoder 4 based on the system clock input from the PLL circuit 13 of the system decoder 4. I do.

[0010] As in the case of this example, when the data is delayed at a fixed interval, the PCR transmitted from the encoding side arrives at the decoding side at the same interval. Thus, the system clock on the decoding side is generated (adjusted) so as to be synchronized with the system clock on the encoding side. As a result, the data is properly reproduced. However, if the network 3 has an ATM (As
As in the case of an asynchronous transfer mode network, when the data has a delay (hereinafter, referred to as delay fluctuation) in the range of 1 ms to 2 ms (hereinafter referred to as delay fluctuation) instead of the delay at a fixed interval, the above-described conventional data transmission is performed. The system has a problem that the delay fluctuation is not absorbed and the data is not properly reproduced.

[0011]

Therefore, various methods for reducing delay fluctuation have been proposed, and by using these methods, delay fluctuation can be reduced to some extent. However, the irregularity of the arrival interval (early or late arrival) of the MPEG transport packet itself to the decoder side has not been eliminated, and as a result, the VBV (Video Buffering Verifier) buffer of the decoder is not shown in FIG. As shown, there was a problem of bankruptcy.

For example, when the arrival of an MPEG transport packet is delayed, the trajectory of the data occupancy of the VBV buffer may be underflowed as shown by a solid line A. In this case, the trajectory may overflow as shown by the solid line B.

The present invention has been made in view of such a problem, and it is an object of the present invention to reduce delay fluctuation and prevent a VBV buffer from breaking down.

[0014]

According to a first aspect of the present invention, there is provided a communication apparatus comprising: a generating unit for generating a clock synchronized with a network clock; a counting unit for counting a clock generated by the generating unit; It is characterized by comprising an adding means for adding the count value counted by the counting means to the data, and a transmitting means for transmitting the data to which the count value has been added by the adding means to the receiving device.

According to a second aspect of the present invention, there is provided a communication method comprising: a generating step of generating a clock synchronized with a network clock; a counting step of counting clocks generated in the processing of the generating step;
The additional step of adding the count value counted in the processing of the counting step, and the processing of the additional step,
Transmitting the data to which the count value has been added to the receiving device.

The medium according to claim 3, wherein the generating step generates a clock synchronized with the network clock.
A counting step for counting the clock generated in the generating step, an adding step of adding the count value counted in the counting step to the input data, and a counting value added by the adding step processing. Transmitting the received data to the receiving device.

In the communication apparatus according to the first aspect, the communication method according to the second aspect, and the medium according to the third aspect, a clock synchronized with a network clock is generated, and the generated clock is counted. The counted value is added to the input data, and the data with the added count value is transmitted to the receiving device.

A communication device according to a fourth aspect of the present invention includes a generating unit for generating a clock synchronized with a network clock;
Counting means for counting the clock generated by the generating means; receiving means for receiving the time-stamped data transmitted from the transmitting device; and a time stamp added to the data received by the receiving means. It is provided with reading means for reading, and determining means for determining timing for outputting data based on the time stamp read by the reading means and the count value counted by the counting means.

According to a fifth aspect of the present invention, there is provided a communication method, comprising: a generating step of generating a clock synchronized with a network clock; a counting step of counting clocks generated in the processing of the generating step; A receiving step of receiving data with a time stamp added thereto, a reading step of reading the time stamp added to the data received in the processing of the receiving step, a time stamp read in the processing of the reading step, and a counting step. And determining a timing for outputting data based on the count value counted in the processing.

A medium according to claim 6, wherein the generating step generates a clock synchronized with the network clock.
A counting step of counting clocks generated in the processing of the generating step;
From the data to which the time stamp has been added, determine the reading step for reading the time stamp, the time stamp read in the reading step processing, and the timing for outputting data based on the count value counted in the counting step processing. And a determining step.

[0021]

FIG. 6 shows a configuration example of a data transmission system to which the present invention is applied. In this system, an MPEG transport stream conforming to the MPEG-2 system is converted into ATM cells and transmitted and received via a network 52 which is an ATM network. That is,
Data transmitted via the network 52 has a delay fluctuation.

As shown in FIG. 7, an MPEG transport packet of 188 bytes including a header portion in which a synchronization byte is set is input to the transmission device 51. This MPEG
A plurality of programs respectively encoded are multiplexed in the transport packet.

The transmitting device 51 sets a predetermined time stamp for each of the inputted MPEG transport packets, converts the packets into ATM cells, and transmits them to the network 52.

The receiving device 53 receives the ATM cells transmitted via the network 52, converts the received ATM cells into MPEG transport packets, and, at the timing based on the time stamps set in the MPEG transport packets, decodes them at a decoder (not shown). Nu).

FIG. 8 shows a configuration example of the transmission device 51. An MPEG transport packet (FIG. 7) supplied to the transmission device 51 is input to an MPEG transport packet synchronizer (hereinafter, abbreviated as a TS packet synchronizer) 61. The TS packet synchronization unit 61 refers to the synchronization byte of the input MPEG transport packet, establishes the synchronization of the MPEG transport packet, and outputs it to the time stamp addition unit 62.

The time stamp adding unit 62 includes, in addition to the MPEG transport packet from the TS packet synchronizing unit 61,
The count value (2-byte data) from the counter 63 is input. The time stamp adding unit 62
Will be described later, the time stamp adding unit 6
2 is the count value (2) from the counter 63 when the MPEG transport packet packet is input.
The byte data) is set as a time stamp as shown in FIG. 9 and output to the MPEG / ATM conversion unit 64.

The MPEG / ATM conversion section 64 converts the MPEG transport packet from the time stamp addition section 62 into an ATM cell and transmits the ATM cell to the network 52. MPEG / ATM
The conversion unit 64 also receives an ATM cell sequentially transmitted from the network 52, generates an 8 KHz clock synchronized with the network 52 based on the received ATM cell, and outputs the clock to the PLL circuit 65. Figure 10
A phase comparator 70 having the configuration shown in FIG. The VCO 71 generates 27 MHZ of a predetermined phase based on the signal supplied from the phase comparison unit 72, and outputs it to the counter 63 and to the frequency divider 73. The frequency divider 73 divides the 27 MHz clock input from the VCO 71 by 1/3375 to generate an 8 KHz clock, and outputs the 8 KHz clock to the phase comparator 72. The phase comparison unit 72 determines whether the MP
The phase of the 8 KHz clock from the EG / ATM converter 64;
Compare the phase of the 8 KHz clock from divider 73,
The comparison result is output to the VCO 71.

Returning to FIG. 8, the counter 63 is a PLL circuit 6
The clock of 27 MHz from 5 is counted, and the count value (2-byte data) is output to the time stamp unit 62. That is, this counter 63
Counts a clock synchronized with the clock of the network 52.

FIG. 11 shows a configuration example of the receiving device 53. The ATM / MPEG converter 81 converts the ATM cell transmitted from the transmitting device 51 via the network 52 into an MPE.
The packet is converted into a G transport packet and output to the TS packet synchronization unit 84. The ATM / MPEG converter 81 also generates an 8 KHz clock synchronized with the clock of the network 52 based on the received ATM cells, and outputs the clock to the PLL circuit 82. The PLL circuit 82 has a configuration similar to that of the PLL circuit 65 in FIG. 8 (having a phase comparison circuit having a configuration similar to that of the phase comparison circuit 70). , Based on the clock supplied from the ATM / MPEG converter 81, and outputs the clock to the counter 83.

The counter 83 receives the 27 from the PLL circuit 82.
The clock of MHZ is counted, and the count value (two-byte data) is output to the packet output control unit 37.

The TS packet synchronizer 84 refers to the synchronization byte set in the MPEG transport packet from the ATM / MPEG converter 81, establishes its synchronization, and outputs it to the time stamp reader 85.

The time stamp reading section 85 reads the time stamp (FIG. 9) added to the MPEG transport packet from the TS packet synchronizing section 84 and outputs the read result (clock value) to the packet output control section 87. . The time stamp reading unit 85 also reads the MPEG transport packet from which the time stamp has been read,
Output to the FIFO 86. Note that, as shown in FIG. 7, the MPEG transport packet from which the time stamp has been read is not added with the time stamp (removed).

The FIFO 86 includes a time stamp reading unit 8
5 stores the MPEG transport packet inputted from 5 and is controlled by the packet output control section 87 to output the stored MPEG transport packet to a decoder (not shown).

The packet output control unit 87 has a counter 83
A timing (count value) for outputting an MPEG transport packet is calculated from the count value input from the MFP and the count value input from the time stamp reading unit 85, and the MPEG transport stored in the FIFO 86 is calculated at the calculated timing. FI so that port packets are output
Controls FO86.

Next, the operation of the transmitting device 51 when performing the time stamp adding process will be described.

The counter 63 counts a 27 MHz clock (clock synchronized with the clock of the network 52) from the PLL circuit 65 and outputs the count value to the time stamp adding unit 62, as shown in FIG. . In this example, since the count value is 2-byte data (0 to 65536), when the count value is the maximum (when 65536), it is approximately 2.
4 (<65536/27 (MHz)) ms.

The time stamp adding section 62 is provided in FIG.
As shown in (B), the TS packet synchronization unit 61 sends the first
The second MPEG transport packet (in FIG. 12 (B),
When a TS packet 1 is input, the count value (FIG. 1) supplied from the counter 63 at that time is input.
In the example of No. 2, “0”) is added to the TS packet 1 as the time stamp 1.

The time stamp adding unit 62 adds a time stamp to the MPEG transport packets that are sequentially input after the TS packet 1, as in the case of the TS packet 1. In the case of the example shown in FIG.
The time stamp 2 (= “101”) is added to the TS packet 3, and the time stamp 3 (= “501”) is added to the TS packet 3.

As described above, a time stamp is added to each MPEG transport packet.

Next, the receiving device 5 for receiving the MPEG transport packet to which the time stamp is added as described above.
Operation 3 will be described.

The counter 83 of the receiving device 53 has a
As shown in (A), the clock of 27 MHz (clock synchronized with the clock of the network 52) from the PLL circuit 82 is counted, and the count value is output to the packet output control unit 87.

The time stamp reading unit 85 is a
As shown in (B), a TS packet 1 to which a time stamp 1 (= "0") is added is sent from the TS packet synchronization unit 84.
When (the first MPEG transport packet) is input, the time stamp 1 is read and output to the packet output control unit 87. The time stamp reading unit 85
Read TS packet 1 that has read time stamp 1 into FIFO 86
Output to The TS packet 1 is stored in the FIFO 86.

The time stamp reading section 85 reads the time stamp 2 (= “10”) from the MPEG transport packet input following the TS packet 1, in the case of FIG.
1 ") and time stamp 3 (=" 501 ") and output them to the packet output control unit 87. The time stamp reading unit 85 also reads the TS packets 2 and 3 from which the time stamps 2 and 3 have been read. Is output to the FIFO 86. The TS packet 2 and the TS
The packet 3 is stored in the FIFO 86.

On the other hand, when the time stamp 1 is supplied from the time stamp reading unit 85, the packet output control unit 87
The count value 1 (“497” in the example of FIG. 13A) input from 3 is stored, and then the FIFO 86 is controlled to output the TS packet 1 to the decoder.

When the time stamp 2 is supplied from the time stamp reading unit 85, the packet output control unit 87 receives the time stamp 2 (= “101”) and the previously stored time stamp 1 (= “0”). ) (= “10
1 ″) is calculated. The packet output control unit 87 further calculates
The calculation result (= “101”) and the previously stored count value 1 (= “497”) are added to determine the timing (count value 2 (= “598”) at which the TS packet 2 is output.

Thus, the packet output control section 87
Determines the count value 2 to output the TS packet 2 and controls the FIFO 86 to output the stored TS packet 2 to the decoder when the count value from the counter 83 reaches that value.

As described above, even when a time stamp (eg, time stamp 3) after the time stamp 2 is input, the packet output control unit 87 outputs the TS packet (eg, TS packet) to which the time stamp has been added. A count value to output the packet 3) is calculated, the FIFO 86 is controlled, and at the timing when the count value from the counter 83 becomes the same value, the TS packet (TS packet 3)
Is output to the decoder.

As described above, in the transmitting device 51, the clock synchronized with the clock of the network 52 is counted, and the count value when the MPEG transport packet is output is added as a time stamp.
Then, in the receiving device 53, the added time stamp is read, and a count value to be output is calculated based on the read time stamp, and the count value of the clock synchronized with the clock of the network 52 becomes the same value. When the MPEG transport packet is output, the MPEG transport packet is prevented from arriving at the decoder early or late,
As a result, the breakdown of the VBV buffer of the decoder is prevented.

The series of processes described above can be executed by hardware, but can also be executed by software. When a series of processing is executed by software, a program constituting the software is installed in a computer incorporated in the transmitting device 51 and the receiving device 53 as dedicated hardware, or various programs are installed. As a result, it is installed in, for example, a general-purpose personal computer capable of executing various functions.

Next, referring to FIG. 14, a program for executing the above-described series of processing is installed in a computer, and a computer used for making the computer executable is a general-purpose personal computer. The following is an example of the case.

As shown in FIG. 14A, the program is stored in a hard disk 102 or a semiconductor memory 1 as a recording medium built in the personal computer 101.
03 in advance.

Alternatively, the program is executed as shown in FIG.
As shown in (B), the floppy disk 111 and the CD-R
OM (Compact Disk-Read Only Memory) 112, MO (Mag
neto-Optical) Disc 113, DVD (Digital Versatile)
Disk) 114, magnetic disk 115, semiconductor memory 11
6, etc., temporarily or permanently stored in a recording medium,
It can be provided as package software.

Further, as shown in FIG. 14C, the program is wirelessly transferred from the download site 121 to the personal computer 101 via the artificial satellite 122 for digital satellite broadcasting, a local area network, the Internet, or the like. Network 131
, And can be transferred to the personal computer 101 by wire, and stored in the built-in hard disk 102 or the like in the personal computer 101.

The medium in the present specification means a broad concept including all these media.

As shown in FIG. 15, for example, the personal computer 101 has a CPU (Central Processing Unit).
it) 142 built-in. The CPU 142 has a bus 141
An input / output interface 145 is connected via the input / output interface 145. When a user inputs a command via the input / output interface 145 from an input unit 147 including a keyboard, a mouse, and the like, the CPU 142 ROM (Read) corresponding to the semiconductor memory 103 of FIG.
(Only Memory) 143 is executed. Alternatively, the CPU 142 may transfer the program stored in the hard disk 102 in advance, the satellite 122 or the network 131 to the communication unit 148.
And the program installed on the hard disk 102 or the floppy disk 111, CD-ROM 112, MO
Disk 113, DVD 114, or magnetic disk 1
15 and installed in the hard disk 102 are stored in a RAM (Random Access Memory).
y) Load to 144 and execute. Further, the CPU 142
Sends the processing result to, for example, the input / output interface 1
An output is provided to a display unit 146, such as an LCD (Liquid Crystal Display), as necessary, via the LCD 45.

In this specification, steps for describing a program provided by a medium are not limited to processing performed in a time-series manner in the described order, but are not necessarily performed in a time-series manner. It also includes processes that are executed individually or individually.

In this specification, the system is
It represents the entire device composed of a plurality of devices.

[0058]

According to the communication apparatus of the first aspect, the communication method of the second aspect, and the medium of the third aspect, a clock synchronized with a network clock is generated, and the generated clock is counted. Then, the count value is added to the input data, and the data is transmitted to the receiving device. Therefore, for example, the breakdown of the VBV buffer of the decoder can be prevented.

According to the communication device of the fourth aspect, the communication method of the fifth aspect, and the medium of the sixth aspect,
Generates a clock synchronized with the network clock, counts the generated clock, reads a time stamp added to data transmitted from the transmission device, and outputs data based on the read time stamp and the count value. I decided to determine the timing,
For example, the breakdown of the VBV buffer of the decoder can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a conventional data transmission system.

FIG. 2 is a diagram illustrating PCR.

FIG. 3 is a block diagram illustrating a configuration example of a system decoder 4 of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a PLL circuit 13 of FIG. 3;

FIG. 5 is a diagram showing a transition of a data occupancy of a VBV buffer.

FIG. 6 is a diagram showing a configuration example of a data transmission system to which the present invention is applied.

FIG. 7 is a diagram illustrating a data structure of an MPEG transport packet.

8 is a diagram illustrating a configuration example of a transmission device 51 in FIG.

FIG. 9 is a diagram showing a data structure of an MPEG transport packet to which a time stamp has been added.

FIG. 10 is a diagram illustrating a configuration example of a phase comparator of FIG. 8;

11 is a diagram illustrating a configuration example of a receiving device 53 in FIG. 6;

FIG. 12 is a diagram illustrating an operation of the transmission device 51.

FIG. 13 is a diagram illustrating an operation of the receiving device 53.

FIG. 14 is a diagram showing a medium.

15 is a diagram illustrating a configuration example of a personal computer 101 in FIG.

[Explanation of symbols]

51 transmitting device, 52 network, 53 receiving device, 61 TS packet synchronizing unit, 62 time stamp adding unit, 63 counter, 64 MPEG / ATM converting unit, 65 PLL circuit, 70 phase comparing unit, 81 A
TM / MPEG conversion unit, 82 PLL circuit, 83 counter, 84 TS packet synchronization unit, 85 time stamp reading unit, 86 FIFO, 87 packet output control unit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroaki Seto 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Eisaburo Itakura 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F term (reference) 5K028 AA15 EE03 KK01 KK35 MM05 NN57 SS24 5K030 GA12 HB01 HB02 HB15 HB19 HB29 JA01 JA06 KA03 KA21 LA15 LE06 5K047 AA05 BB16 DD01 DD02 GG02 HH54 MM24 MM46 MM46 MM46 MM46 MM46 MM46 MM46 MM46 MM46

Claims (6)

[Claims] 1. A communication device connected to a receiving device via a network that transmits data according to a network clock, comprising: a generating unit that generates a clock synchronized with the network clock; and a clock that is generated by the generating unit. Counting means for counting; adding means for adding the count value counted by the counting means to the input data; transmitting the data to which the count value has been added by the adding means to the receiving device A communication device comprising: a transmission unit. 2. A communication method for a communication device connected to a receiving device via a network for transmitting data according to a network clock, wherein: a generating step of generating a clock synchronized with the network clock; A counting step of counting the received clock; an adding step of adding the count value counted in the processing of the counting step to input data; and the processing of the adding step adds the count value. Transmitting the data to the receiving device. 3. A communication processing program for transmitting data to a receiving device connected via a network that transmits data according to a network clock, comprising: a generating step of generating a clock synchronized with the network clock. A counting step of counting the clock generated in the processing of the generating step, an adding step of adding the count value counted in the processing of the counting step to input data, and a processing of the adding step. A transmission step of transmitting the data to which the count value has been added to the reception device, the program causing a computer to execute a program. 4. A communication device connected to a transmission device via a network for transmitting data according to a network clock, wherein: a generation unit for generating a clock synchronized with the network clock; and a clock generated by the generation unit. Counting means for counting; receiving means for receiving data to which a time stamp is added, transmitted from the transmitting device; reading means for reading the time stamp added to the data received by the receiving means; A communication device comprising: a time stamp read by the reading means; and a determining means for determining a timing of outputting the data based on a count value counted by the counting means. 5. A communication method for a communication device connected to a transmitting device via a network that transmits data according to a network clock, wherein: a generating step of generating a clock synchronized with the network clock; A counting step of counting the clock that has been performed; a receiving step of receiving data to which a time stamp has been added, which has been transmitted from the transmitting device; and the adding to the data received in the processing of the receiving step. A reading step of reading a time stamp; a determining step of determining a timing of outputting the data based on the time stamp read in the processing of the reading step and a count value counted in the processing of the counting step. Features include Communication method for. 6. A communication processing program for receiving data from a transmitting device connected via a network that transmits data in accordance with a network clock, wherein the program generates a clock synchronized with the network clock. A counting step of counting the clock generated in the processing of the generating step; a reading step of reading the time stamp from data to which a time stamp is added, transmitted from the transmitting device; and a reading step. Executing the program on a computer, comprising: a determination step of determining a timing of outputting the data based on the time stamp read in the processing of step (b) and the count value counted in the processing of the counting step. Medium .