KR100238410B1 - Variable bit rate data management device and method contained dvdp - Google Patents

Abstract

The present invention relates to a video / audio signal processing apparatus using an optical disc such as a compact disc (CD), a digital video disc play (DVDP), and the like, and buffers data output from the signal processor 40. It receives the input from the unit 50 and stores it in the memory unit 60 and outputs data only when desired by the system unit 80, and reads data from the disk when the capacity of the memory unit 60 is saturated through the block management unit Stop and transfer the data stored in the memory unit 60 to the cyste unit 80. If the capacity of the memory unit 60 is not saturated, the data is read from the disk again and transmitted from the signal processor 40 to the buffer unit 50. It is effective to output the stable data to the system unit 80 by receiving the input from the system unit 80, and does not lose the data read from the disk.

Description

DVDP with Variable Bit Rate Data Management Apparatus and Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video / audio signal processing apparatus using an optical disc such as a CD (Compact Disc), a DVDP (Digital Video Disc Play), and more particularly, a system for processing data read from a disc in a signal processing unit. The buffer control and block management are used to transfer the data to the system (MPA-2) so that the data transmission can be input only when the system unit wants it. When the value is lower than the set value, the data can be read from the disk again.

However, in processing a moving picture using a conventional optical disk, the data transmitted by processing the input data is not received at a constant speed by the system unit using a variable bit rate method, so that the input data efficiency is lowered and the system is stabilized. There was a problem.

An object of the present invention is to solve the above-mentioned conventional problems, in particular, the data output from the signal processing unit is received from the buffer control unit and stored in the memory, the system unit outputs the data only when desired, the buffer control unit If the memory capacity of the memory is saturated, the operation of reading data from the disk is stopped through the block management unit, and the data stored in the memory is transferred to the system. If the memory capacity is not saturated, the data is read again from the disk and the signal processor The present invention provides a "variable bit rate data management apparatus and method for DVDP" which is inputted from the buffer control unit and outputted to the system unit.

In order to achieve the above object, the present invention "variable bit rate data management apparatus for DVDP" includes a spindle motor for driving disk rotation; A pickup device for reading data of the disc; A control unit for controlling the speed of the spindle motor and controlling the pickup device to read data at the same position by a jump signal; A signal processor which receives the data transmitted from the pickup device, converts the analog signal into a digital signal, corrects the error, outputs the error, and outputs the number of the sector currently being read; Receives the data 1 signal, the clock 1 signal, the sector signal and the block signal output from the signal processor and stores them in a memory unit to be described later, and outputs data by the data request signal output from the system unit described later. A buffer unit for outputting a full-1 signal to stop reading data of the disk when the capacity is greater than or equal to the set value, and outputting a signal for reading data of the disk when the memory capacity is less than or equal to the set value; A memory unit which receives the address signal, the data 2 signal, and the store / read signal output from the buffer unit and outputs data by the data request signal output from the system unit; A block manager which receives the full-1 signal output from the buffer unit and includes the block in a block that is a data processing unit and outputs a full-2 signal; A system unit for converting a video / audio signal into a video / audio signal based on the data 3 signal and the clock 3 signal output from the buffer unit; The signal processing unit receives a full-2 signal output from the block management unit and outputs a hold signal for blocking an error correction operation by converting data from an analog signal into a digital signal, and jumping to the control unit. Outputs a control signal to control the speed of the spindle motor by controlling the speed of the spindle motor, reads data from the disk at the same position, outputs a setting signal to set the memory of the buffer, and pulls 2 -2) If no signal is output, it is characterized by including the CPU to drive all the operation again.

The buffer unit may include: a buffer controller configured to receive a clock 1 signal output from a signal processor and a data request signal output from a system unit; An address generator which receives the clock 1 signal output from the signal processor and the clock 3 signal output from the buffer controller; A switching unit configured to receive a data 1 signal output from a signal processor and a store / read signal output from the buffer controller; And a comparator configured to receive the clock 1 signal output from the signal processor and the clock 3 signal output from the buffer controller.

The buffer controller may be configured to set the memory to store data when clock 1 is input from the signal processor, and to output the clock 3 signal when the data request signal is input from the system to the memory. To control.

The address generator may include a first address generator configured to receive the clock 1 signal output from the signal processor and to generate an A1 signal which is a memory storage address; A second address generator configured to receive the clock 3 signal output from the buffer controller to generate an A2 signal which is a memory read address; It consists of a multiplexer that receives the A1 / A2 signal and outputs the A1 signal to the memory when the A2 signal is stored when it is read.

The switching unit may include: a first switch configured to switch the data 2 signal of the memory to the data 3 signal of the system unit when the signal output from the buffer controller is a read signal; When the input signal is a storage signal, a second switch is configured to switch the data 1 signal of the signal processor to be input to the data 2 of the memory.

The comparison unit may further include: a counter for counting how many bytes (BYTE) are currently recorded in the memory by increasing memory storage when the clock 1 signal output from the signal processing unit is input and decreasing the memory read signal when the clock 3 signal is input. Wow; A register unit which stores a value set by the CPU; It consists of a comparator that compares the value set by the register with the value counted by the counter and outputs a full-1 signal when the value counted by the counter is large.

On the other hand, "DVDP including a variable bit rate data management method" of the present invention includes a data reading step (S1) for outputting data in accordance with the request signal of the system unit; A memory capacity saturation step (S2) of outputting if the memory capacity is equal to or larger than a set value or returning to the memory reading step; A block ending step (S3) of receiving the output signal and processing the block of data and then returning to the data reading step; A sector number storage step (S4) in which the CPU at which the block is terminated receives the memory saturation signal and stores the number of saturated sectors; An inner circumferential movement step (S5) in which the pickup device is moved inward when the sector number is output; A saturation state determination step (S6) of outputting when the memory saturation state is released and maintaining the current position of the pickup device if the memory saturation state is not released; A sector number detecting step (S7) of reading the sector number when the saturation state is released; The method is characterized in that it comprises a saturation sector number detection step S8 which returns to the data reading step if the sector number where the saturation state first starts is found and returns to the sector number detection step.

The present invention " DVDP including a variable bit rate data management apparatus and method " receives data output from a signal processor from a buffer controller, stores the data in a memory, outputs data only when desired by the system controller, and saturates the memory capacity of the buffer controller. In the state, stop the operation of reading the data from the disk through the block management unit and transfer the data stored in the memory to the system. If the memory capacity is not saturated, read the data from the disk and send it from the signal processing unit. It receives the output to the system unit, outputs stable data to the system unit, and does not lose the data read from the disk.

1 is a block diagram showing the configuration of a "DVDP including a variable bit rate data management apparatus" according to an embodiment of the present invention;

2 is a control flowchart showing "DVDP including a variable bit rate data management method" according to an embodiment of the present invention;

3 is a detailed view illustrating the buffer unit of FIG. 1 in detail;

* Explanation of symbols for main parts of the drawings

10: spindle motor 20: pickup device

30: control unit 40: signal processing unit

50: buffer part 60: memory part

70: block management unit 80: system unit

90: CPU 51: buffer control unit

52: address generator 52a: first address generator

52b: second address generator 52c: multiplexer

53: switching unit 53a: first switch

53b: second switch 54: comparison unit

54a: counter 54b: register

54c: comparator

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment according to the technical concept of the present invention "DVDP including a variable bit rate data management apparatus and method" will be described in detail.

EXAMPLE

First, the input terminal of the spindle motor 10 and the input terminal of the pickup device 20 are connected to the output terminal of the control unit 30, the output terminal of the pickup device 20, and the input terminal of the signal processing unit 40, and the signal processing unit 40 is connected. Is connected to an output terminal of the buffer unit 50, an output terminal of the buffer unit 50, an input terminal of the memory unit 60, an input terminal of the block manager 70, and an input terminal of the system unit 80, The output terminal of the controller 90, the input terminal of the buffer unit 50, the input terminal of the signal processing unit 40, the input terminal of the control unit 40, and the output terminal of the spindle motor 10 are connected to the input / output terminal of the CPU 90.

Hereinafter, the operation of the apparatus having the above-described configuration will be described with reference to the block diagram shown in FIG.

When the disk is rotated by the drive of the spindle motor 10, the pickup device 20 reads the data stored in the disk and outputs the data to the signal processing unit 40 to output the input signal to the signal processing unit 40. After converting an analog signal into a digital signal to correct an error, and outputting a data 1 signal, a clock 1 signal, a sector signal, and a block signal, the buffer control unit 51 in the buffer unit 50 receives the store / read signal and Outputs the clock 3 signal and the address generator 52 receives the clock 1 signal from the first address generator 52a to generate the A1 signal, which is a memory storage address, and receives the clock 3 signal from the second address generator 52b. When the A2 signal, which is the read address, is generated and output to the multiplexer 52c, the multiplexer 52c receives the A1 / A2 signal and reads the A1 signal into the memory unit 60 as an address signal when storing the A2 signal. The.

In addition, the switching unit 53 in the buffer unit 50 outputs the data 2 signal of the memory as the data 3 signal of the system unit 80 when the first switch input signal is a read signal, and the second switch When the input signal is a storage signal, the data 1 signal of the signal processing unit 40 is input to the data 2 of the memory, and the comparator 54 in the buffer unit 50 sets the value set in the CPU 90 and the counter 54a. Compares the value counted by the counter 54a and outputs a full-1 signal when the value counted by the counter 54a is large, and the memory unit 60 outputs an address signal, a data 2 signal, and a store / read signal output from the buffer unit 50. Receives the data request signal output from the system unit 80 from the buffer control unit 51 of the buffer unit 50 and outputs to the memory unit 60 outputs the data, the system unit 80 inputs When data is converted to video / audio signal by 3 data and clock 3 signal When the capacity of the memory unit 60 is greater than or equal to the set value, a full-1 signal is output, and the block manager 70 outputs a full-2 signal including the full-1 signal to the block, and the CPU controls the block management unit ( 70) receives the full-2 signal output from the signal processing unit 40 converts the data from the analog signal to the digital signal to output a hold signal to block the error correction operation and outputs a jump signal to the control unit spindle motor Outputting a control signal for controlling the speed of 10 and controlling the operation of reading data from the disk at the same position, outputting a setting signal for setting the capacity of the memory unit 60, and the block management unit 70; If 2 signals are not output, it operates all the operations again.

On the other hand, the "DVDP including the variable bit rate data management method" of the present invention reads the data by the request signal of the system unit (first step) and outputs when the memory capacity is equal to or larger than the set value, or returns to the memory read step (the first step). Step 2) If the output signal is received and processed, the block of data is transmitted. If not, the process returns to the data reading step (Step 3). If the block is processed, the CPU receives the memory saturation signal and stores the number of saturated sectors. Step 4) When the sector number is output, the pickup device moves to the inner circumference (Step 5). If the memory saturation is released, the pickup device outputs it. If not, the pickup device keeps the current position (Step 6) and the saturation state is released. Reads the sector signal (step 7), finds the sector number where the saturation first starts, and returns to the data reading step, or returns to the sector number detection step. (The eighth step)

As described above, the present invention "DVDP including an apparatus and method for managing a variable bit rate data", in particular, receives data output from a signal processor from a buffer controller, stores the data in a memory, and outputs the data only when desired by the system controller. If the memory capacity of the buffer controller is saturated, the operation of reading data from the disk is stopped through the block management unit, and the data stored in the memory is transferred to the system. If the memory capacity is not saturated, the data is read again from the disk and the signal processor In this case, it receives the input from the buffer control unit and outputs it to the system unit so that the stable data is output to the system unit and the data read from the disk is not lost.

Claims (7)

A spindle motor for driving disk rotation; A pickup device for reading data of the disc; A control unit for controlling the speed of the spindle motor and controlling the pickup device to read data at the same position by a jump signal; A signal processing unit which receives data transmitted from the pickup device, converts an analog signal into a digital signal, corrects and outputs the error, and outputs a number of a sector currently read; It receives the data 1 signal, clock 1 signal, sector signal and block signal output from the signal processor and stores them in the memory unit to be described later, and outputs data by the data request signal output from the system unit to be described later. A buffer unit for outputting a full-1 signal to stop reading data of the disk when the capacity is greater than or equal to the set value, and outputting a signal for reading data of the disk when the memory capacity is less than or equal to the set value; A memory unit which receives the address signal, the data 2 signal, and the store / read signal output from the buffer unit and outputs data by the data request signal output from the system unit; A block manager which receives the full-1 signal output from the buffer unit and includes the block in a block that is a data processing unit and outputs a full-2 signal; A system unit for converting a video / audio signal into a video / audio signal based on the data 3 signal and the clock 3 signal output from the buffer control unit; Inputs the full-2 signal output from the block manager and outputs a hold signal that blocks the error correction operation by converting the data from the analog signal to the digital signal in the signal processor, and outputs a jump signal to the controller. Outputs a control signal that controls the speed of the spindle motor, controls the operation of reading data from the disk at the same location, outputs a setting signal that sets the memory of the buffer, and the block management unit pull-2 (Full-2). DVDP including a variable bit rate data management device characterized in that the technical configuration is configured to include a CPU for driving all the operation again if no signal is output. The apparatus of claim 1, wherein the buffer unit comprises: a buffer controller configured to receive a clock 1 signal output from a signal processor and a data request signal output from a system unit; An address generator which receives the clock 1 signal output from the signal processor and the clock 3 signal output from the buffer controller; A switching unit configured to receive a data 1 signal from a signal processor and a store / read signal output from the buffer controller; And a comparator for receiving a clock 1 signal output from a signal processor and a clock 3 signal output from the buffer controller. The memory controller of claim 2, wherein the buffer controller sets the memory to store data when clock 1 is input from the signal processor, and reads data from the memory when the data request signal is input from the system. And a variable bit rate data management apparatus for controlling the signal processing unit, the memory unit, and the system unit to output a signal. 3. The apparatus of claim 2, wherein the address generator comprises: a first address generator configured to receive the clock 1 signal output from the signal processor and to generate an A1 signal which is a memory storage address; A second address generator configured to receive the clock 3 signal output from the buffer control unit and generate an A2 signal which is a memory read address; DVDP including a variable bit rate data management device characterized in that the configuration consists of a multiplexer for receiving the A1 / A2 signal when the readout A2 signal is stored when the readout A2 signal is stored in the memory. 3. The display device of claim 2, wherein the switching unit comprises: a first switch configured to switch the data 2 signal of the memory to the data 3 signal of the system unit when the signal output from the buffer controller is a read signal; And a second bit switch configured to switch the data 1 signal of the signal processor to be input to the data 2 of the memory when the input signal is the stored signal. The memory of claim 2, wherein the memory is increased when the clock 1 signal output from the signal processor is input, and the memory read signal is decreased when the clock 3 signal is input, thereby writing a few bytes to the current memory. A counter for counting whether or not; A register unit which stores a value set by the CPU; A DVDP including a variable bit rate data management device having a technical configuration, comprising a comparator configured to compare a value set in a register unit with a counter counted value and output a full-1 signal when the counter counted is large. A data reading step S1 for outputting data in response to a request signal from the system unit; A memory capacity saturation step (S2) of outputting if the memory capacity is equal to or larger than a set value or returning to the memory reading step; A block ending step (S3) of receiving the output signal and processing the block of data and then returning to the data reading step; A sector number storage step (S4) in which the CPU receives the memory saturation signal when the block ends and stores the number of saturated sectors; An inner circumferential movement step (S5) in which the pickup device is moved inward when the sector number is output; A saturation state determination step (S6) of outputting when the memory saturation state is released and maintaining the current position of the pickup device if the memory saturation state is not released; A sector number detecting step (S7) of reading the sector number when the saturation state is released; Variable bit rate data management, characterized in that it comprises a saturation sector number detection step (S8) that returns to the data reading step when the sector number where the saturation state first starts is found and returns to the data reading step. DVDP with instructions.

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