JPH02121019A - Logic circuit device - Google Patents

Abstract

PURPOSE:To make the processing speed and the power consumption of a logic circuit other than CMOS controllable by calculating an expected processing time every lapse of prescribed time, and changing the voltage of a power circuit and the clock period of a clock generation circuit according to this expected processing time. CONSTITUTION:Computer system is constituted of a processing device 101 provided with a processing speed determining part 104, a power source 201 constituted so that its output voltage is variable, an a clock generator 301 constituted so that its output clock period is variable. Here, the expected processing time is calculated every lapse of the prescribed time, and the voltage of the power source 201 and the clock period of the clock generator 301 are changed according to such an expected processing time. Thus, a logic circuit device whose processing speed and the power consumption are controllable can be obtained even in the case of the logic circuit other than the CMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit device, and more particularly to a logic circuit device whose power consumption and processing speed can be controlled in accordance with the amount of processing.

[Conventional technology]

In conventional devices of this type, for example, Japanese Patent Application Laid-Open No. 1986-
As disclosed in Japanese Patent Publication No. 166419, there has been known a device that realizes low power consumption of a logic circuit using CMO8 technology. This device uses CMO8 technology to reduce the power consumption of logic circuits, which is directly related to the clock cycle. The idea was to reduce the

[Problem to be solved by the invention]

The above conventional technology has a problem in that it cannot be applied to logic circuits whose power consumption does not change only by changing the clock cycle. for example.

A logic circuit using an ECL circuit consumes power regardless of the clock cycle, and therefore cannot be applied.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology and to make it possible to control the processing speed and power consumption of logic circuits other than CMO8. An object of the present invention is to provide a logic circuit device.

[Means to solve the problem]

The above-mentioned object of the present invention is to calculate an expected processing time every predetermined period of time in a device having a power supply circuit, a clock generation circuit, and a logic circuit, and to calculate the voltage of the power supply circuit and the clock generation based on the expected processing time. This is achieved by a logic circuit device that is provided with a means for changing the clock cycle of the circuit, thereby making it possible to change the operating speed of the logic circuit.

[Effect]

In the logic circuit device according to the present invention, the power supply voltage/clock cycle adjustment circuit operates to lower the power supply voltage applied to the logic circuit and lengthen the clock cycle when switching from high-speed operation to low-speed operation. As a result, the power consumption of the logic circuit is reduced, and since the clock cycle is lengthened (although the switching time is increased), malfunctions do not occur, and low-speed operation is performed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram of a computer system showing an embodiment of the present invention. This system includes a processing section W101 having a processing speed determining section 104, a power supply 201 configured to have a variable output voltage, and a clock generator 301 configured to have a variable output clock cycle.

The processing device 101 is composed of a job management section 102 and a job processing section 103. Submitted jobs are placed in a job queue 105 within the job management section 102, and then sequentially sent to the job processing section 103 for processing. Ru. The job management section 102 includes the processing speed determination section 104 described above.

Furthermore, the processing speed determining unit 104 determines the processing speed by monitoring the job queue 105, and sets the control signal 107 to a value of 0'' when high-speed processing is required, and a value of LL 1 g when low-speed processing is required. It has a function to output.

The power source 201 is composed of a receiving section 203 and a DC stabilized power source 202, and the receiving section 203 receives the control signal 10.
7, it has a function of converting it into an analog signal 205 to be input to the DC stabilized power supply 202.

The above-mentioned receiving unit 203 receives ((OI) as the control signal 107.
When receiving I, the DC stabilized power supply 202 outputs a high-speed processing voltage as an output voltage 204, as shown in FIG. In addition, the receiving unit 203 sends rr as the control signal 107.
1 u, the DC stabilized power supply 202 outputs the low-speed processing voltage as the output voltage 204.

The clock generator 301 is composed of an oscillator 302, a frequency divider 304, and a selector 307.

A clock signal 303 output from the oscillator 302 is separated by a frequency divider 304 into a clock signal 305 for high-speed processing and a clock signal 306 for low-speed processing.

The selector 307 selects the control signal 1 as shown in FIG.
When 07 is “0”, the high-speed processing clock signal 305 is output as the clock signal 308. In addition, the control signal 107
When is “1”, the low-speed processing clock signal 306 is output as the clock signal 308. The processing device 101 can thereby operate at the processing speed determined by the processing speed determination unit 104.

FIG. 3 is a flowchart showing the processing of the processing speed determination unit 104 described above. First, in step 401, the control signal 107 is set to '0'' as an initial state, and then in step 402, the IAT, A, T (turnaround time) and processing state observation interval are read from the outside.
In step 403, steps 404 to 409 are repeated until the system is stopped.

While the system is in operation, a timer is used to monitor the elapsed time, and each time the processing state observation interval read in step 402 elapses, the processing speed is determined to be switched (steps 404, 409). In this switching decision, first,
The expected processing time is calculated from the number of remaining jobs in the job queue 105 using equation (1) below (step 405).

Expected processing time = average processing time during low-speed processing × number of remaining jobs (1) Then, compare the expected processing time with the targets T, A, and T (step 406), and predict the processing time > target T, A , T, for high-speed processing, the control signal 107 described above is
If the expected processing time is greater than the target T, A, or T, the control signal 107 is set to 111'' for low-speed processing (step 408). Through the above processing, the processing speed is determined. The unit 104 determines the processing speed at regular intervals and controls the control signal 107.

FIG. 4 is a diagram showing an ECL basic gate.

The levels of the input signal 602 and the output signal 604 change as shown in FIG. 5 due to changes in the power supply voltage 601.

Since the base current is sufficiently small compared to the collector current, E
The current flowing through the CL basic gate is approximated to the collector current. Since the collector current changes in proportion to the power supply voltage, power consumption (current amount x voltage) changes in proportion to the square of the power supply voltage. Therefore, power consumption is reduced by lowering the power supply voltage.

FIG. 6 shows the relationship between the power supply voltage and the switching time of the logic circuit, and shows that the switching time increases as the power supply voltage is lowered. Further, FIGS. 7(a) to (c) show the configuration and operation example of an inverter circuit as an example of a logic circuit. This logic circuit operates by taking in a signal output from an input flip-flop 501 to an output flip-flop 502. Therefore, the clock period given to the logic circuit needs to be larger than the delay value of the signal from the input flip-flop 501 to the output flip-flop 502.

When this logic circuit is operated at the voltage 1 shown in FIGS. 5 and 6, if the delay value 504 due to the wiring patterns 506 and 507 is rLDJ, the delay value due to the gate 503 is as shown in FIG. 7(b). Since 505 is B, if the clock interval of the clock signal 510 is set to rB+LDJ, it will operate normally. However, when the power supply voltage is set to voltage 2 shown in FIGS. 5 and 6, the gate 503
The delay 508 is C as shown in FIG. 7(c). At this time, if the clock interval of the clock signal 511 remains rB + LDJ, the circuit will malfunction, but by setting the clock interval to rC+LDJ, the circuit will operate normally.

According to this embodiment, since the power supply voltage and the clock cycle can be changed simultaneously, when the number of processed jobs decreases, such as when waiting for job submission, it is possible to perform low-speed, low-power consumption operation, and the consumption can be reduced. It is possible to reduce power consumption.

It goes without saying that a meaningful time should be selected as the processing state observation interval described above in order to reduce power consumption.

〔Effect of the invention〕

As described above, according to the present invention, there is provided means for calculating the expected processing time every predetermined time period and changing the voltage of the power supply circuit and the clock period of the clock generation circuit based on the estimated processing time. Therefore, it is possible to realize a logic circuit device in which the processing speed and power consumption of logic circuits other than the CMO 8 can be controlled.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a computer system showing an embodiment of the present invention, Fig. 2 is a diagram showing the contents of control signals, Fig. 3 is a flowchart showing the processing of the processing speed determining section, and Fig. 4 is an ECL
Figure 5 shows the relationship between power supply voltage and operating level; Figure 6 shows the relationship between power supply voltage and switching time; Figure 7 shows the configuration and operation example of an inverter circuit. FIG. 101: processing device, 102: job management unit, 103: job processing unit, 104: processing speed determination unit, 105: job queue, 107: control signal, 201: power supply with variable output voltage, 301: output clock cycle A variably configured clock generator, 303: clock signal, 304: frequency divider, 305: clock signal for high-speed processing, 306: clock signal for low-speed processing, 307: selector.

Claims (1)

[Scope of Claims] 1. In a device having a power supply circuit, a clock generation circuit, and a logic circuit, an expected processing time is calculated every predetermined period of time, and the voltage of the power supply circuit and the clock generation are calculated based on the expected processing time. A logic circuit device comprising means for changing the clock cycle of the circuit. 2. The means for changing the voltage of the power supply circuit and the clock period of the clock generation circuit, the means for calculating the expected processing time at each processing state observation interval, and the calculated expected processing time and target turnaround time, 2. The logic circuit device according to claim 1, further comprising means for outputting a control signal for changing the voltage of the power supply circuit and changing the clock cycle of the clock generation circuit.