JP6771233B2 - Semiconductor integrated circuits, control methods in semiconductor integrated circuits, image processing equipment - Google Patents

Description

The present invention relates to a semiconductor integrated circuit and a technique for controlling a semiconductor integrated circuit.

The power consumption of a semiconductor integrated circuit increases as the scale of the circuit through which current flows increases. Then, clock gating is used in order to suppress an increase in power consumption due to an increase in the scale of the circuit. Clock gating is a process of stopping the supply of a clock signal to a circuit block when the circuit block including a plurality of circuits is in a standby state in which data is not rewritten. In the following description, the semiconductor integrated circuit is also simply referred to as an integrated circuit. The clock signal is, for example, a continuous binary pulse signal.

In clock gating, when the supply of the clock signal is stopped, the operation of the circuit block using the clock signal is also suddenly stopped. At this time, the current consumption of the circuit block that stops the operation may increase sharply, and the bias voltage supplied to the circuit block may decrease. If the reduced bias voltage is lower than the rated voltage of the integrated circuit including the circuit block, the integrated circuit may malfunction or stop functioning. As an example of the operation of the circuit block using the clock signal, for example, there is a toggle operation of the flip-flops constituting the circuit block.

Further, in clock gating, when the circuit block changes from the standby state to the operating state in which data is rewritten, when the supply of the clock signal to the circuit block is started, the circuit block using the clock signal The operation starts suddenly. At this time, the current consumption of the circuit block that starts operation sharply decreases, and the bias voltage supplied to the circuit block increases. When the increased bias voltage exceeds the rated voltage of the integrated circuit including the circuit block, the integrated circuit may malfunction or stop functioning.

In order to deal with such a situation, conventionally, a plurality of circuit blocks, a voltage supply means for supplying a voltage to the plurality of circuit blocks, a clock generation means for generating a clock signal, a control means, and a switching means are provided. The technology to prepare is known. In this technique, the switching means switches the supply state of whether or not the clock signal generated by the clock generation means is supplied to a specific circuit block. The control means controls the frequency of the clock signal generated by the clock generation means. Further, the control means first temporarily lowers the frequency of the clock signal from the first frequency to the second frequency according to the power consumption of the specific circuit block when the switching means switches the supply state. It is controlled to return to the frequency (see, for example, Patent Document 1).

JP-A-2007-148681

Here, in the invention described in Patent Document 1, by changing the frequency of the clock signal from the first frequency to the second frequency, the operating speed of the circuit block is reduced by the reduced frequency. Therefore, when the circuit block shifts from the standby state to the operating state, the processing capacity of the circuit may decrease. Further, in the conventional circuit block, when clock gating is performed, a large number of circuits are added around the power supply in order to suppress the change of the bias voltage when the supply of the clock signal is stopped and started. It was. Then, since the number of parts used in the integrated circuit increases, the structure of the integrated circuit becomes complicated and the manufacturing cost increases.

The present invention has been made in view of the above problems, and it is possible to prevent the circuit around the power supply from becoming complicated and increase the manufacturing cost, and to reduce the processing capacity due to the transition of the circuit state between the standby state and the operating state. Provided is a semiconductor integrated circuit that can be suppressed.

To solve such problems, the invention of claim 1 includes a standby state in which rewriting of data is not performed, a semiconductor integrated circuit Ru and a operating state rewriting of data is performed, the operating state in, the rewriting of the data by using the input clock signal is performed, a first circuit portion having a plurality of transistor circuits, in the operating state, rewrite rows of the data by using the input clock signal A first clock game that includes a second circuit unit having a plurality of transistor circuits, and the first circuit unit controls on / off of an input state of the clock signal with respect to the entire first circuit unit. The second circuit unit includes a ting unit, and the second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit. In the standby state, the first clock gating unit performs a process of blocking the clock signal input to the first circuit unit, and the second clock gating unit performs the second clock gating unit. A process of passing the clock signal input to the transistor circuit included in the circuit unit is performed, and in the operating state, the first clock gating unit inputs the clock signal input to the transistor circuit included in the first circuit unit. In addition to performing the process of passing the clock signal, the second clock gating unit constitutes the second circuit unit, and the clock input to the transistor circuit in which data is not rewritten. It is characterized in that it performs a process of blocking a signal .

The invention according to claim 2 includes a standby state in which data is not rewritten and an operating state in which data is rewritten. In the operating state, the data can be rewritten using an input clock signal. It includes a first circuit unit having a plurality of transistor circuits to be performed, a standby state in which data is not rewritten, and an operating state in which data is rewritten, and the input clock signal is input in the operating state. A second circuit unit having a plurality of transistor circuits, wherein the data is rewritten by using the first circuit unit, and the second circuit unit consume power in each of the operating states. The first circuit unit includes a first clock gating unit that controls on / off of an input state of the clock signal with respect to the entire first circuit unit, and is configured so that the amounts are substantially equal to each other. The second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit, and the first clock game unit. The ting unit performs a process of blocking the clock signal input to the first circuit unit in the standby state, and a process of passing the clock signal input to the first circuit unit in the operating state. In the standby state, the second clock gating unit passes the clock signal input to each of the transistor circuits constituting the second circuit unit, and in the operating state, the data of the data. It is characterized in that a process of blocking the clock signal input to the transistor circuit that is not rewritten is performed .

In the invention according to claim 3, in addition to the configuration according to claim 1 or 2, the first circuit section and the second circuit section are configured so that the areas are substantially equal to each other. It is characterized by.

The invention according to claim 4 has, in addition to the configuration according to any one of claims 1 to 3, the transistor circuit in the first circuit section and / or the transistor in the second circuit section. The circuit is characterized by being a flip-flop circuit.

The invention according to claim 5, a standby state in which rewriting of data is not performed, a control method in the semiconductor integrated circuit rewriting data Ru and a operation which is carried out, in the operating state, is input the rewriting of data is performed using the clock signal, a first circuit portion having a plurality of transistor circuits, in the operating state, the rewriting of data is performed using the input clock signal, a plurality of transistors e Bei and a second circuit section having a circuit, the first circuit unit includes a first clock gating unit for controlling on and off of the input state of the clock signal for the entire circuit portion of said first The second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit, and is in the standby state. the first clock gating unit performs processing for cutting off the clock signal input to the first circuit portion, the second clock gating unit the second circuit portion The process of passing the clock signal input to the transistor circuit provided is performed, and in the operating state, the first clock gating unit is input to the transistor circuit included in the first circuit unit. While performing the process of passing the clock signal, the second clock gating unit cuts off the clock signal input to the transistor circuit in which data is not rewritten, which constitutes the second circuit unit. It is characterized in that the processing is performed.

The invention according to claim 6 includes a standby state in which data is not rewritten and an operating state in which data is rewritten. In the operating state, the data can be rewritten using an input clock signal. A first circuit unit having a plurality of transistor circuits to be performed, a standby state in which data is not rewritten, and an operating state in which data is rewritten are provided, and the input clock signal is input in the operating state. A control method in a semiconductor integrated circuit including a second circuit unit having a plurality of transistor circuits, wherein the data is rewritten by using the first circuit unit and the second circuit unit. Is configured so that the power consumption in each of the operating states is substantially equal, and the first circuit unit is configured by the first clock gating unit to obtain the clock for the entire first circuit unit. The on / off of the signal input state is controlled, and the second circuit unit is configured by the second clock gating unit to control the clock for each individual clock circuit constituting the second circuit unit. The on / off of the signal input state is controlled, and in the standby state, the first clock gating unit performs a process of blocking the clock signal input to the first circuit unit. The second clock gating unit performs a process of passing the clock signal input to each of the transistor circuits included in the second circuit unit, and in the operating state, the first clock gating unit. The ting unit performs a process of passing the clock signal input to the first circuit unit, and the second clock gating unit constitutes the second circuit unit, so that data can be rewritten. It is characterized in that a process of blocking the clock signal input to the transistor circuit, which is not performed, is performed. The invention according to claim 7 is an image processing apparatus, characterized in that it includes the semiconductor integrated circuit according to any one of claims 1 to 4.

According to the first and fifth aspects of the invention, the first circuit unit includes a first clock gating unit that controls on / off of an input state of a clock signal with respect to the entire first circuit unit. The first clock gating unit performs a process of blocking the clock signal input to the first circuit unit in the standby state, and at the same time, receives the clock signal input to the first circuit unit in the operating state. By performing the passing process, the power consumption of the first circuit unit in the standby state can be reduced. Further, the second circuit unit includes a second clock gating unit for controlling the on / off of the input state of the clock signal for each transistor circuit constituting the second circuit unit, and the second clock unit. The gating unit passes the clock signal input to the individual transistor circuits constituting the second circuit unit in the standby state, and passes the clock signal input to the transistor circuit in which the data is not rewritten in the operating state. By performing the shutoff process, it is possible to suppress an increase in the power consumption of the second circuit unit in the operating state. Then, by using the first circuit unit and the second circuit unit together, the power consumption of one circuit unit increases when the standby state and the operating state transition, and the other circuit unit increases. The power consumption is reduced, and even if a circuit for suppressing a sudden change in power consumption is not provided around the power supply, a sudden change in power consumption between the standby state and the operating state can be suppressed. As a result, in the semiconductor integrated circuit, it is possible to prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and it is possible to prevent the processing capacity from decreasing when the circuit shifts from the standby state to the operating state. ..

According to the invention of claim 2, the first circuit unit and the second circuit unit are configured so that the power consumption in each operating state is substantially equal, so that the first clock -The power consumption in the standby state, which is reduced by the gating unit, and the power consumption in the operating state, in which the increase is suppressed by the second clock gating unit, can be made substantially equal. As a result, it is possible to prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and to suppress a sudden change in power consumption between the standby state and the operating state with high accuracy.

According to the invention of claim 3, the first circuit section and the second circuit section are configured so that the areas are substantially equal to each other, so that the scale of the circuit is substantially equal to the area of the circuit section. In the semiconductor integrated circuit that is configured to depend on it, the circuit scale of the first circuit unit and the circuit scale of the second circuit unit are configured to be substantially the same scale. Then, the power consumption in the standby state, which is reduced by the first clock gating unit, and the power consumption in the operating state, which is suppressed by the second clock gating unit, are almost equal to each other. Can be. As a result, it is possible to prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and to suppress a sudden change in power consumption between the standby state and the operating state with higher accuracy.

According to the invention of claim 4, since the transistor circuit in the first circuit section and / or the transistor circuit in the second circuit section is a flip-flop circuit, data can be rewritten by a clock signal. While forming the first circuit part and the second circuit part by using the circuit, it is possible to prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and in the standby state and the operating state. It is possible to suppress abrupt changes in power consumption.

According to the invention of claim 6, image processing capable of preventing the circuit around the power supply from becoming complicated and increasing the manufacturing cost and suppressing a sudden change in power consumption between the standby state and the operating state. Equipment can be provided.

It is a functional block diagram which shows the whole structure of the image processing apparatus and the semiconductor integrated circuit which concerns on this embodiment. It is a figure which showed typically the outline of the semiconductor integrated circuit of this embodiment. It is a figure which shows typically the correspondence example of the circuit block and the functional block of the semiconductor integrated circuit. It is a figure which shows typically the structural outline of the 1st circuit block of the 1st circuit part in the semiconductor integrated circuit. It is a figure which shows typically the structural outline of the 4th circuit block of the 2nd circuit part in the semiconductor integrated circuit. In the semiconductor integrated circuit of this embodiment, (a) a diagram schematically showing the relationship between the time and current values in the standby state and the operating state of the first circuit unit, and (b) the second circuit unit. It is a figure which shows typically the relationship between the value of time, and the value of a current in a standby state and an operating state. (A) A diagram schematically showing a change in the current value between the standby state and the operating state of the semiconductor integrated circuit according to the prior art, and (b) the standby state and the operating state of the semiconductor integrated circuit according to this embodiment. It is a figure which shows the change of the value of an electric current schematically.

1 to 7 show embodiments of the present invention.

[Basic configuration]
FIG. 1 is a functional block diagram showing the overall structure of the image processing apparatus and the semiconductor integrated circuit according to this embodiment.

[Image processing device]
The image processing device 100 shown in FIG. 1 is, for example, an image generation process and an image output process for displaying a moving image or a still image on an image display device (not shown) provided in front of a game machine (not shown). It is an embedded device that executes various processes including. The image processing device 100 is not limited to the image display device provided in the game machine, and may display a moving image or a still image on an image display device provided in another device. Further, the gaming machine is, for example, a pachinko machine, a slot machine, or the like.

The image processing device 100 is driven by the electric power supplied from the power source. The power source may be, for example, a commercial power source distributed to stores, homes, and factories, a storage battery, or the like.

The image processing device 100 includes, for example, a CPU 2 that controls the functions of the image processing device 100, an SRAM 3 that functions as a processing area for image generation by the drawing circuit 6, and an EEPROM 4 that records various data and programs, as shown in FIG. Further, the image processing device 100 includes a decoder 5 that decodes the encoded data, a drawing circuit 6 that performs processing for image generation based on the data, and an oscillation circuit 7 that oscillates a clock signal. The image processing device 100 includes the semiconductor integrated circuit 1 of this embodiment as hardware. The semiconductor integrated circuit 1 is an integrated circuit having a structure such as a CMOS (Complementary MOS) circuit. The semiconductor integrated circuit 1 realizes the functions of the CPU 2, SRAM 3, EEPROM 4, the decoder 5, the drawing circuit 6, and the oscillation circuit 7 shown in FIG.

In the following description, for simplification of the description, the CPU 2, SRAM 3, EEPROM 4, the decoder 5, the drawing circuit 6, and the oscillation circuit 7 will be described as the configuration of the semiconductor integrated circuit 1. However, each component included in the semiconductor integrated circuit 1 may realize a unique function by the cooperation of hardware and software.

[First circuit section, second circuit section]
FIG. 2 is a diagram schematically showing an outline of the semiconductor integrated circuit 1 of the embodiment. The configuration of the semiconductor integrated circuit 1 will be described with reference to FIG.

The semiconductor integrated circuit 1 largely includes two circuit units, a first circuit unit A10 and a second circuit unit B10.

The first circuit unit A10 is clock-gated by the entire clock gating unit 11 (see FIG. 4, not shown in FIG. 2) as the “first clock gating unit”. Second circuit portion B10 individual clock gating section ₂₁ 1 of the m (m> 1) as a "second clock gating _unit", 21 2, · · · 21 _m (see Fig. 5. Figure Clock gating is performed by (not shown in 2). The overall clock gating unit 11, the individual clock gating unit _{21 1,} 21 2 will be described later · · · 21 _m.

[Circuit block]
As shown in FIG. 2, in the semiconductor integrated circuit 1 of this embodiment, the first circuit unit A10 and the second circuit unit B10 each include one or a plurality of circuit blocks. Specifically, the first circuit unit A10 includes a plurality of, for example, three first circuit blocks A1, the second circuit block A2, and the third circuit block A3, and the second circuit unit B10 includes a plurality of, for example, three fourth circuits. It includes a block B1, a fifth circuit block B2, and a third circuit block B3.

The first to sixth circuit blocks A1, A2, A3, B1, B2, and B3 are each configured as a unit having a predetermined function in the image processing apparatus 100.

FIG. 3 is a diagram schematically showing an example of a correspondence relationship between a circuit block and a functional block of the semiconductor integrated circuit 1 according to this embodiment. As shown in FIG. 3, the first to third circuit blocks A1, A2, and A3 have the function of the drawing circuit 6. Further, the fourth and fifth circuit blocks B1 and B2 will be described as having the functions of the SRAM 3, and the sixth circuit blocks B3 will be described as having the functions of the decoder 5. However, the first to sixth circuit blocks A1, A2, A3, B1, B2, and B3 may form functional blocks in any division other than the above, and functions such as cache and EEPROM other than the above may be provided. It may be configured as a functional block to be provided.

[Circuit and clock gating section that make up the circuit block]
4 and 5 are diagrams schematically showing circuits constituting the circuit block of the semiconductor integrated circuit 1 of this embodiment. Although the configuration of the first circuit block A1 is shown in the figure, the other second to sixth circuit blocks A2, A3, B0, B1, B2 also have the same configuration.

[Circuit that constitutes the first circuit section]
FIG. 4 is a diagram schematically showing a configuration outline of the first circuit block A1 of the first circuit unit A10 in the semiconductor integrated circuit 1 of this embodiment. As shown in the figure, the first circuit unit A10 includes the entire clock gating unit 11 as one "first clock gating unit" and a plurality of, for example, n (n> 1) "second". Individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n, and a plurality of, for example, n (n> 1) flip-flop circuits 13 ₁ , as "transistor circuits". 13 _2, and a ··· 13 _n.

The overall clock gating unit 11 and the individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n are, for example, logic circuits such as an AND circuit.

The overall clock gating unit 11 and the individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n include at least two input units and one output unit. Specifically, for example, the overall clock gating unit 11 of the first circuit unit A10 includes a clock signal input unit 31 and a control signal input unit 32A as input units of two systems, and serves as an output unit of one system. A clock signal output unit 33 is provided. Although not shown, the overall clock gating unit 11 of the second circuit unit A2 is replaced with the control signal input unit 32A, and the overall clock gating unit 11 of the third circuit unit A3 is replaced with the control signal input unit 32B. A control signal input unit 32C is provided in place of the control signal input unit 32A, and different clock signals are input to the respective control signal input units 32A, 32B, 32C.

The individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n include the same clock signal input unit 31 and clock signal output unit 33 as the overall clock gating unit 11, and the control signal input unit 32a. ₀₁ , 32a ₀₂ , ... 32a _0n is provided. Different clock signals are input to the control signal input units 32a ₀₁ , 32a ₀₂ , ... 32a _0n . These clock signals are also different from the clock signals input to the control signal input units 32A, 32B, 32C.


Although not shown, the individual clock gating portion of the second circuit portion _{A2 12 1, 12 2, ···} 12 n of the control signal input section _{32a 11, 32a 12, ··· 32a} 1n, the third circuit The individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n of the control signal input units 32a ₂₁ , 32a ₂₂ , ... 32a _{2n of} the unit A3 also have a configuration in which different clock signals are input. It has become.

Flip-flop circuit _{13 1, 13 2, ··· 13} n is composed of a combination of a plurality of logic circuits, for example RS-type, a flip-flop circuit of the D type. Flip-flop circuit 13 _1, 13 _2, the · · · 13 _n, in Tachi up and stood timing of falling of the input clock signal, "0", "1" holds and the data consisting of binary, one value For example, the rewriting is performed from "0" to the other value, for example, "1".

The overall clock gating unit 11 is connected to individual individual clock gating units 12 ₁ , 12 ₂ , ... 12 _n on the rear stage side. Further, the individual clock gating unit _{12 1, 12 2, ··· 12} n includes flip-flop circuits _{13 1,} 13 2 in the rear stage side, respectively, it is connected to the · · · 13 _n.

The individual clock gating unit 12 ₁ is connected to, for example, the flip-flop circuit 13 ₁ on the rear stage side. Flip-flop circuit _{13 1,} 13 2, the · · · 13 _n, each of the data input unit _{14 1,} 14 2, and · · · 14 _n, the data output unit _{15 1,} 15 2, and · · · 15 _n, Is provided.

Global clock gating section 11, all of the flip-flop circuit ₁₃ 1 constituting the first circuit block _A1, 13 2, which controls the supply and stop of the clock signal to the · · · 13 _n. The overall clock gating unit 11 operates in both the standby state and the operating state, cuts off the clock signal in the standby state, stops the supply of the clock signal to the first circuit block A1, and clocks in the operating state. A clock signal is supplied to the first circuit block A1 by passing the signal.

Individual clock gating unit _{12 1, 12 2, ··· 12} n is the individual flip-flop circuit connected to the rear stage _{13 1,} 13 2, and clock signal supply to · · · 13 _n stopped and Control. Individual clock gating unit 12 _1, for example, does not work because the entire clock gating unit 11 has stopped the supply of the clock signal is in the standby state, the clock of the operating state to the flip-flop circuit 13 ₁ Controls the supply and stop of signals.

Data input unit _{14 1, 14 2, ··· 14} n, and the data output unit _{15 1, 15 2, ··· 15} n is a transmission path. Data input unit _{14 1, 14 2, ··· 14} n are each flip-flop circuit _{13 1,} 13 2, the data input to · · · 13 _n is transmitted. Data output unit _{15 1, 15 2, ··· 15} n are each flip-flop circuit _{13 1,} 13 2, the data output from · · · 13 _n is transmitted.

In the following description, unless when it is necessary to distinguish the individual clock gating unit _{12 1, 12 2, ··· 12} n, the flip-flop circuit _{13 1,} 13 2, the · · · 13 _n , The individual clock gating unit 12 and the flip-flop circuit 13, respectively. Further, the data input unit _{14 1,} 14 2, · · · 14 _n, the data output unit _{15 1,} 15 2, the · · · 15 _n, each of the data input unit 14, referred to as data output unit 15.

[Circuit that constitutes the second circuit section]
FIG. 5 is a diagram schematically showing a configuration outline of a fourth circuit block B1 of the second circuit unit B10 in the semiconductor integrated circuit 1 of this embodiment. As shown in FIG. 5, a fourth circuit block B1 is, for example, the individual clock gating unit ₂₁ 1 as the m "second clock gating _unit", 21 2, provided with a · · · 21 _m There is. Further, the fourth circuit block B1 includes a flip-flop circuit _{22 1,} 22 2 as a "transistor circuit" of m, and a · · · 22 _m. Individual clock gating unit _{21 1,} 21 2, · · · 21 _m, respectively, the flip-flop circuit _{22 1,} 22 2 in the rear stage side, is connected to the · · · 22 _m. The individual clock gating unit 21 ₁ is connected to, for example, the flip-flop circuit 22 ₁ . Flip-flop circuit _{22 1,} 22 2, the · · · 22 _m, each of the data input unit _{23 1,} 23 2, and · · · 23 _m, the data output unit _{24 1,} 24 2, and · · · 24 _m, Is provided.

Individual clock gating unit _{21 1, 21 2, ··· 21} m has the same structure as the whole clock gating section 11 and the individual clock gating section 12.

Individual clock gating unit _{21 1, 21 2, ··· 21} m includes a control signal input section _{32 b 01,} 32 b 02, a · · · _{32 b 0 m.} Different clock signals are input to the control signal input units 32b ₀₁ , 32b ₀₂ , ... 32b _0m . These clock signals are input to any of the other control signal input units 32A, 32B, 32C, 32a ₀₁ , 32a ₀₂ , ... 32a _0n , 32a ₁₁ , 32a ₁₂ , ... 32a _1n , 32a ₂₁ , 32a ₂₂ , ... It is also different from the clock signal input to 32a _2n . Although not shown, the individual clock gating section ₂₁ 1 of the fifth circuit portion _B2, 21 2, control · · · 21 _m signal input unit _{32 11, 32 12, ··· 32} 1n, sixth circuit individual clock gating unit _{21 1,} 21 2 parts B3, the control signal input section ₃₂ 21 of _{··· 21 m, 32 22, ···} 32 2n also is configured to mutually different clock signals are input ing.

Flip-flop circuit _{22 1, 22 2, ··· 22} m has a configuration similar to that of the flip-flop circuit 13.

Individual clock gating unit _{21 1,} 21 2, · · · 21 _m, the individual flip-flop circuit ₂₂ connected to the rear stage side _1, 22 2, and clock signal supply to · · · 22 _m stopped and Control. The individual clock gating unit 21 ₁ controls, for example, the function is stopped in the standby state, and the supply and stop of the clock signal to the flip-flop circuit 22 ₁ in the operating state.

Data input unit _{23 1, 23 2, ··· 23} m, and a data output unit _{24 1, 24 2, ··· 24} m has the same configuration as the data input unit 14 and data output unit 15.

In the description below, unless otherwise there is a need for distinction, the individual clock gating unit _{21 1,} 21 2, · · · 21 _m, the flip-flop circuit _{22 1,} 22 2, the · · · 22 _m , The individual clock gating unit 21 and the flip-flop circuit 22, respectively. Further, the data input unit _{23 1,} 23 2, · · · 23 _m, the data output unit _{24 1,} 24 2, the · · · 24 _m, each of the data input unit 23, referred to as data output unit 24.

[Size of the first circuit part and the second circuit part 1. Concept of setting]
In this embodiment, the first circuit unit A10 and the second circuit unit B10 are formed to have substantially the same size.

Here, the sizes of the first circuit unit A10 and the second circuit unit B10 will be described.

The first circuit unit A10 and the second circuit unit B10 are configured so that their respective circuit scales are substantially the same and the power consumption is the same. The power consumption in this embodiment means the magnitude of the power consumed by the first circuit unit A10 and the second circuit unit B10 in a unit time (for example, 1 second). The first circuit unit A10 and the second circuit unit B10 may be configured so that the magnitudes of physical quantities related to the consumed power are equal to each other instead of the power consumption. The magnitude of the physical quantity related to the consumed power is, for example, the magnitude of the current flowing through the first circuit unit A10 and the second circuit unit B10 per unit time, the first circuit unit A10 at a predetermined time point, and the like. It may be the magnitude of the voltage applied to the second circuit unit B10 or the like. Physical quantities such as power consumption, current, and voltage are referred to as power consumption unless otherwise distinguished.

In this embodiment, the power consumption of the first circuit unit A10 transitions to a small state in the standby state and a large state in the operating state (specifically, will be described later). On the other hand, the power consumption of the second circuit unit B10 transitions to a large state in the standby state and a small power state in the operating state (specifically, will be described later).

Therefore, if the first circuit unit A10 and the second circuit unit B10 having the same power consumption are used in combination, one of the circuit units (for example, the first circuit unit A10) accompanies the transition between the standby state and the operating state. Transition from a state in which the power consumption of the power consumption is small to a state in which the power consumption is large. At the same time, the power consumption of the other circuit unit (second circuit unit B10) changes from a large state to a small state. Then, when the states transition between the standby state and the operating state, the power consumption of the first circuit unit A10 and the second circuit unit B10 transitions in opposite directions, so that the power consumption of the semiconductor integrated circuit 1 as a whole is consumed. The change in power is small. As a result, the semiconductor integrated circuit 100 can effectively suppress abrupt changes in power consumption. In particular, in a situation where the image processing device 100 and the semiconductor integrated circuit 1 can continuously receive a stable power supply from a commercial power source or the like, the effect of effectively suppressing abrupt changes in power consumption can be stably suppressed for a long time. You can.

Further, in order to enhance such an effect, the circuit scales of the first circuit unit A10 and the second circuit unit B10 are the average value of the power consumption in the first circuit unit A10 and the second circuit unit. It is desirable that the setting is made so that the average value of the power consumption in B10 is substantially equal to the average value. The circuit scale of the first circuit unit A10 and the second circuit unit B10 is such that the maximum values (or minimum values) of the power consumption of the respective circuit units A10 and B10 are set to be substantially equal. Good. Further, the configuration may be such that the average value of one circuit unit, for example, the first circuit unit A10 and the maximum value (or minimum value) of the other circuit unit, for example, the second circuit unit B10 are set to be substantially equal. ..

If the first circuit unit A10 and the second circuit unit B10 can be used together to suppress a sudden change in power consumption, the first circuit unit A10 and the second circuit unit B10 can be used together. The circuit scale and power consumption may be different.

[Size 2 and area setting of the first circuit section and the second circuit section]
In general, the circuit scale of the semiconductor integrated circuit 1 largely depends on the area of the circuit.

Then, as shown in FIG. 2, in this embodiment, the area S1 of the first circuit unit A10 and the area S2 of the second circuit unit B10 are configured to have substantially the same size, and both circuit units A10 , B10 are configured so that the circuit scales are substantially equal, and the power consumption of both circuit units A10 and B10 is substantially equal.

The area S1 of the first circuit unit A10 and the area S2 of the second circuit unit B10 here may be an area that can be visually recognized when they are viewed in a plan view, or layers of stacked circuits may be formed. It may be the area in the unfolded state, the area including the area that can be visually recognized when viewed from the side, or any area.

[Operation procedure]
Next, the operation procedure of the semiconductor integrated circuit 1 in the image processing apparatus 100 of this embodiment will be described. Specifically, the operation procedure in the standby state and the operating state of the semiconductor integrated circuit 1 will be described.

[Operation procedure 1 / Standby state]
In the standby state, in the first circuit unit A10, the overall clock gating unit 11 cuts off the clock signal to the first circuit unit A10. Therefore, the supply of the clock signal to all the flip-flop circuits 13 constituting the first circuit unit A10 is stopped, and the data of all the flip-flop circuits 13 is not rewritten.

On the other hand, in the standby state, in the second circuit unit B10, the function of the individual clock gating unit 21 is stopped, so that the clock signal is supplied to all the flip-flop circuits 22. However, since the data is not supplied from the data input unit 23 to the flip-flop circuit 22 in the standby state, the data rewriting process is not performed in the flip-flop circuit 22.

[Operation procedure 2-Operating state]
In the operating state, in the first circuit unit A10, the entire clock gating unit 11 passes the clock signal to the first circuit unit A10. As a result, the clock signal is supplied to all the individual clock gating units 12. Further, in the individual clock gating unit 12, only the one connected to the flip-flop circuit 13 in which the data is rewritten passes the clock signal.

Specifically, for example, flip-flop circuit 13 connected to individual clock gating unit 12 ₁ to ₁ rewriting of data is performed, supplies a clock signal to the flip-flop circuit 13 ₁ is passed through the clock signal. Flip-flop circuit 13 ₁ performs rewriting of data using the data input from the data input unit 14 _1, and outputs the rewritten data to the data output unit 15 _1.

It is not performed rewriting data, other flip-flop circuit ₁₃ 2, ··· _{13 n} connected to individual clock gating unit ₁₂ 2, ··· _{12 n} blocks the clock signal. Accordingly, the flip-flop circuit ₁₃ 2, the clock signal to · · · 13 _n is not supplied, the rewriting of data is not performed.

On the other hand, in the operating state, in the second circuit unit B10, all the individual clock gating units 21 are operating. Further, only the individual clock gating unit 21 connected to the flip-flop circuit 22 in which the data is rewritten passes the clock signal.

Specifically, for example, the individual clock gating unit 21 ₁ connected to the flip-flop circuit 22 _{1 in} which data is rewritten passes the clock signal and supplies the clock signal to the flip-flop circuit 22 ₁ . The flip-flop circuit 22 ₁ rewrites the data using the data input from the input unit 23 _1, and outputs the rewritten data to the data output unit 24 ₁ .

Is not performed rewriting data, other flip-flop circuit ₂₂ 2, ... 22 connected to the _m individual clock gating unit ₂₁ 2, ... 21 _m blocks the clock signal. Accordingly, the flip-flop circuit ₂₂ 2, the clock signal to · · · 22 _m is not supplied, the rewriting of data is not performed.

[Operation procedure 3-Power consumption in standby state and operation procedure]
As shown in the operation procedure 1 and the operation procedure 2, in the standby state, in the first circuit unit A10, the overall clock gating unit 11 cuts off the clock signal to the first circuit unit A10.

Therefore, in the first circuit unit A10, power consumption due to input of the clock signal to all the flip-flop circuits 13 of the first circuit unit A10 and data rewriting are performed by operating the flip-flop circuit 13. There is no power consumption due to the flip-flops. Therefore, in the standby state, the power consumption in the first circuit unit A10 is very small.

On the other hand, in the standby state, in the second circuit unit B10, all the individual clock gating units 21 pass the clock signal, and the clock signal is input to all the flip-flop circuits 22.

Therefore, power consumption occurs because the clock signal is input to all the flip-flop circuits 22. Therefore, in the standby state, a large amount of power is consumed in the second circuit unit B10.

Next, in the operating state, in the first circuit unit A10, the entire clock gating unit 11 passes the clock signal to the first circuit unit A10. In the first circuit portion A10, a flip-flop circuit clock signal to the flip-flop circuit 13 ₁ for example rewriting of data is performed is supplied, the process of rewriting the data in the flip-flop circuit 13 ₁ is performed.

Therefore, if the operating state, in the first circuit portion A10, all clock signals to the individual clock gating portion 12 of the first circuit portion A10 is supplied, also data rewriting in the flip-flop circuit 13 ₁ Power consumption occurs as a result of the processing. Therefore, the power consumption of the first circuit unit A10 is larger than that in the standby state.

On the other hand, if the operating state, in the second circuit portion B10, the process of rewriting the data in the flip-flop circuit 22 ₁ to the flip-flop circuit 22 ₁ rewriting of data is performed is supplied the clock signal is performed. In the second circuit portion 10 of the flip-flop circuit ₂₂ 2 rewriting of data is not performed, ... 22 connected to the _m individual clock gating unit ₂₁ 2, ... 21 _m clock signals The clock signal is not supplied to the flip-flop circuit 22 _m .

Therefore, in the operating state, the flip-flop circuit 22 ₁ is all of the flip-flop circuit ₂₂ 1 rewriting of data is _performed, 22 2, when a low ratio with respect · · · 22 _m, the second circuit portion B10 The power consumption in is smaller than that in the standby state. In the above description, in the operating state, the flip-flop circuit rewriting of data is performed is described as a flip-flop circuit 22 _1, it may be performed rewriting data of two or more flip-flop circuit 22 is at the same time ..

FIG. 6 is a diagram schematically showing the relationship between the power consumption of the first circuit unit A10 and the power consumption of the second circuit unit B10 of the semiconductor integrated circuit 1 of this embodiment. In the figure, the horizontal axis is the time and the vertical axis is the current value. However, since the size of the power consumption of the semiconductor integrated circuit 1 of this embodiment changes depending on the size of the current, the figure is shown in the figure. The state of shows the change in power consumption with time (the same applies to the schematic diagram of FIG. 7 using the same parameters).

As shown in FIG. 6A, the current value of the first circuit unit A10 is larger in the operating state than in the standby state. On the contrary, as shown in FIG. 6B, the current value of the second circuit unit B10 is smaller in the operating state than in the standby state.

Therefore, in this embodiment, the power consumption of the first circuit unit A10 and the second circuit unit B10 is increased when the standby state is changed to the operating state or the operating state is changed to the standby state. , If one side increases, the other side decreases. Therefore, the power consumption of the semiconductor integrated circuit 1 as a whole has a relationship in which the direction of change of the first circuit unit A10 and the direction of change of the second circuit unit B10 cancel each other out.

This will be described in the schematic diagram of FIG. 7 in comparison with the prior art.

In the prior art, the drawing circuit 6, the SRAM 3, and the decoder 5 are all configured by the first circuit unit A10. Therefore, as shown in the schematic diagram of FIG. 7A, in the semiconductor integrated circuit according to the prior art, the current values of the drawing circuit 6, the SRAM 3, and the decoder 5 are all reduced in the standby state, while the current values are reduced. In the operating state, the values of all the currents of the drawing circuit 6, the SRAM 3, and the decoder 5 become large.

On the other hand, in the semiconductor integrated circuit 1 of this embodiment, as shown in the schematic diagram of FIG. 7B, the current value of the drawing circuit 6 constituting the first circuit unit A10 is set from the standby state. The current value increases when the operating state is entered. Further, when the SRAM 3 and the decoder 5 constituting the second circuit unit B10 shift from the standby state to the operating state, the current value becomes large. Therefore, with the change between the standby state and the operating state, the change in the power consumption of the drawing circuit 6 and the change in the power consumption of the drawing circuit 6 of the SRAM 3 and the decoder 5 cancel each other out. Become.

As a result, in the semiconductor integrated circuit 1 of the embodiment, when the standby state is changed to the operating state or the operating state is changed to the standby state, the power consumption is rapidly increased or decreased. It is prevented from causing sudden changes. Further, since the first circuit unit A10 itself and the second circuit unit B10 itself can suppress a sudden change in power consumption, it is not necessary to add another circuit for stabilizing power consumption around the power supply. It is possible to suppress an increase in manufacturing cost due to a complicated circuit configuration and an increase in the number of parts.

Further, in this embodiment, the circuit scales of the first circuit unit A10 and the second circuit unit B10 are substantially the same, and the power consumption of the first circuit unit A10 and the second circuit unit B10 is substantially the same. Become. Therefore, a sudden change in power consumption when the semiconductor integrated circuit 1 shifts from the standby state to the operating state or shifts from the operating state to the standby state is more effectively suppressed. In addition, the need for other circuits for stabilizing power consumption becomes lower, and it is possible to more effectively suppress an increase in manufacturing cost due to a complicated circuit configuration and an increase in the number of parts.

[Action effect]
As shown above, in this embodiment, the first circuit unit A10 includes an overall clock gating unit 11 that controls on / off of the input state of the clock signal with respect to the entire first circuit unit A10. The overall clock gating unit 11 performs a process of blocking the clock signal input to the first circuit unit A10 in the standby state, and passes the clock signal input to the first circuit unit A10 in the operating state. Perform processing. As a result, the semiconductor integrated circuit 1 can reduce the power consumption of the first circuit unit A10 in the standby state.

Further, the second circuit unit B10 includes an individual clock gating unit 21 that controls on / off of the input state of the clock signal for each flip-flop circuit 22 constituting the second circuit unit B10. The individual clock gating unit 21 passes the clock signal input to the individual flip-flop circuits 22 constituting the second circuit unit B10 in the standby state. Further, the individual clock gating unit 21 performs a process of blocking the clock signal input to the flip-flop circuit 22 in which the data is not rewritten in the operating state. As a result, the semiconductor integrated circuit 1 can suppress an increase in power consumption of the second circuit unit B10 in the operating state.

Then, by using the first circuit unit A10 and the second circuit unit B10 together as described above, when the standby state and the operating state transition, one of the circuit units, for example, the first circuit unit A10 The power consumption increases and the power consumption of the other circuit unit, for example, the second circuit unit B10 decreases. As a result, the semiconductor integrated circuit 1 can suppress a steep change in power consumption between the standby state and the operating state without providing a circuit around the power supply for suppressing a steep change in power consumption.

As described above, in the semiconductor integrated circuit 1, it is possible to prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and to prevent the processing capacity from decreasing when the circuit shifts from the standby state to the operating state. it can.

In the embodiment, the first circuit unit A10 and the second circuit unit B10 are configured so that the power consumption in each operating state is substantially equal. As a result, the power consumption in the standby state, which is reduced by the overall clock gating unit 11, and the power consumption in the operating state, whose increase is suppressed by the individual clock gating unit 21, are made substantially equal. Can be done. Therefore, the semiconductor integrated circuit 1 can prevent the circuit around the power supply from becoming complicated and the manufacturing cost from increasing, and can suppress abrupt changes in power consumption between the standby state and the operating state with high accuracy. it can.

In the embodiment, the first circuit unit A10 and the second circuit unit B10 are configured so that the areas are substantially equal to each other. Therefore, in the semiconductor integrated circuit 1 in which the scale of the circuit is configured to be substantially dependent on the area of the circuit unit, the circuit scale of the first circuit unit A10 and the circuit scale of the second circuit unit B10 are substantially the same scale. It will be in the configured state. As a result, the power consumption in the standby state, which is reduced by the overall clock gating unit 11, and the power consumption in the operating state, whose increase is suppressed by the individual clock gating unit 21, are made substantially equal. Can be done. Therefore, the semiconductor integrated circuit 1 prevents the circuits around the power supply from becoming complicated and the manufacturing cost from increasing, and suppresses abrupt changes in power consumption between the standby state and the operating state with higher accuracy. Can be done.

In this embodiment, the semiconductor integrated circuit 1 constitutes the image processing device 100, but the present invention is not limited to this, and a data processing device for processing other data and a signal processing device for processing signals are used. A semiconductor integrated circuit 1 may be used as a configuration. Other configurations are, for example, voice processing devices, machine learning devices, and the like.

In this embodiment, the transistor circuits constituting the first circuit section A10 and the second circuit section B10 of the semiconductor integrated circuit 1 are flip-flop circuits 13 and 22, but the present invention is not limited to this. The transistor circuit may be any circuit that operates by a clock signal, such as a counter circuit, a register circuit, or a latch circuit, or may be a combination of a plurality of types of circuits that operate by a clock signal. Good.

It goes without saying that the above-described embodiment is an example of the present invention and does not mean that the present invention is limited to the above-mentioned embodiment.

1 ... Semiconductor integrated circuit 11 ... Overall clock gating section (first clock gating section)
12, 12 ₁ , 12 ₂ , ... 12 _n ... Individual clock gating section (second clock gating section)
_{13,13 1, 13 2, ··· 13} n ··· flip-flop circuit (transistor circuit)
_{21,21 1, 21 2, ··· 21} m ··· individual clock gating section (second clock gating section)
22, 22 ₁ , 22 ₂ , ... 22 _m ... Flip-flop circuit (transistor circuit)
A10 ... First circuit unit B10 ... Second circuit unit 100 ... Image processing device

Claims (7)

A standby state in which rewriting of data is not performed, a semiconductor integrated circuit Ru and a operating state rewriting of data is performed,
In the operating state, the first circuit unit having a plurality of transistor circuits, in which the data is rewritten using the input clock signal, and
A second circuit unit having a plurality of transistor circuits, in which the data is rewritten using the input clock signal in the operating state, is provided.
The first circuit unit includes a first clock gating unit that controls on / off of an input state of the clock signal with respect to the entire first circuit unit.
The second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit.
In the standby state, the first clock gating unit performs a process of blocking the clock signal input to the first circuit unit, and the second clock gating unit performs the second clock gating unit. A process of passing the clock signal input to the transistor circuit included in the circuit unit is performed.
In the operating state, the first clock gating unit performs a process of passing the clock signal input to the transistor circuit included in the first circuit unit, and the second clock gating unit. The unit is a semiconductor integrated circuit that constitutes the second circuit unit and performs a process of blocking the clock signal input to the transistor circuit in which data is not rewritten . It has a plurality of transistor circuits having a standby state in which data is not rewritten and an operating state in which data is rewritten, and in the operating state, the data is rewritten using an input clock signal. The first circuit part and
It has a plurality of transistor circuits having a standby state in which data is not rewritten and an operating state in which data is rewritten, and in the operating state, the data is rewritten using an input clock signal. Equipped with a second circuit section
The first circuit unit and the second circuit unit are configured so that the power consumption in each of the operating states is substantially equal .
The first circuit unit includes a first clock gating unit that controls on / off of an input state of the clock signal with respect to the entire first circuit unit.
The second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit.
The first clock gating unit performs a process of blocking the clock signal input to the first circuit unit in the standby state, and is input to the first circuit unit in the operating state. The process of passing the clock signal is performed.
The second clock gating unit passes the clock signal input to the individual transistor circuits constituting the second circuit unit in the standby state, and rewrites the data in the operating state. A semiconductor integrated circuit characterized by performing a process of blocking the clock signal input to the transistor circuit, which is not performed. The semiconductor integrated circuit according to claim 1 or 2, wherein the first circuit unit and the second circuit unit are configured so that the areas are substantially equal to each other. The invention according to any one of claims 1 to 3, wherein the transistor circuit in the first circuit section and / or the transistor circuit in the second circuit section is a flip-flop circuit. Semiconductor integrated circuit. A standby state in which rewriting of data is not performed, a control method in the semiconductor integrated circuit Ru and a operating state rewriting of data is performed,
In the operating state, the first circuit unit having a plurality of transistor circuits, in which the data is rewritten using the input clock signal, and
In the operating state, the rewriting of data is performed using the input clock signal, e Bei and a second circuit portion having a plurality of transistor circuits,
The first circuit unit includes a first clock gating unit that controls on / off of an input state of the clock signal with respect to the entire first circuit unit.
The second circuit unit includes a second clock gating unit that controls on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit.
In the standby state, the first clock gating unit performs processing for cutting off the clock signal input to the first circuit portion, the second clock gating unit the second Performs a process of passing the clock signal input to the transistor circuit provided in the circuit unit of
In the operating state, the first clock gating unit performs a process of passing the clock signal input to the transistor circuit included in the first circuit unit, and the second clock gating unit. The unit is a control method in a semiconductor integrated circuit, which comprises a process of blocking the clock signal input to the transistor circuit in which data is not rewritten, which constitutes the second circuit unit. It has a plurality of transistor circuits having a standby state in which data is not rewritten and an operating state in which data is rewritten, and in the operating state, the data is rewritten using an input clock signal. The first circuit part and
It has a plurality of transistor circuits having a standby state in which data is not rewritten and an operating state in which data is rewritten, and in the operating state, the data is rewritten using an input clock signal. It is a control method in a semiconductor integrated circuit provided with a second circuit unit.
The first circuit unit and the second circuit unit are configured so that the power consumption in each of the operating states is substantially equal.
The first circuit unit is configured so that the first clock gating unit controls the on / off of the input state of the clock signal with respect to the entire first circuit unit.
The second circuit unit is configured such that the second clock gating unit controls the on / off of the input state of the clock signal for each individual transistor circuit constituting the second circuit unit.
In the standby state, the first clock gating unit performs a process of blocking the clock signal input to the first circuit unit, and the second clock gating unit performs the second clock gating unit. A process of passing the clock signal input to each of the transistor circuits included in the circuit unit is performed.
In the operating state, the first clock gating unit performs a process of passing the clock signal input to the first circuit unit, and the second clock gating unit performs the process of passing the clock signal input to the first circuit unit. A control method in a semiconductor integrated circuit, comprising a process of blocking the clock signal input to the transistor circuit in which data is not rewritten, which constitutes the second circuit unit . An image processing apparatus comprising the semiconductor integrated circuit according to any one of claims 1 to 4.

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