JPH05109896A - Layout processing method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To adjust an interconnection delay value without changing an interconnection route and without redesigning a cell arrangement and an interconnection by a method wherein the interconnection delay value and an interconnection to be adjusted are selected and a piece of wiring information that a conductor layer having the same plane shape as the plane shape of the interconnection is overlapped and wired so as to reduce an interconnection resistance is added. CONSTITUTION:Cells 20 to 24 are arranged; a layout is designed; after that, an interconnection length for individual nets 30, 31 is extracted; an interconnection delay value is extracted by the processing operation of a computer; a delay simulation is executed. When, e.g. the net 31 whose interconnection delay value is to be reduced exists, a piece of information that a substance whose resistivity is smaller than that of a substance for an interconnection layer, e.g. gold, is applied to and wired to an interconnection on the net 31 is added to a piece of wiring information. Then, a net 41 which has been covered with a metal is formed on the interconnection. The interconnection delay value is adjusted by an interconnection resistance which has been lowered. Consequently, the interconnection delay value can be adjusted even when the interconnection route of the net 30 is not bypassed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout processing method for semiconductor integrated circuits.

[0002]

2. Description of the Related Art In a conventional layout processing method, when it is found by simulation after layout design that there is a problem in signal wiring delay, the delay value is adjusted by changing the wiring route.

For example, in the layout diagram shown in FIG. 6A, five macro cells 20, 21, 22, 23 and 2 are provided.
4 and two nets 30 and 31 are shown.
The net 30 connects the macro cell 20 and the macro cell 21. Here, it is assumed that the macro cell 20 is focused. In the macro cell 20, wiring suitable for the channel region is initially performed by the wiring algorithm like the net 30.

However, paying attention to the timing of the input signal of the macro cell 20, in the wiring of the net 31 and the net 30, because of the difference in the wiring length between the two nets, the net 31
The wiring delay value in is larger. In order to make the wiring delay values of these two nets equal and to adjust the timing, conventionally, a means of equal length wiring has been used. That is, as shown in FIG. 6B, the net 30 is rewired like the net 40 so that the wiring length of the net 40 and the wiring length of the net 31 are equal to each other, and the wiring delay values of the two nets are set. Make adjustments.

[0005]

As described above, in the conventional layout processing method, if there is a problem with the wiring delay value in the original layout, the wiring route is changed according to the principle of equal length wiring, The wiring delay time was adjusted.

However, according to this method, it may be difficult to change to an optimum wiring route when the wiring is complicated and congested. In such a case, the layout of cells and the design of wiring must be redone from the beginning in consideration of the delay.

However, if the layout and wiring design is newly redone to change the wiring route, the high quality design result in the wiring information will be lost.

Further, the wiring design again requires a great deal of time and labor.

Furthermore, if the wiring delay value is adjusted with equal-length wiring, even if the wiring can be wired with a short wiring length, as in the case of a clock line, for example, the wiring route is bypassed. As a result, there is a problem that the wiring area increases and wiring becomes more difficult.

[0010]

A layout processing method for a semiconductor integrated circuit according to the present invention comprises at least a step of designing a layout of cells, a wiring route between cells and a plane shape, and a wiring for each net based on the design result. The step of extracting the length, the step of predicting the wiring delay value of the signal in the wiring for each net from the extracted wiring length, and the resistance value should be adjusted based on the predicted wiring delay value It is characterized by including a step of selecting a wiring and a step of adding to the wiring information that a conductor layer is stacked on the selected wiring and wiring is performed.

[0011]

In the layout processing method for a semiconductor integrated circuit of the present invention, a wiring whose wiring delay value is to be adjusted is selected, and a conductor layer having the same plane shape as that of the wiring is formed without changing the wiring route of this wiring. The wiring delay value is adjusted by adding to the wiring information that the wiring resistance is reduced by overlapping and wiring.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flow chart illustrating an embodiment of the present invention. FIG. 2 is a diagram showing an example of the layout of the semiconductor integrated circuit chip subjected to the layout processing according to this embodiment. FIG. 3 is a sectional view showing an example of the sectional structure of the semiconductor integrated circuit chip according to the present embodiment.

In the processing procedure of this embodiment, as shown in the flow chart of FIG. 1, first, in step 1, cells are arranged to perform layout design.

Next, in step 2, the wiring length for each net is extracted. From the result, in step 3, the wiring delay value is extracted by computer processing.

Thereafter, a delay simulation is performed in step 4 based on the above wiring delay value.

Next, from the result of the delay simulation,
In step 5, it is judged whether there is a net whose wiring delay value is to be reduced. If such a net is present, it is indicated in step 6 that the wiring of the net 31 in the layout shown in FIG. 6 is covered with a material having a specific resistance smaller than that of the wiring layer, for example, gold. Add information to wiring information. If not, the flow is complete.

In the conventional layout processing method, the wiring delay value is adjusted by means such as equal length wiring. For example, pay attention to the macro cell 20 in FIG. Here, initially, wiring suitable for the channel region like the net 30 is made by the wiring algorithm. However, if an error occurs in the delay simulation performed for this layout, it is necessary to use a means of equal-length wiring to bypass the wiring route and redo the wiring. If it doesn't work, you have to go back to the layout design.

However, in the processing procedure of this embodiment, the net 31 in FIG. 6A is determined to be the net whose wiring delay value is to be reduced in step 5 of FIG. Then, in step 6 of FIG. 1, information indicating that the wiring of the net 31 is covered with a material having a smaller specific resistance than the material of the wiring layer, for example, gold, is added to the wiring information. With this, the processing is completed, and the manufacturing is performed based on the wiring information.

The structure of the semiconductor integrated circuit chip manufactured based on the wiring information by the layout processing method of this embodiment will be described below. FIG. 3 is a sectional view showing a sectional structure of a wiring portion of such a semiconductor integrated circuit chip. With reference to FIG. 3, this semiconductor integrated circuit chip is manufactured as follows. First, the oxide film 1 is formed on the semiconductor substrate 10.
1 is provided, the first aluminum wiring layers 12 and 13 are formed by using the photolithography technique, and the interlayer insulating film 14 is formed.

Next, based on the wiring information, the interlayer insulating film 14 on the first aluminum wiring layer 12 for which the wiring delay value is desired to be reduced is removed by using the photolithography technique, and gold having a small specific resistance is formed on the interlayer insulating film 14. Form layer 15. Next, all the gold layers other than the first aluminum wiring layer 12 are removed by using the photolithography technique. Then, the interlayer insulating film 16 is formed and the second aluminum wiring layer 17 is formed.

In the case of further multilayer wiring, the interlayer insulating film 18 is formed in the same process as described above, and the wiring layer is provided thereon.

When this embodiment is applied to, for example, the net 31 in FIG. 6A, the net 41 having the gold layer on the wiring is realized as shown in FIG. The fact that the resistance is low is shown by thickening the wiring width. As a result, the wiring delay value is adjusted, and the original wiring route is maintained without bypassing the wiring route of the original net (net 30 in FIG. 6A) like the net 40 in FIG. 6B. Net 30 which is That is,
The wiring delay value can be adjusted without redesigning the layout and wiring.

Next, a second embodiment of the present invention will be described. FIG. 4 is a flowchart of the second embodiment of the present invention. Figure 4
In this embodiment, steps 1 to 6 are the same as those in the first embodiment. However, after step 5, step 7 is provided to check whether it is a clock net. If the net is a clock net, in step 8, based on the result in the clock net, in step 9, select the wiring of the pin pair whose wiring delay value is to be reduced, and cover the wiring of the pin pair with gold. Wiring is added to the wiring information.

As shown in FIG. 5, the clock driver 25
In the case of the clock net 32 output from the above and inputting the signals to the macro cells 26, 27, 28 and 29, focusing on the timing of the macro cell 26 and the macro cell 27, the net 32a is delayed between the net 32a and the net 32b. .. When it is necessary to reduce the value of the clock skew by making the wiring delay values for each pin pair from the output pin to the input pin equal, as in the case of a clock line, conventionally, a means of equal length wiring has been used. However, in the flow of this embodiment shown in FIG. 4, the clock net 32 in FIG. 5 is judged to be a clock in step 7. Then, in step 8 of FIG. 4, nets (32a, 32b, 32c and 32 in FIG. 5) for each pin pair in the clock net are shown.
The wiring delay value of d) is extracted. Then, in step 9 of FIG. 4, the clock net 32 whose wiring delay value is desired to be reduced is
Select a and 32d, and in step 6, add wiring to the wiring information to cover only the selected net with gold. With this, the processing is completed, and the manufacturing is performed based on the wiring information. The manufacturing process is the same as in the first embodiment.

As described above, in this embodiment, since the wiring delay value for each pin pair in the clock net is extracted, when the wiring delay occurs in the clock net, the wiring delay value for each pin pair can be adjusted. There is an advantage that is possible.

[0026]

As described above, according to the present invention,
After layout design of cell placement and wiring, extract the wiring length for each net, obtain the wiring delay value from this wiring length, select the wiring whose resistance value should be adjusted in consideration of this wiring length delay value, By adding wiring to the selected wiring by further covering the wiring with a conductor layer, it is possible to adjust the wiring delay without changing the wiring route when the wiring delay is adjusted. Also, the wiring is crowded,
Even when it is difficult to change the wiring route, it is not necessary to redistribute the layout and wiring again, and the wiring design can be facilitated. Further, it is possible to prevent the congestion of wiring and the increase of the wiring area, which occur when the wiring delay value is adjusted for the clock line by the equal length wiring.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a layout processing method according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of a semiconductor integrated circuit chip according to a first embodiment of the present invention.

FIG. 3 is a sectional view showing a sectional structure of a semiconductor integrated circuit chip manufactured by applying the present invention.

FIG. 4 is a flowchart illustrating a layout processing method according to a second embodiment of the present invention.

FIG. 5 is a layout diagram of a semiconductor integrated circuit chip according to a second embodiment of the present invention.

FIG. 6A is a diagram showing an example of a layout of a semiconductor integrated circuit chip. Diagram (b) is diagram (a)
FIG. 11 is a diagram showing a layout obtained as a result of processing the layout shown in FIG. 1 by a conventional layout processing method.

[Explanation of symbols]

1,2,3,4,5,6,7,8,9 Step 10 Semiconductor substrate 11 Oxide film 12,13 First aluminum wiring layer 14,16,18 Interlayer insulating film 15 Gold layer 17 Second aluminum wiring layer 20 , 21, 22, 23, 24 Macrocell 25 Clock driver 30, 31, 32, 32a, 32b, 32c, 32d,
51,52 net

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display area H01L 21/3205

Claims (1)

[Claims] 1. At least a step of designing a layout of cells and a wiring route and a planar shape between cells, a step of extracting a wiring length for each net from the design result, and a step of extracting a net from the extracted wiring length. For each, a step of predicting a wiring delay value of a signal in the wiring, a step of selecting a wiring whose resistance value is to be adjusted based on the predicted wiring delay value, and a conductor on the selected wiring A layout processing method comprising: a step of adding wiring to the wiring information in a layered manner.