JP2003044535A - Design method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently resolve a breach of delay limitations of wiring by using actively a wiring layer with a low resistance having a thick film in a design method for semiconductor integrated circuit using a wiring layer with multilayer. SOLUTION: A design method for semiconductor integrated circuit performing a wiring layout again after performing an assignment of specified wiring layers by selecting by net more than one wiring layer from a plurality of wiring layers varying thickness of film to resolve the breach of delay limitations in a step 5 for resolving of breach of delay limitations based on the information 2 on a layout result acquired in a step 1 for wiring layout and the wiring information 4 acquired in a step 3 for determining delay on the breach of limitations of signal transmission delay time caused by each laid out wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit for wiring a digital logic circuit or the like in a computer or the like by using a multilayer wiring structure.

[0002]

2. Description of the Related Art In designing an LSI, it is important to satisfy a propagation delay time required for a signal to propagate from one circuit to another circuit and to minimize the layout area of the semiconductor integrated circuit. Very important in terms of performance and cost. On the other hand, since the circuit scale of the semiconductor integrated circuit is increasing and the operating frequency of the circuit is also high, the delay constraint for restricting the propagation delay time in advance at the design stage is becoming severe. Therefore, it is an important issue how to reduce the signal propagation delay time of the path (wiring) that violates the delay constraint in the initially laid-out semiconductor integrated circuit and modify the design so as to satisfy the delay constraint. is there.

Conventionally, when a delay constraint violation is found, that is, after the layout is completed, the capacitance value and resistance value of the wiring in the layout are accurately grasped, and the signal propagation delay of the wiring is based on these. When the time is calculated and the calculated delay time exceeds the set delay time and a violation of the delay constraint is found, the following method for reducing the signal propagation delay time has been adopted. That is, a method of replacing a transistor that drives a wiring that violates a delay constraint with one that has a large driving capability, or a wiring that violates a delay constraint is shortened or widened to reduce the resistance value of the wiring. And a method of reducing the capacitance value of the wiring by widening the interval between the wirings violating the delay constraint and the adjacent wiring.

[0004]

With the progress of miniaturization of semiconductor integrated circuits and the improvement of the degree of integration, the ratio of the wiring delay to the signal propagation delay is increasing. In particular, the delay effect due to the wiring resistance cannot be ignored. Is coming. Therefore, as a laminated structure of the wiring layer, an inverse scaling structure in which the film thickness of the wiring layer gradually increases from the lower layer to the upper layer has become the mainstream. Nevertheless, none of the above-mentioned conventional methods for solving the delay constraint violation can sufficiently utilize the inverse scaling wiring structure.

That is, by positively utilizing a structure in which the wiring resistance varies greatly depending on the wiring layer, the effort for layout correction can be minimized or the area efficiency of the wiring layout can be maximized. However, the conventional method remains the method applied to the conventional wiring structure in which all wiring layers have the same film thickness and the same wiring resistance.

The present invention has been made in view of the above points, and an object thereof is to actively utilize a wiring layer having a large film thickness and a low resistance in a multilayer wiring layer and to violate the delay constraint violation of the wiring. An object of the present invention is to provide a method for efficiently designing a semiconductor integrated circuit.

[0007]

In order to achieve the above object, a first semiconductor integrated circuit designing method according to the present invention comprises:
Based on the wiring layout process that connects the components that make up the circuit based on the net information of the connection terminals and the information of the layout result obtained by the wiring layout process, each laid out wiring violates the signal propagation delay time constraint. A method for designing a semiconductor integrated circuit, comprising: a delay determining step for determining whether or not to perform the delay constraint violation, and a delay constraint violation eliminating step for eliminating the delay constraint violation based on the layout result information and the determination result in the delay determining step. In the delay constraint violation resolving step, the designated wiring layer is assigned and then the wiring layout is performed again by selecting one or more wiring layers from a plurality of wiring layers having different film thicknesses for each net. Characterize.

In the first semiconductor integrated circuit design method, the delay determination step includes a delay constraint violation wiring extraction step for extracting a wiring whose signal propagation delay time violates the signal propagation delay constraint, and the delay constraint violation is resolved. In the step, it is preferable that, for the extracted wiring that violates the delay constraint, the wiring layer mainly used by the net is changed to a wiring layer having a larger film thickness, and then the wiring layout is performed again.

Alternatively, in the first method for designing a semiconductor integrated circuit, the delay determination step includes a delay constraint violation wiring extraction step for extracting a wiring whose signal propagation delay time violates the signal propagation delay constraint, and the delay constraint In the violation resolving step, the extracted wirings violating the delay constraint are preferentially selected for a net in which the driving force of the component that drives the net is relatively high,
It is preferable to change the wiring layer mainly used by the net to a wiring layer having a larger film thickness and then perform the wiring layout again.

In the first method for designing a semiconductor integrated circuit, the delay constraint violation resolving step involves connecting the nets of the extracted delay constraint violation wirings in the form of parallel wirings using upper and lower wiring layers. It is preferable to provide one or more connection vias in the middle of the parallel wiring path.

In order to achieve the above-mentioned object, a second semiconductor integrated circuit designing method according to the present invention comprises a wiring layout step of connecting components constituting the circuit based on net information of connection terminals, and a wiring layout step. Based on the information of the layout result obtained by, the delay determination step of determining whether each of the laid out wiring violates the constraint of the signal propagation delay time, the information of the layout result and the determination result in the delay determination step. And a delay constraint violation eliminating step of eliminating a delay constraint violation based on the above. In the delay constraint violation resolving step, the wiring layer having a relatively thick film thickness is mainly used in the extracted delay constraint violation wiring. It was to have nets preferentially selected, and replaces the component that is driving the net higher driving capability component.

In order to achieve the above object, a third semiconductor integrated circuit designing method according to the present invention prepares basic circuit components as a library and selects components constituting a circuit from the library. A method of designing a semiconductor integrated circuit to be used, characterized in that output terminals of components having relatively high driving ability in a library are connected in advance to a wiring layer having relatively thick film thickness.

According to the above configuration, when there is a wiring that violates the delay constraint, the wiring that violates the delay constraint is efficiently eliminated by positively utilizing the thick film wiring layer having a low resistance, and the man-hours required for the design are reduced. It becomes possible to reduce.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a flow chart showing a method for designing a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a layout step. In this layout step 1, after arranging the components that form the circuit, wiring layout is performed based on the net information of the connection terminals. As a result of the processing of the layout step 1, layout result information 2 is obtained.

Next, 3 is a delay judgment step, which includes a delay constraint violation wiring extraction step 31. In the delay determination step 3, the layout result information 2 is input, the propagation delay time from the time of transmission of a signal between the components connected by each wiring to the time of reception is calculated, and the signal propagation time for each wiring is calculated. The delay constraint information for constraining is read from a memory or the like, and the calculated signal propagation delay time of each wiring is compared with the corresponding delay constraint to determine whether or not each laid-out wiring violates the delay constraint. , Wiring having a large propagation delay time is extracted in violation of the delay constraint. Delay delay violation wiring information 4 is obtained by the delay determination step 3 including the delay constraint violation wiring extraction step 31.

Next, 5 is a delay constraint violation solving step, which includes a wiring layer designation changing step 51. In the delay constraint violation resolving step 5, based on the layout result information 2 and the delay constraint violation wiring information 4, for the extracted delay constraint violation wiring, the used wiring layer of the wiring is relatively thicker in film thickness. The specified information at the time of wiring layout is changed to use the wiring layer, and the wiring layout is performed again, so that the delay constraint violation is resolved.

As a result, the final layout information 6 in which the delay constraint violation is resolved can be obtained.

In the delay constraint violation elimination step 5,
As shown in the flow chart of FIG. 2, for wiring that violates the delay constraint, a net having a relatively high driving force of a component that drives the net is preferentially selected, and a wiring layer mainly used by the net is set as a film. A process of prioritizing wiring that violates the delay constraint, such as changing the designation to a thicker wiring layer and then performing the wiring layout again (prioritizing the wiring to be changed by the driving force of the driving component). It is also effective to add step 52).

Further, in the delay constraint violation elimination step 5, for example, when the wiring layer structures are all structures having the same film thickness, as for the wiring which violates the delay constraint, as shown in the wiring layer structure diagram of FIG. Are connected in the form of parallel wiring using upper and lower two wiring layers (first wiring layer wiring 202 and third wiring layer wiring 204, second wiring layer wiring 203 and fourth wiring layer wiring 205). A configuration in which a thick film wiring is pseudo-realized by providing one or more connection vias 206 in the middle of the route is also effective.

FIG. 4 shows the signal propagation delay when the driving force (driver size) of the components for driving the wiring net is constant,
It is a graph which carried out the simulation measurement according to wiring length using the thin film wiring layer (A) and the thick film wiring layer (B). Here, the resistance value of the thick film wiring layer per unit wiring length is set to 1/4 of the resistance value of the thin film wiring layer. As can be seen from FIG. 4, for a net having a wiring length longer than a certain length, the effect of reducing the delay time is increased by using the thick wiring layer.

(Second Embodiment) FIG. 5 is a flowchart showing a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention. 5, the layout process 1, the layout result information 2, the delay determination process 3, the delay constraint violation wiring extraction process 31, the delay constraint violation wiring information 4, and the layout result 6 in which the delay constraint violation is resolved are shown in FIG.
Is the same as.

Reference numeral 15 is a delay constraint violation resolving step, and the object to be changed by the wiring layer used is the latitude line prioritizing step 151.
And a driving force changing step 152 of the driving component.
In the delay constraint violation resolving step 15, based on the layout result information 2 and the delay constraint violating wiring information 4, for the extracted wiring which violates the delay constraint, the signal propagation delay of the wiring is shortened to eliminate the delay constraint violation. To do.

The delay constraint violation resolving step 15 in this embodiment has the same role as the delay constraint violation resolving step 5 in the first embodiment, but the method adopted is different. That is, in the present embodiment,
In the delay constraint violation resolving step 15, a wiring net that mainly uses a wiring layer having a relatively large film thickness among the wirings violating the delay constraint is preferentially selected (the change target depending on the used wiring layer is a parallel line). In the prioritization step 151), the component driving the net is replaced with a component having a higher driving capability (driving force changing process 152 of the driving component) to eliminate the delay constraint violation. After this step, layout information 6 is obtained as a result of eliminating the delay constraint violation.

FIG. 6 is a graph showing the rate of delay reduction by doubling the driving force of the parts for each film thickness. In addition,
In FIG. 6, the information diamond points indicate the delay reduction rate when the drive capability of the component is increased from “drive force 2” to “drive force 4”, and the information square points indicate the drive capability of the component from “drive force 4”. The delay reduction rate when the driving force is increased to 8 is indicated, and the information triangle points indicate the driving ability of the component from "driving force 8" to "driving force 1".
6 shows the delay reduction rate when it is increased to "6".

For example, in the example of the information triangle points in FIG. 6, comparing the delay reduction rates when the used wiring layer is a thin film wiring layer and when it is a thick film wiring layer, a comparison is made when the thin film wiring layer is used. The delay reduction rate is 13%, while the delay reduction rate is 32% when the thick film wiring layer is used. This allows you to select nets that are mainly wired using thick film wiring layers,
It can be understood that giving priority to the driving capability of the components driving the net is effective in eliminating the delay constraint violation.

(Third Embodiment) FIG. 7 shows a case where a transistor is used as a component of a library used in the method for designing a semiconductor integrated circuit according to the third embodiment of the present invention, in the case of low driving force (a). In the case of high driving force, it is illustrated separately in (b). In FIG. 7, 101 and 101 ′ are output terminals of transistors, 102 is a first wiring layer, and 103 is a second wiring layer.
Wiring layer, 104 is a third wiring layer, 105 is a fourth wiring layer, 106 is a fifth wiring layer, 107 is a ground wiring, and 108
Is a power supply wiring, 109 is a connection via, 110 is a transistor gate region, 111 is a transistor active region, 11
2 is an input terminal of the transistor.

In the case of a low driving force transistor, FIG.
As shown in FIG. 7A, the wiring layer of the output terminal 101 of the transistor is the lower wiring layer 102 as usual, but in the case of a high driving force transistor, as shown in FIG. The wiring layer of the terminal 101 'is
Wiring layer 102, second wiring layer 103, third wiring layer 1
04, the fourth wiring layer 105, the fifth wiring layer 106, and the like, the wiring layers of the upper layer having a relatively large film thickness are previously raised. As a result, it is possible for the automatic wiring processing system to more easily create a situation in which an upper wiring layer having a large film thickness can be easily used for a wiring net driven by a component having a high driving force.

As already mentioned, it is effective to use a thick film wiring layer for shortening the delay in a long wiring which needs to be driven with a high driving force. Raising the output terminal to the upper layer in advance is effective in reducing delay constraint violation at the time of initial layout and shortening the overall design time.

[0030]

As described above, according to the present invention,
When there is a wiring that violates the delay constraint, it is possible to efficiently eliminate the wiring that violates the delay constraint by actively utilizing the low-resistance thick film wiring layer, and reduce the man-hours required for the design.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a modification of the method for designing a semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 3 is a wiring structure diagram showing an example of a case where parallel wirings of upper and lower two wiring layers are used in the method for designing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a difference in delay time depending on a wiring film thickness in the method for designing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a difference in a delay reduction effect by doubling a driving force according to a wiring film thickness in a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 7 is a structural diagram of a library component used in a semiconductor integrated circuit designing method according to a third embodiment of the present invention.

[Explanation of symbols]

1 Layout process 2 Layout result information 3 Delay determination process 31 Delay constraint violation wiring extraction process 4 Delay constraint violation wiring information 5 Delay constraint violation resolution process 51 Wiring layer designation modification process 52 Priority of modification target wiring by driving force of driving component Attaching Step 6 Layout Result with Resolved Delay Violation 15 Delay Delay Constraint Violation Resolving Step 151 Prioritizing Steps for Change Target Wiring by Used Wiring Layer 152 Driving Force Changing Steps 101, 101 ′ Transistor Output Terminal 102 First Wiring Layer 103 second wiring layer 104 third wiring layer 105 fourth wiring layer 106 fifth wiring layer 107 ground wiring 108 power supply wiring 109 connection via 110 transistor gate electrode 111 transistor active region 112 transistor input terminal 201 circuit component 202 first Wiring layer wiring 203 Second wiring layer wiring 204 Third Line layer wiring 205 fourth wiring line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/04 H01L 21/88 ZF term (reference) 5B046 AA08 BA06 JA01 5F033 UU04 UU07 XX10 XX27 5F038 CD05 CD12 EZ11 EZ20 5F064 EE02 EE03 EE23 EE26 EE42 EE58 HH06

Claims (6)

[Claims] 1. A wiring layout process for connecting components constituting a circuit based on net information of connection terminals, and a signal propagated to each of the laid-out wirings based on information of a layout result obtained by the wiring layout process. A delay determination step of determining whether or not the delay time constraint is violated,
A method of designing a semiconductor integrated circuit, comprising: a delay constraint violation resolving step of resolving the delay constraint violation based on the layout result information and a determination result in the delay determining step, wherein the delay constraint violation resolving step comprises: , Designing a semiconductor integrated circuit characterized in that, by selecting one or more wiring layers from a plurality of wiring layers having different thicknesses for each net, the designated wiring layers are allocated and then the wiring layout is performed again. Method. 2. The delay judgment step includes a delay constraint violation wiring extraction step of extracting a wiring whose signal propagation delay time violates the signal propagation delay constraint, and the delay constraint violation elimination step includes the extraction. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein wirings violating the delay constraint are redesigned by changing the wiring layer mainly used by the net to a wiring layer having a thicker film thickness. . 3. The delay judgment step includes a delay constraint violation wiring extraction step of extracting a wiring whose signal propagation delay time violates the signal propagation delay constraint, and the delay constraint violation elimination step includes the extraction. For wiring that violates the delay constraint, preferentially select a net that has a relatively high driving force of the components that drive the net, and change the wiring layer mainly used by the net to a thicker wiring layer. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the wiring layout is performed again after that. 4. The delay constraint violation resolving step performs connection of the net for the extracted delay constraint violation wiring in the form of parallel wiring using upper and lower two wiring layers,
4. The method for designing a semiconductor integrated circuit according to claim 2, wherein one or more connection vias are provided in the middle of the parallel wiring path. 5. A wiring layout process for connecting components constituting a circuit based on net information of connection terminals, and a signal transmission of each of the laid-out wirings based on the layout result information obtained by the wiring layout process. A delay determination step of determining whether or not the delay time constraint is violated,
A method of designing a semiconductor integrated circuit, comprising: a delay constraint violation resolving step of resolving the delay constraint violation, based on the layout result information and the determination result of the delay determining step, wherein the delay determining step is a signal A delay constraint violation wiring extraction step of extracting a wiring whose propagation delay time violates the signal propagation delay constraint, and the delay constraint violation resolution step comprises a relative film among the extracted delay constraint violation wires. Select the wiring net that mainly uses thick wiring layer preferentially,
A method of designing a semiconductor integrated circuit, characterized in that a component driving the net is replaced with a component having a higher driving ability. 6. A method of designing a semiconductor integrated circuit, wherein basic circuit components are prepared as a library, and components constituting a circuit are selected from the library and used. A method for designing a semiconductor integrated circuit, wherein the output terminal of a component having high driving ability is connected in advance to a wiring layer having a relatively large film thickness.