JP3052863B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit comprising a logic circuit using MOS transistors.

[0002]

2. Description of the Related Art A semiconductor integrated circuit of this type is configured as a functional circuit block such as a gate of NAND or NOR, a flip-flop or an inverter by combining circuit cells composed of circuit elements such as MOS transistors. Further, these functional circuit blocks are connected by wiring to form a required logic circuit.

[0003] Recently semiconductor integrated circuit of this type, high performance, and more accompanied high degree of integration in the trend of high performance, functional circuit blocks (hereinafter circuit block) between the wiring of the resistance of such capacity increase The problem is the signal delay caused by the above.

FIG. 4 is a circuit diagram showing the connection between two circuit blocks. Referring to FIG. 4, circuit blocks 1 and 2 at the front and rear stages to be connected, and a wiring W1 of length 1 connecting these circuit blocks 1 and 2, including.

Referring to FIG. 5A, which shows a block diagram of a conventional semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. Hei 4-23347 in which the signal delay caused by the wiring is suppressed, Circuit block 1 common to FIG.
2, wirings W2 and W3, each of which divides the wiring W1 and have lengths 11 and 12, respectively, and a buffer gate 3 inserted between these wirings W2 and W3.

Next, the operation of the conventional semiconductor integrated circuit will be described with reference to FIG. 5A. The circuit blocks 1 and 2 are latch circuits, and the delay time D between the circuit blocks 1 and 2 is Sum of delay time for each gate stage D = d1
+ D2. Here, d1 indicates a delay time from the circuit block 1 to the buffer gate 3, and d2 indicates a delay time from the buffer gate 3 to the circuit block 2. Here, each of (d) of d1 and d2 is the driving capability of the gate serving as the source (the circuit block 1 or the like), the additional capacitance of the gate serving as the sink (the circuit block 2 or the like), the wiring capacitance, and the wiring resistance between the source and the sink. And is expressed by the following equation.

D = dCL + dw = dC + dL + dW (1) where, dC: gate circuit delay time under no load, d
L: load delay time which is an increment due to load on dC,
dW: represents a wiring delay time due to wiring.

These component-dependent delay times depend on the wiring length when the net configuration such as the source gate and the fan-out is the same. Here, the wiring delay time dW is expressed by the following equation.

DW = α × R × C = α × rl × cl = α × r × c × l ² (2) where R: resistance between source and sink, C: load of net Capacitance, α: proportional constant, c: capacitance per unit length, r: resistance per unit length, l: wiring length.

As shown in the equation 2, the wiring delay time dW is
It increases in proportion to the square of the wiring length. On the other hand, when the circuit load delay time dCL exceeds a certain range with respect to the load capacitance, the load delay time dCL becomes substantially constant, so that the total delay time is proportional to l ² .

When the difference between the sum of the delay times of the divided wirings when the wiring length l of the wiring W1 is divided and the original wiring delay time of the wiring W1 is larger than the delay time of one stage of the buffer gate. By dividing the wiring W1 into the wirings W2 and W3 and inserting the buffer gate 3, the delay time can be reduced.

The operation of this conventional placement and routing method will be described with reference to FIG. 6 which is a flowchart showing a delay time improvement process by inserting a buffer gate in a conventional semiconductor integrated circuit. First, in step P1, an initial placement process is executed. I do. Next, all the wiring net information is read (step P2), and it is determined whether the read wiring net information is a wiring net requiring delay time improvement (step P3), and if necessary, step P4 is performed. In step P1
Tentative wiring length is calculated based on the placement result of step P5.
Then, the delay time corresponding to the provisional wiring length is calculated, and step P
At 6, it is determined whether the calculated delay time is within the constraint value. As a result of judgment, the net exceeding the constraint value is
In step P7, buffer gate logic is added to the logic information file. Next, a process of actually arranging the added buffer gate is performed (step P8).

As described above, in this conventional semiconductor integrated circuit and its layout method, the delay time is reduced by inserting the buffer gate between the preceding circuit block and the subsequent circuit block.

However, a complementary MOS (CMOS) using a general MOS transistor as this kind of logic circuit
In the case of the type logic circuit, as shown in FIG. 5B, the buffer gate 3 has a configuration in which normally two stages of inverters 31, 32 are directly connected in cascade without wiring. Therefore,
The load on the wiring W3 is not distributed between the inverters 31 and 32, and the load on the wiring W3 is concentrated on the inverter 32.
Therefore, the improvement of the delay time is insufficient. If a buffer gate is simply inserted, power consumption increases by the amount of the buffer gate.

[0015]

In the above-described conventional semiconductor integrated circuit and the method of arranging and wiring the same, a delay time is reduced by inserting a buffer gate between a preceding circuit block and a subsequent circuit block. General CMOS
In the type logic circuit, the buffer gate is composed of two stages of inverters directly connected in cascade, and the wiring load is not distributed among these two stages of inverters and the wiring load is concentrated only on the inverter at the subsequent stage. However, there was a drawback that was insufficient.

Further, if a buffer gate is simply inserted, there is a disadvantage that power consumption increases by the amount of the buffer gate.

An object of the present invention is to provide a semiconductor integrated circuit which can solve the above-mentioned drawbacks and can effectively reduce the delay time by adding a small number of circuit elements, and a method of arranging and wiring the same.

[0018]

A semiconductor integrated circuit according to the present invention comprises complementary MOS transistor circuit cells, and interconnects a first circuit function block on a signal source side and a second circuit function block on a signal reception side. A semiconductor integrated circuit constituting a desired logic circuit, comprising an even number of first inverters inserted so as to divide the wiring between the first circuit block and the second circuit block at substantially equal intervals; The sum of the delay time of the even number of first inverters and the delay time of the divided wiring due to the second wiring length is made smaller than the signal delay time of the first wiring length of the wiring, and The sum of the sum of the gate widths of the MOS transistors constituting each of the first inverters and the gate width of the MOS transistors of the second inverter in the output stage of the first circuit block is the even number. It is characterized in that equal to the first third of the gate width of the inverter of the MOS transistor of the first circuit block before inserting the inverter.

[0019]

[0020]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The semiconductor integrated circuit according to the present embodiment shown in this figure has an even number of inverters 4 and 5 inserted at regular intervals between the circuit blocks 1 and 2 which are common to the prior art, and two inverters 4 and 5 for convenience of explanation. Equal length wirings W5, W6, and W7 are provided to connect between the block 1 and the inverters 4 and the inverters 4 and 5, and between the inverter 5 and the circuit block 2, respectively.

That is, the wirings W5, W6, and W7 divide the wiring length 1 between the circuit blocks 1 and 2 into three equal parts, and
Each has the same wiring length 1/3.

Next, the operation of the present embodiment will be described with reference to FIG. 1. The wiring delay time is proportional to the square of the wiring length l according to the above two equations.

DW = α × r × c × l ² = Kl ² (3) where K = α × r × c: constant. The wiring length l of this wiring W
Is divided by an arbitrary ratio j, k (j + k = 1, j ≦ 0.5), and when the wiring lengths of the respective wirings Wj, Wk are jl, kl, the total wiring delay time dWT is expressed by the following equation. .

DWT = dWj + dWk = K ｛(jl) ² + (kl) ² ｝ = Kl ² (j ² + k ² ) = Kl ² (2j ² + 1-2j) (4) Differentiating equation (4) with respect to j gives the following equation.

4j-2 (5) Therefore, j = 1/2, that is, j = k, and therefore When divided equally, the total wiring delay time dWT becomes minimum.

Next, a method for placing and routing a semiconductor integrated circuit according to the present invention will be described with reference to FIG. 2 which is a flowchart showing a specific procedure for inserting an inverter according to the present embodiment. A temporary placement and routing process for the target circuit block is executed. Next, the wiring net information of the temporary placement and wiring performed in step S1 is read (step S1).
2) Calculate the wiring length of the read temporary wiring (Step S)
3) It is determined whether the wiring length is within a predetermined reference value (step S4). The reference value is set in advance. If the reference is violated, the process proceeds to step S5, and the signal delay time of the wiring net that violates the reference is calculated. Next, in step S7, an even number of inverters are inserted so as to divide the wiring violating the standard at equal intervals, and tentative placement wiring is performed.
Returning to step 5, the delay time is calculated for the provisionally placed wiring with the inverter inserted. The inverter insertion temporary placement wiring in step S7 and the delay time calculation in step S5 are repeated a preset number of times X times for each length of the reference violation wiring (step S5).
6) Increase the number of inverters inserted. For example, if X = 3 is determined from the standard violation wiring length, step S
The tentative placement and routing of the inverter 7 performs the case of inserting two inverters, the case of inserting four inverters, and the case of inserting six inverters, and performs the delay time calculation of step S5 for each case. Whether or not the processing of steps S7 and S5 has been repeated X times is performed in step S6.

If it is determined in step S6 that the repetition of the processing in steps S7 and S5 has been completed X times, the process proceeds to step S8,
The provisional placement wiring with the minimum delay time is selected from the delay time of the inverter insertion provisional placement wiring calculated in step S5 and the delay time of the wiring violating the criteria in step S4. next,
In step S9, a placement and wiring process for actually inserting an inverter is performed.

Next, a description will be given of a measurement example of the delay time improvement by the inverter insertion process in the semiconductor integrated circuit arrangement and wiring method according to the present embodiment.

Here, as a test sample, a P channel M having a gate length L of 0.25 μm and a gate width UP of 10 μm was used.
A CMOS circuit having a basic configuration including an OS transistor and an N-channel MOS transistor having a gate length L of 0.25 μm and a gate width UN of 12 μm was used. The power supply voltage and the input signal voltage are 2.5V, and the frequency of the input signal is 1 × 10
Using a rectangular wave of ⁷ (10 M) Hz, the delay time was measured at the amplitude point of the input and output voltage of 1.25 V (1/2).

In the configuration shown in FIG. 4, when the inverter 11 having a gate width 9 times that of the basic configuration is used as the output stage of the preceding circuit block 1 and the wiring length l of the wiring W1 is 40 mm, the delay time is 4.49 ns. Met.

Next, referring to FIG. 5B, a description will be given of a measurement example of the delay time improvement in the case where the conventional buffer gate is inserted. Has the same gate width as the basic configuration, and the inverter 32 at the subsequent stage has a gate width three times that of the basic configuration. The positions where the wirings W2 and W3 have the same length are set as the insertion positions of the buffer gates 3. Due to the insertion of the buffer gate 3, the delay time is 2.79.
ns.

Next, referring to FIG. 1 again, a description will be given of a measurement example of the delay time improvement when the inverter is inserted according to the present embodiment. The inserted inverters 4 and 5 have respective gate widths U4 and U5. Was twice as large as Therefore, the gate widths of the inserted inverters 4 and 5 are equal to the sum of the gate widths of the above-mentioned conventional buffer gates 3, and the driving capability and the power consumption are also equal. In this case, the measured value of the delay time is reduced to 2.57 ns, and the above-mentioned conventional 2.79 is used.
ns.

Next, a second embodiment of the present invention will be described with reference to FIG. 3, which is similar to FIG. The difference from the first embodiment is that the method of the temporary insertion and placement of the inverter in step S7 is different, and the former circuit block 1, the inverters 4 and 5 of the first embodiment are replaced with the former circuit block. 1 is a circuit in which the gate width U1 of the inverter 11 in the output stage before the inverter is inserted and the total UT of the gate widths of the inverters 11A in the output stage of the inverter and the output stage of the preceding circuit block 1A after the inverter insertion are set to be equal. Block 1A and inverters 4A and 5A.

Therefore, the gate widths U1A, U4A, U5A of the circuit block 1A and the inverters 4A, 5A, respectively.
, The following equation is established.

U1 = U1A + U4A + U5A (6) Further, similarly to the first embodiment, each wiring W5, W6,
The wiring length of W7 is 1/3, which is obtained by dividing the entire wiring length 1 into three equal parts.

Next, with reference to FIG. 3, a description will be given of a measurement example of the delay time improvement when the inverter is inserted according to the present embodiment under the same conditions as those of the conventional and the first embodiments. As described above, the inverter 11 in the output stage of the circuit element 1 has a gate width U1 which is nine times the basic configuration as described above, so that the inserted inverters 4A, 5A and 11A have respective gate widths U4A, U5A, U1.
A is three times the basic configuration. Therefore, the sum of the gate widths of these inverters before and after the insertion of the inverter is equal, and the power consumption is also equal. The measured value of the delay time in this case is 2.4.
8 ns. Therefore, the delay time can be reduced as compared with the related art without increasing power consumption.

In the present embodiment, the wiring length cannot be divided at equal intervals, which is ideal, and the allowable range of the wiring length of 140 mm is set to 20% with respect to 1E = 13.3 mm in the case of equal spacing division. l5 = 16mm, l6 = 13mm,
When divided into 17 = 11 mm , the delay time is 2.60 n
s, and the delay time can be reduced as compared with the conventional case.

[0038]

As described above, according to the semiconductor integrated circuit and the method of arranging and wiring the same according to the present invention, the wiring between the former-stage circuit block and the latter-stage circuit block is divided at equal intervals.
By even number inserting the CMOS inverter, equally disperse the wiring load in each CMOS inverter, the CM
Since the sum of the delay time of the OS inverter and the delay time due to the wiring length of the divided wiring can be made smaller than the signal propagation time due to the wiring length of the wiring, there is an effect that the delay time can be efficiently reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a flowchart illustrating an example of an operation in the method of arranging and wiring a semiconductor integrated circuit according to the present embodiment;

FIG. 3 is a block diagram showing a second embodiment of the semiconductor integrated circuit of the present invention.

FIG. 4 is a block diagram illustrating an example of a circuit subject to delay time compensation.

FIG. 5 is a block diagram showing an example of a conventional semiconductor integrated circuit and details thereof.

FIG. 6 is a flowchart showing an example of an operation in a conventional method for arranging and wiring semiconductor integrated circuits.

[Explanation of symbols]

1, 1A, 2 Circuit block 3 Buffer gate 4, 4A, 5, 5A, 11, 11A, 31, 32 Inverter W1 to W3, W5 to W7 Wiring

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit comprising complementary MOS transistor circuit cells and connecting a first circuit function block on a signal source side and a second circuit function block on a signal reception side by wiring to form a desired logic circuit, An even number of first inverters inserted so as to divide the wiring between the first circuit block and the second circuit block at substantially equal intervals,
Making the sum of the delay time of the even number of first inverters and the delay time of the divided wiring due to the second wiring length smaller than the signal delay time of the first wiring length of the wiring;
MOS constituting each of the even number of first inverters
The sum of the gate width of the transistor and the gate width of the MOS transistor of the second inverter in the output stage of the first circuit block is equal to the first circuit block before the insertion of the even number of first inverters. Of the third inverter of
A semiconductor integrated circuit having a gate width equal to that of an OS transistor.