JPH05102622A - Printed wiring board and inspection apparatus therefor - Google Patents

Printed wiring board and inspection apparatus therefor

Info

Publication number
JPH05102622A
JPH05102622A JP28953891A JP28953891A JPH05102622A JP H05102622 A JPH05102622 A JP H05102622A JP 28953891 A JP28953891 A JP 28953891A JP 28953891 A JP28953891 A JP 28953891A JP H05102622 A JPH05102622 A JP H05102622A
Authority
JP
Japan
Prior art keywords
printed wiring
characteristic impedance
wiring board
layer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28953891A
Other languages
Japanese (ja)
Inventor
Yoshiaki Umezawa
義明 梅沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28953891A priority Critical patent/JPH05102622A/en
Publication of JPH05102622A publication Critical patent/JPH05102622A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits

Abstract

PURPOSE:To provide a printed wiring board which can easily undergo the measurement of characteristic impedance and an inspection apparatus for easily deciding pass/fail of the printed wiring board. CONSTITUTION:A printed wiring board provides independent patterns 2, 6 in the same width as a signal pattern on a signal layer, signal layer connecting through holes 3, 7 at the end point of the independent patterns and also provides therein through holes 4, 5 connected to GND layer and power supply layer. An inspection apparatus comprises probe pins 8 corresponding to through holes of this printed wiring board, a characteristic impedance measuring means 10, a characteristic impedance setting means 11 for setting a target value, a comparison means 12 for deciding pass/fail by comparing measured data of the characteristic impedance measuring means with the target value and a display means 13 for displaying the decision results. Therefore, impedance measurement can be realized easily to decide pass/fail without complicated waveform measurement and computation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線基板及び
その特性インピーダンスの測定によりプリント配線基板
の良否判定を行う検査装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and an inspection device for determining the quality of the printed wiring board by measuring its characteristic impedance.

【0002】[0002]

【従来の技術】近年、デバイス技術の発展により、スイ
ッチングスピードの高速化が進み、それに伴いデバイス
の入出力インピーダンスと、それを実装するプリント配
線基板の特性インピーダンスとの不一致がディレータイ
ム増加をまねき、装置性能の障害になってきている。そ
こで、従来ではデバイスとプリント配線基板の特性イン
ピーダンスの整合を取るために、プリント配線基板の信
号パターン幅及び電源GNDと信号層間厚を調整してい
るが、プリント配線基板製造時のバラツキにより一種一
様になってしまい、性能不良のプリント配線基板が混入
する恐れがあった。
2. Description of the Related Art In recent years, due to the progress of device technology, the switching speed has been increased, and the mismatch between the input / output impedance of the device and the characteristic impedance of the printed wiring board on which it is mounted leads to an increase in the delay time. It is becoming an obstacle to device performance. Therefore, conventionally, the signal pattern width of the printed wiring board and the power supply GND and the signal interlayer thickness are adjusted to match the characteristic impedance of the device and the printed wiring board. As a result, a printed wiring board having poor performance may be mixed.

【0003】[0003]

【発明が解決しようとする課題】上述したような性能不
良のプリント配線基板の混入を防止するためには、1枚
ごとに特性インピーダンスを測定して良否判定を行えば
良いが、従来のプリント配線基板の電気的特性の良否
は、論理接続に使用している信号パターンから配線長の
長いパターンを選択し、特性インピーダンスの判明して
いるケーブル等による反射波測定により信号パターンの
特性インピーダンスを算出することによって判断してい
たので、検査に長時間を要し実際の運用に耐えられない
という問題があった。このため、プリント配線基板の特
性インピーダンス測定を実施しないことが多く、不良プ
リント配線基板混入による装置の性能及び信頼性悪化を
まねく等の問題点があった。
In order to prevent the above-described defective printed wiring board from being mixed in, it is sufficient to measure the characteristic impedance of each sheet to determine whether the printed wiring board is good or bad. To determine the electrical characteristics of the board, select a pattern with a long wiring length from the signal pattern used for logical connection, and calculate the characteristic impedance of the signal pattern by measuring the reflected wave using a cable or the like with a known characteristic impedance. Since it was decided based on this, there was a problem that the inspection took a long time and could not withstand actual operation. For this reason, the characteristic impedance of the printed wiring board is often not measured, and there is a problem in that the performance and reliability of the device are deteriorated due to mixing of a defective printed wiring board.

【0004】本発明は、上記問題点にかんがみてなされ
たもので、容易に特性インピーダンスの測定が行えるプ
リント配線基板及びその良否判定を容易に行うことがで
きる検査装置の提供を目的とする。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a printed wiring board whose characteristic impedance can be easily measured, and an inspection apparatus which can easily determine the quality of the printed wiring board.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に本発明のプリント配線基板は、信号パターンを形成し
た信号層とGND層及び電源層を積層してなるプリント
配線基板において、前記信号層に信号パターンと同一幅
の独立パターンを形成し、該独立パターンの端点に信号
層接続スルーホールを設け、かつ該信号層接続スルーホ
ールの近傍にGND層及び電源層に接続したスルーホー
ルをそれぞれ設けた構成としてある。また、上記目的を
達成するために本発明の検査装置は、信号層に信号パタ
ーンと同一幅の独立パターンを形成し、該独立パターン
の端点に信号層接続スルーホールを設け、かつ該信号層
接続スルーホールの近傍にGND層及び電源層に接続し
たスルーホールをそれぞれ設けたプリント配線基板の各
スルーホールに対応した複数のプローブピンと、特性イ
ンピーダンスを算出する特性インピーダンス測定部と、
特性インピーダンスの目標値の上限下限を設定する特性
インピーダンス設定部と、前記特性インピーダンス測定
部の測定データを前記特性インピーダンス設定部の目標
値と比較して良否の判定を行う比較部と、該比較部の判
定結果を表示する表示部とを備えた構成としてある。
In order to achieve the above object, a printed wiring board of the present invention is a printed wiring board in which a signal layer having a signal pattern, a GND layer and a power supply layer are laminated. An independent pattern having the same width as the signal pattern is formed, a signal layer connecting through hole is provided at an end point of the independent pattern, and through holes connected to the GND layer and the power supply layer are provided near the signal layer connecting through hole, respectively. It has a different configuration. In order to achieve the above-mentioned object, the inspection device of the present invention forms an independent pattern having the same width as the signal pattern on the signal layer, provides signal layer connection through holes at the end points of the independent pattern, and connects the signal layer. A plurality of probe pins corresponding to the through holes of the printed wiring board, each having a through hole connected to the GND layer and a power supply layer in the vicinity of the through hole, and a characteristic impedance measuring unit for calculating a characteristic impedance,
A characteristic impedance setting unit that sets the upper and lower limits of the target value of the characteristic impedance, a comparison unit that compares the measurement data of the characteristic impedance measurement unit with the target value of the characteristic impedance setting unit, and determines whether the quality is good or bad, and the comparison unit. And a display unit that displays the determination result of.

【0006】[0006]

【作用】プリント配線基板のインピーダンス測定に際し
ては、論理接続に使用している信号パターンから配線長
の長いパターンを選別する必要がなく、独立パターンの
信号層接続スルーホールとGNDまたは電源接続スルー
ホールを測定ポイントに選定すればよい。検査装置で
は、特性インピーダンス測定部からの測定データを比較
部が特性インピーダンス測定部に設定してある目標値と
比較してプリント配線基板の良否を判定し、その結果を
表示部に表示する。
When the impedance of the printed wiring board is measured, it is not necessary to select a pattern having a long wiring length from the signal pattern used for the logical connection, and the signal layer connection through hole and the GND or power supply connection through hole of the independent pattern are formed. It should be selected as the measurement point. In the inspection device, the comparison unit compares the measurement data from the characteristic impedance measurement unit with a target value set in the characteristic impedance measurement unit to determine the quality of the printed wiring board, and displays the result on the display unit.

【0007】[0007]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1は本発明の一実施例によるプリント
配線基板の平面図である。本プリント配線基板1の表信
号層には、表信号層独立パターン2が配線され、その端
点に表信号層接続スルーホール3が設けられている。ま
た、表信号層接続スルーホール3の近傍には、GNDが
供給されるGND接続スルーホール4aと電源が供給さ
れる電源接続スルーホール5aが設けられている。同様
に、プリント配線基板1の裏信号層には、裏信号層独立
パターン6、裏信号層接続スルーホール7及びGND接
続スルーホール4b、電源接続スルーホール5bが設け
られている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a printed wiring board according to an embodiment of the present invention. On the surface signal layer of the present printed wiring board 1, the surface signal layer independent pattern 2 is wired, and the surface signal layer connection through hole 3 is provided at the end point thereof. In the vicinity of the surface signal layer connecting through hole 3, a GND connecting through hole 4a to which GND is supplied and a power connecting through hole 5a to which power is supplied are provided. Similarly, the back signal layer of the printed wiring board 1 is provided with the back signal layer independent pattern 6, the back signal layer connection through hole 7, the GND connection through hole 4b, and the power supply connection through hole 5b.

【0008】上述のように構成される本プリント配線基
板1において、各信号層の特性インピーダンスを測定す
る場合、各表裏の表信号層接続スルーホール3、裏信号
層接続スルーホール7と、GND接続スルーホール4
a,4b、電源接続スルーホール5a,5bを測定ポイ
ントに選定すればよく、論理接続に使用している信号パ
ターンから配線長の長いパターンを選別する手間が省
け、容易に選定可能となる。
When measuring the characteristic impedance of each signal layer in the printed wiring board 1 configured as described above, the front and back signal layer connection through holes 3, the back signal layer connection through holes 7, and the GND connection are used. Through hole 4
It suffices to select a, 4b and the power supply connection through holes 5a, 5b as the measurement points, which saves the trouble of selecting a pattern having a long wiring length from the signal pattern used for logical connection, and can be easily selected.

【0009】図2は本発明の一実施例による検査装置の
構成ブロック図である。本検査装置は、特性インピーダ
ンス測定部10と、特性インピーダンス設定部11と、
比較部12と、表示部13とで構成される。特性インピ
ーダンス測定部10には、図1に示したプリント配線基
板1の各スルーホールに対応して6本のプローブピン8
がケーブル9によってそれぞれ接続されている。このプ
ローブピン8をプリント配線基板1の表信号層接続スル
ーホール3、裏信号層接続スルーホール7、GND接続
スルーホール4a,4b、電源接続スルーホール5a,
5bに差込むことにより検査を実行する。
FIG. 2 is a block diagram showing the arrangement of an inspection apparatus according to an embodiment of the present invention. The inspection apparatus includes a characteristic impedance measuring unit 10, a characteristic impedance setting unit 11,
It is composed of a comparison unit 12 and a display unit 13. The characteristic impedance measuring unit 10 has six probe pins 8 corresponding to each through hole of the printed wiring board 1 shown in FIG.
Are respectively connected by cables 9. The probe pin 8 is connected to the front signal layer connecting through hole 3 of the printed wiring board 1, the back signal layer connecting through hole 7, the GND connecting through holes 4a and 4b, and the power connecting through hole 5a,
The test is performed by plugging in 5b.

【0010】特性インピーダンスは、プリント配線基板
1の被測定信号層が面しているGNDあるいは電源層に
対するキャパシタンスとインダクタンスを測定して計算
することにより算出できるが、信号層とGND、電源層
との層間距離が小さい程特性インピーダンスは低下す
る。そこで、特性インピーダンス測定部10は、被測定
信号層とGND層間及び被測定信号層と電源層間のキャ
パシタンスとインダクタンス測定及びインピーダンス計
算を行い、低い方の値を被測定信号層の特性インピーダ
ンスとする選択機能と、さらに測定信号層番号付加機能
を有している。そのため、被測定信号層がGND層に面
しているか、電源層に面しているか分らないプリント配
線基板でも測定可能になっている。
The characteristic impedance can be calculated by measuring and calculating the capacitance and the inductance with respect to the GND or the power supply layer facing the signal layer to be measured of the printed wiring board 1. However, the characteristic impedance of the signal layer, the GND, and the power supply layer can be calculated. The smaller the interlayer distance, the lower the characteristic impedance. Therefore, the characteristic impedance measuring unit 10 measures the capacitance and inductance between the signal layer under measurement and the GND layer and between the signal layer under measurement and the power supply layer and calculates the impedance, and selects the lower value as the characteristic impedance of the signal layer under measurement. In addition to the function, it has a measurement signal layer number addition function. Therefore, it is possible to perform measurement even on a printed wiring board that does not know whether the measured signal layer faces the GND layer or the power supply layer.

【0011】また、特性インピーダンスの目標値は、そ
の上限下限の良好範囲の値を各信号層毎に特性インピー
ダンス設定部11に設定してある。比較部12は、特性
インピーダンス測定部10の各信号層データと特性イン
ピーダンス設定部11の目標値を比較判定し、表示部1
3で各信号層毎の結果を表示する。これにより、面倒な
波形測定及び計算をすることなく容易に良否の判定が可
能になる。以上、好ましい実施例をあげて本発明を説明
したが、本発明は上記実施例に限定されるものではな
い。
Further, the target value of the characteristic impedance is set in the characteristic impedance setting section 11 for each signal layer such that the upper and lower limits are in a good range. The comparison unit 12 compares and determines each signal layer data of the characteristic impedance measuring unit 10 and the target value of the characteristic impedance setting unit 11, and the display unit 1
At 3, the results for each signal layer are displayed. As a result, it is possible to easily determine the quality without performing troublesome waveform measurement and calculation. The present invention has been described above with reference to the preferred embodiments, but the present invention is not limited to the above embodiments.

【0012】[0012]

【発明の効果】以上説明したように、本発明のプリント
配線基板は、信号層接続スルーホールとGND接続スル
ーホール及び電源接続スルーホールを測定ポイントに選
定すればよく、論理接続に使用している信号パターンか
ら配線長の長いパターンを選別する手間が省け、インピ
ーダンス測定が容易に行えるようになる。また、本発明
のプリント配線基板の検査装置は、特性インピーダンス
測定部からの測定データを比較部が特性インピーダンス
測定部に設定してある目標値と比較してプリント配線基
板の良否を判定し、その結果を表示部に表示するので、
面倒な波形測定及び計算をすることなく容易に良否の判
定が可能になる。
As described above, in the printed wiring board of the present invention, the signal layer connection through hole, the GND connection through hole and the power supply connection through hole may be selected as the measurement points, and they are used for the logical connection. This eliminates the need to select a pattern having a long wiring length from the signal pattern, and makes impedance measurement easy. Further, the printed wiring board inspection apparatus of the present invention determines the quality of the printed wiring board by comparing the measurement data from the characteristic impedance measurement unit with the target value set in the characteristic impedance measurement unit by the comparison unit, Since the result is displayed on the display,
It becomes possible to easily judge pass / fail without performing troublesome waveform measurement and calculation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によるプリント配線基板の平
面図である。
FIG. 1 is a plan view of a printed wiring board according to an exemplary embodiment of the present invention.

【図2】本発明の一実施例による検査装置の構成ブロッ
ク図である。
FIG. 2 is a configuration block diagram of an inspection apparatus according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…プリント配線基板 2…表信号層独立パターン 3…表信号層接続スルーホール 4a,4b…GND接続スルーホール 5a,5b…電源接続スルーホール 6…裏信号層独立パターン 7…裏信号層接続スルーホール 8…プローブピン 9…ケーブル 10…特性インピーダンス測定部 11…特性インピーダンス設定部 12…比較部 13…表示部 1 ... Printed wiring board 2 ... Front signal layer independent pattern 3 ... Front signal layer connection through hole 4a, 4b ... GND connection through hole 5a, 5b ... Power connection through hole 6 ... Back signal layer independent pattern 7 ... Back signal layer connection through Hall 8 ... Probe pin 9 ... Cable 10 ... Characteristic impedance measurement unit 11 ... Characteristic impedance setting unit 12 ... Comparison unit 13 ... Display unit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 信号パターンを形成した信号層とGND
層及び電源層を積層してなるプリント配線基板におい
て、 前記信号層に信号パターンと同一幅の独立パターンを形
成し、該独立パターンの端点に信号層接続スルーホール
を設け、かつ該信号層接続スルーホールの近傍にGND
層及び電源層に接続したスルーホールをそれぞれ設けた
ことを特徴とするプリント配線基板。
1. A signal layer on which a signal pattern is formed and GND.
In a printed wiring board formed by stacking layers and power supply layers, an independent pattern having the same width as a signal pattern is formed on the signal layer, a signal layer connection through hole is provided at an end point of the independent pattern, and the signal layer connection through is formed. GND near the hall
A printed wiring board having through holes connected to the power supply layer and the power supply layer, respectively.
【請求項2】 信号層に信号パターンと同一幅の独立パ
ターンを形成し、該独立パターンの端点に接続スルーホ
ールを設け、かつ該接続スルーホールの近傍にGND層
及び電源層に接続したスルーホールをそれぞれ設けたプ
リント配線基板の各スルーホールに対応した複数のプロ
ーブピンと、特性インピーダンスを算出する特性インピ
ーダンス測定部と、特性インピーダンスの目標値の上限
下限を設定する特性インピーダンス設定部と、前記特性
インピーダンス測定部の測定データを前記特性インピー
ダンス設定部の目標値と比較して良否の判定を行う比較
部と、該比較部の判定結果を表示する表示部とを備えて
なることを特徴とするプリント配線基板の検査装置。
2. A through hole in which an independent pattern having the same width as a signal pattern is formed on a signal layer, a connection through hole is provided at an end point of the independent pattern, and the GND layer and a power supply layer are connected in the vicinity of the connection through hole. A plurality of probe pins corresponding to the respective through holes of the printed wiring board, the characteristic impedance measuring section for calculating the characteristic impedance, the characteristic impedance setting section for setting the upper and lower limits of the target value of the characteristic impedance, and the characteristic impedance A printed wiring comprising: a comparison unit that compares the measurement data of the measurement unit with a target value of the characteristic impedance setting unit to determine pass / fail; and a display unit that displays the determination result of the comparison unit. Board inspection device.
JP28953891A 1991-10-09 1991-10-09 Printed wiring board and inspection apparatus therefor Pending JPH05102622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28953891A JPH05102622A (en) 1991-10-09 1991-10-09 Printed wiring board and inspection apparatus therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28953891A JPH05102622A (en) 1991-10-09 1991-10-09 Printed wiring board and inspection apparatus therefor

Publications (1)

Publication Number Publication Date
JPH05102622A true JPH05102622A (en) 1993-04-23

Family

ID=17744541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28953891A Pending JPH05102622A (en) 1991-10-09 1991-10-09 Printed wiring board and inspection apparatus therefor

Country Status (1)

Country Link
JP (1) JPH05102622A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002067638A1 (en) * 2001-02-19 2002-08-29 Sony Corporation Printed wiring board, multilayer printed wiring board, and, method of detecting foreign matter and voids in inner layer of multilayer printed wiring board
JP2002359451A (en) * 2001-05-30 2002-12-13 Ibiden Co Ltd Printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002067638A1 (en) * 2001-02-19 2002-08-29 Sony Corporation Printed wiring board, multilayer printed wiring board, and, method of detecting foreign matter and voids in inner layer of multilayer printed wiring board
JP2002359451A (en) * 2001-05-30 2002-12-13 Ibiden Co Ltd Printed wiring board

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